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61. 发明授权

US06924181B2 Strained silicon layer semiconductor product employing strained insulator layer 有权
标题翻译：应变应变绝缘体层的硅层半导体产品
公开(公告)号：US06924181B2
公开(公告)日：2005-08-02
申请号：US10366220
申请日：2003-02-13
申请人： Chien-Chao Huang , Chao-Hsiung Wang , Chung-Hu Ge , Wen-Chin Lee , Chen Ming Hu
发明人： Chien-Chao Huang , Chao-Hsiung Wang , Chung-Hu Ge , Wen-Chin Lee , Chen Ming Hu
IPC分类号： H01L21/28 , H01L29/778 , H01L21/336
CPC分类号： H01L29/7842 , H01L21/2807 , H01L29/7782 , Y10S438/933
摘要： A strained silicon layer fabrication and a method for fabrication thereof employ a strained insulator material layer formed over a strained silicon layer in turn formed upon a strained silicon-germanium alloy material layer which is formed upon a relaxed material substrate. The strained insulator material layer provides increased fabrication options which provide for enhanced fabrication efficiency when fabricating the strained silicon layer fabrication.
摘要翻译：应变硅层制造及其制造方法采用在应变硅层上形成的应变绝缘体材料层，其又形成在形成于松弛材料基板上的应变硅 - 锗合金材料层上。应变绝缘体材料层提供增加的制造选择，其在制造应变硅层制造时提供增强的制造效率。

62. 发明授权

US08120767B2 Mask making decision for manufacturing (DFM) on mask quality control 有权
标题翻译：面罩制作决策（DFM）对面罩质量控制
公开(公告)号：US08120767B2
公开(公告)日：2012-02-21
申请号：US12048043
申请日：2008-03-13
申请人： Chih-Chiang Tu , Chien-Chao Huang
发明人： Chih-Chiang Tu , Chien-Chao Huang
IPC分类号： G01N21/00 , G06K9/00
CPC分类号： G03F1/84
摘要： The present disclosure provide a method for making a mask. The method includes assigning a plurality of pattern features to different data types; writing the plurality of pattern features on a mask; inspecting the plurality of pattern features with different inspection sensitivities according to assigned data types; and repairing the plurality of pattern features on the mask according to the inspecting of the plurality of pattern features.
摘要翻译：本公开提供了一种制造掩模的方法。该方法包括将多个模式特征分配给不同的数据类型; 在掩模上写入多个图案特征; 根据分配的数据类型检查具有不同检查灵敏度的多个图案特征; 以及根据所述多个图案特征的检查来修复所述掩模上的所述多个图案特征。

63. 发明授权

US07871742B2 Method for controlling phase angle of a mask by post-treatment 有权
标题翻译：通过后处理控制面罩的相位角的方法
公开(公告)号：US07871742B2
公开(公告)日：2011-01-18
申请号：US11697015
申请日：2007-04-05
申请人： Chun-Lang Chen , Tran-Hui Shen , Fei-Gwo Tsai , Chien-Chao Huang
发明人： Chun-Lang Chen , Tran-Hui Shen , Fei-Gwo Tsai , Chien-Chao Huang
IPC分类号： G03F1/00
CPC分类号： G03F1/26 , G03F1/32
摘要： A method for controlling phase angle of a mask is provided. A mask comprising a substrate and an absorber is formed. A nitrogen-containing plasma treatment is performed on the mask to reduce the phase angle. Alternatively, a nitrogen-containing plasma treatment is performed on the mask, followed by a vacuum ultraviolet treatment to form a passivated layer on the mask.
摘要翻译：提供了一种用于控制掩模的相位角的方法。形成包括基板和吸收体的掩模。对掩模进行含氮等离子体处理以减小相位角。或者，对掩模进行含氮等离子体处理，然后进行真空紫外线处理，以在掩模上形成钝化层。

64. 发明授权

US07571421B2 System, method, and computer-readable medium for performing data preparation for a mask design 有权
标题翻译：用于执行掩模设计的数据准备的系统，方法和计算机可读介质
公开(公告)号：US07571421B2
公开(公告)日：2009-08-04
申请号：US11738844
申请日：2007-04-23
申请人： Peng-Ren Chen , Chien-Chao Huang , Chih-Chiang Tu
发明人： Peng-Ren Chen , Chien-Chao Huang , Chih-Chiang Tu
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method, computer-readable medium, and system for performing data preparation are provided. An integrated circuit design is received, and a plurality of pre-optical proximity correction processes are invoked such that the plurality of pre-optical proximity correction processes are performed in parallel. An optical proximity correction process is invoked in response to a determination that each of the plurality of pre-optical proximity correction processes have completed. A post-optical proximity correction process is invoked in response to a determination that the optical proximity correction process has completed.
摘要翻译：提供了一种用于执行数据准备的方法，计算机可读介质和系统。接收集成电路设计，并且调用多个预光学邻近校正处理，使得并行地执行多个预光学邻近校正处理。响应于多个预光学邻近校正处理中的每一个已经完成的确定来调用光学邻近校正处理。响应于光学邻近校正处理已经完成的确定，调用后光学邻近校正处理。

65. 发明申请

US20070235835A1 Shallow trench isolation structure for semiconductor device 有权
标题翻译：用于半导体器件的浅沟槽隔离结构
公开(公告)号：US20070235835A1
公开(公告)日：2007-10-11
申请号：US11809519
申请日：2007-05-31
申请人： Chih-Hsin Ko , Chung-Hu Ke , Chien-Chao Huang
发明人： Chih-Hsin Ko , Chung-Hu Ke , Chien-Chao Huang
IPC分类号： H01L29/00
CPC分类号： H01L29/0847 , H01L21/76232 , H01L21/823481 , H01L29/66636 , H01L29/7834
摘要： A semiconductor device provides a transistor adjacent an isolation trench. The device may be formed by producing isolation trenches in a semiconductor substrate, filling the trenches with a filler material, creating voids near top edges of the trenches and annealing by a gaseous ambient to reflow the edges of the trenches causing the edges to become rounded and overhang the trench. The filler material may be a dielectric. The transistors which are then formed in close proximity to the trenches may include source/drain regions formed in the rounded portion of the semiconductor substrate that overhangs the trench.
摘要翻译：半导体器件提供与隔离沟槽相邻的晶体管。该器件可以通过在半导体衬底中产生隔离沟槽，用填充材料填充沟槽，在沟槽的顶部边缘附近产生空隙，并通过气态环境进行退火以使沟槽的边缘回流，从而使边缘变圆; 突出沟槽。填充材料可以是电介质。然后形成在靠近沟槽的晶体管可以包括形成在半导体衬底的圆形部分中的突出于沟槽的源极/漏极区域。

66. 发明授权

US07119440B2 Back end IC wiring with improved electro-migration resistance 有权
标题翻译：后端IC布线具有改善的电迁移电阻
公开(公告)号：US07119440B2
公开(公告)日：2006-10-10
申请号：US10813784
申请日：2004-03-30
申请人： Chien-Chao Huang
发明人： Chien-Chao Huang
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L21/76838 , H01L21/76877 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： A multi-level semiconductor device wiring interconnect structure and method of forming the same to improve electrical properties and reliability of wiring interconnects including an electromigration resistance and electrical resistance, the method including forming a dielectric insulating layer over a conductive portion; forming a via opening in closed communication with the conductive portion; forming a first barrier layer to line the via opening; forming a layer of AlCu according to a sputtering process to fill the via opening to form an AlCu via including a portion overlying the first dielectric insulating layer; and, photolithographically patterning and dry etching the portion to form an AlCu interconnect line over the AlCu via.
摘要翻译：一种多级半导体器件布线互连结构及其形成方法，以改善包括电迁移电阻和电阻的布线互连的电性能和可靠性，所述方法包括在导电部分上形成介电绝缘层; 形成与所述导电部分密封连通的通孔; 形成第一阻挡层以使所述通孔开口; 根据溅射工艺形成AlCu层以填充通孔以形成包含覆盖在第一介电绝缘层上的部分的AlCu; 并且光刻地图案化和干蚀刻该部分以在AlCu通孔上形成AlCu互连线。

67. 发明授权

US06255023B1 Method of manufacturing binary phase shift mask 有权
标题翻译：制造二元相移掩模的方法
公开(公告)号：US06255023B1
公开(公告)日：2001-07-03
申请号：US09434046
申请日：1999-11-04
申请人： Chien-Chao Huang , Michael W C Huang , Juan-Yuan Wu
发明人： Chien-Chao Huang , Michael W C Huang , Juan-Yuan Wu
IPC分类号： G03F900
CPC分类号： G03F1/32
摘要： A method of manufacturing a binary phase shift photomask. A phase shift layer and a mask layer are sequentially formed over a transparent substrate. The mask layer and the phase shift layer are patterned to form a plurality of first openings and a plurality of second openings that expose a portion of the transparent substrate. The mask layer is patterned to form a layer of mask material around the edges of the first openings. All first openings occupy an area greater than a preset minimum area while all second openings occupy an area greater than the preset minimum area. The mask layer only surrounds the first openings while the phase shift layer surrounds both the first and the second openings.
摘要翻译：一种制造二进制相移光掩模的方法。在透明基板上依次形成相移层和掩模层。图案化掩模层和相移层以形成多个第一开口和暴露透明基板的一部分的多个第二开口。图案化掩模层以在第一开口的边缘周围形成掩模材料层。所有第一开口占据大于预设最小面积的区域，而所有第二开口占据大于预设最小面积的区域。掩模层仅围绕第一开口，而相移层围绕第一和第二开口。

68. 发明授权

US07504652B2 Phase change random access memory 有权
标题翻译：相变随机存取存储器
公开(公告)号：US07504652B2
公开(公告)日：2009-03-17
申请号：US11180430
申请日：2005-07-13
申请人： Chien-Chao Huang
发明人： Chien-Chao Huang
IPC分类号： H01L47/00
CPC分类号： H01L45/06 , H01L45/122 , H01L45/1233 , H01L45/126 , H01L45/144
摘要： A phase change memory device with a reduced phase change volume and lower drive current and a method for forming the same are provided. The method includes forming a bottom insulating layer comprising a bottom electrode contact, forming a bottom electrode film on the bottom electrode contact, forming an anti-reflective coating (ARC) film on the bottom electrode film, patterning and etching the ARC film and the bottom electrode film to form a bottom electrode comprising a side edge, and forming a phase change material portion on the ARC film and the bottom insulating layer, wherein the phase change material portion physically contacts the side edge of the bottom electrode. The method further includes forming a top electrode on the phase change material portion, and forming a top electrode contact on the top electrode.
摘要翻译：提供了具有减小的相变容积和较低驱动电流的相变存储器件及其形成方法。该方法包括形成底部绝缘层，该底部绝缘层包括底部电极触点，在底部电极触点上形成底部电极膜，在底部电极膜上形成抗反射涂层（ARC）膜，对ARC膜和底部形成包括侧边缘的底部电极，并且在所述ARC膜和所述底部绝缘层上形成相变材料部分，其中所述相变材料部分物理接触所述底部电极的侧边缘。该方法还包括在相变材料部分上形成顶部电极，以及在顶部电极上形成顶部电极接触。

69. 发明申请

US20080248404A1 Method for Controlling Phase Angle of a Mask by Post-Treatment 有权
标题翻译：通过后处理控制面膜相位角的方法
公开(公告)号：US20080248404A1
公开(公告)日：2008-10-09
申请号：US11697015
申请日：2007-04-05
申请人： Chun-Lang Chen , Tran-Hui Shen , Fei-Gwo Tsai , Chien-Chao Huang
发明人： Chun-Lang Chen , Tran-Hui Shen , Fei-Gwo Tsai , Chien-Chao Huang
IPC分类号： G03F1/00
CPC分类号： G03F1/26 , G03F1/32
摘要： A method for controlling phase angle of a mask is provided. A mask comprising a substrate and an absorber is formed. A nitrogen-containing plasma treatment is performed on the mask to reduce the phase angle. Alternatively, a nitrogen-containing plasma treatment is performed on the mask, followed by a vacuum ultraviolet treatment to form a passivated layer on the mask.
摘要翻译：提供了一种用于控制掩模的相位角的方法。形成包括基板和吸收体的掩模。对掩模进行含氮等离子体处理以减小相位角。或者，对掩模进行含氮等离子体处理，然后进行真空紫外线处理，以在掩模上形成钝化层。

70. 发明授权

US07312136B2 Method of fabricating a wafer with strained channel layers for increased electron and hole mobility for improving device performance 有权
标题翻译：制造具有应变通道层的晶片以提高电子和空穴迁移率以提高器件性能的方法
公开(公告)号：US07312136B2
公开(公告)日：2007-12-25
申请号：US10899270
申请日：2004-07-26
申请人： Chien-Chao Huang , Yee-Chia Yeo , Kuo-Nan Yang , Chun-Chieh Lin , Chenming Hu
发明人： Chien-Chao Huang , Yee-Chia Yeo , Kuo-Nan Yang , Chun-Chieh Lin , Chenming Hu
IPC分类号： H01L21/20
CPC分类号： H01L21/3247 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02658 , H01L21/02664 , H01L21/324 , H01L21/76259 , H01L29/1054
摘要： A method for making a SOI wafer with a strained silicon layer for increased electron and hole mobility is achieved. The method forms a porous silicon layer on a seed wafer. A H2 anneal is used to form a smooth surface on the porous silicon. A strain free (relaxed) epitaxial SixGe1-x layer is deposited and a bonding layer is formed. The seed wafer is then bonded to a handle wafer having an insulator on the surface. A spray etch is used to etch the porous Si layer resulting in a SOI handle wafer having portions of the porous Si layer on the relaxed SixGe1-x. The handle wafer is then annealed in H2 to convert the porous Si to a smooth strained Si layer on the relaxed SiGe layer of the SOI wafer.
摘要翻译：实现了制造具有用于增加电子和空穴迁移率的应变硅层的SOI晶片的方法。该方法在种子晶片上形成多孔硅层。使用H 2 H 2退火在多孔硅上形成光滑表面。沉积无应变的（松弛的）外延的Si 1 x 1-x层，并形成结合层。然后将种子晶片结合到在表面上具有绝缘体的手柄晶片。使用喷涂蚀刻来蚀刻多孔Si层，导致SOI处理晶片，其具有在松弛的Si 1 x 1-x x上的多孔Si层的部分。然后将手柄晶片在H 2 2中退火以将多孔Si转化为SOI晶片的松弛SiGe层上的平滑应变Si层。

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