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61. 发明申请

US20060033133A1 MRAM cell having shared configuration 有权
标题翻译：具有共享配置的MRAM单元
公开(公告)号：US20060033133A1
公开(公告)日：2006-02-16
申请号：US11053379
申请日：2005-02-08
申请人： Chi-Wen Liu , Kuo-Ching Chiang , Horng-Huei Tseng , Denny Tang
发明人： Chi-Wen Liu , Kuo-Ching Chiang , Horng-Huei Tseng , Denny Tang
IPC分类号： H01L29/94
CPC分类号： H01L27/228
摘要： A magnetic memory includes two first magnetic layers each oriented over a substrate, a second magnetic layer interposing the two first magnetic layers, and two dielectric layers each contacting the second magnetic layer and interposing the second magnetic layer and one of the two first magnetic layers. Each of the first and second magnetic layers and the dielectric layers may be oriented substantially perpendicular to the substrate or at an acute angle relative to the substrate.
摘要翻译：磁存储器包括两个分别定向在衬底上的第一磁性层，插入两个第一磁性层的第二磁性层和与第二磁性层接触并插入第二磁性层和两个第一磁性层之一的两个电介质层。第一和第二磁性层和电介质层中的每一个可以基本上垂直于衬底取向或相对于衬底成锐角。

62. 发明授权

US06958291B2 Interconnect with composite barrier layers and method for fabricating the same 有权
标题翻译：与复合阻挡层互连及其制造方法
公开(公告)号：US06958291B2
公开(公告)日：2005-10-25
申请号：US10654757
申请日：2003-09-04
申请人： Chen-Hua Yu , Horng-Huei Tseng , Syun-Ming Jang , Chenming Hu
发明人： Chen-Hua Yu , Horng-Huei Tseng , Syun-Ming Jang , Chenming Hu
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76846
摘要： Composite ALD-formed diffusion barrier layers. In a preferred embodiment, a composite conductive layer is composed of a diffusion barrier layer and/or a low-resistivity metal layer formed by atomic layer deposition (ALD) lining a damascene opening in dielectrics, serving as diffusion blocking and/or adhesion improvement. The preferred composite diffusion barrier layers are dual titanium nitride layers or dual tantalum nitride layers, triply laminar of tantalum, tantalum nitride and tantalum-rich nitride, or tantalum, tantalum nitride and tantalum, formed sequentially on the opening by way of ALD.
摘要翻译：复合ALD形成的扩散阻挡层。在优选实施例中，复合导电层由扩散阻挡层和/或由电介质中的镶嵌开口衬底的原子层沉积（ALD）形成的低电阻金属层组成，用作扩散阻挡和/或粘附改善。优选的复合扩散阻挡层是通过ALD在开口上依次形成的双氮化钛层或双氮化钽层，三层层状的钽，氮化钽和富钽的氮化物，或钽，氮化钽和钽。

63. 发明申请

US20050156156A1 Method of fabricating a non-floating body device with enhanced performance 有权
标题翻译：制造具有增强性能的非浮体装置的方法
公开(公告)号：US20050156156A1
公开(公告)日：2005-07-21
申请号：US11032403
申请日：2005-01-10
申请人： Horng-Huei Tseng , Jyh-Chyurn Guo , Chenming Hu , Da-Chi Lin
发明人： Horng-Huei Tseng , Jyh-Chyurn Guo , Chenming Hu , Da-Chi Lin
IPC分类号： H01L21/762 , H01L29/06 , H01L29/10
CPC分类号： H01L29/7842 , H01L21/76232 , H01L21/76264 , H01L21/76283 , H01L29/0653 , H01L29/1054 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： Provided is a semiconductor transistor device including a substrate having at least two regions, a semiconductive region extending to a first surface of the substrate and an insulative region extending to a second surface of the substrate. The semiconductor transistor device also includes a patterned semiconductor structure overlying both surfaces of the substrate. The patterned semiconductor structure includes a source or drain region overlying the second surface of the substrate. The semiconductor transistor device further includes a patterned gate structure overlying the patterned semiconductor structure.
摘要翻译：提供了一种半导体晶体管器件，其包括具有至少两个区域的衬底，延伸到衬底的第一表面的半导体区域和延伸到衬底的第二表面的绝缘区域。半导体晶体管器件还包括覆盖在衬底的两个表面上的图案化半导体结构。图案化的半导体结构包括覆盖在衬底的第二表面上的源极或漏极区域。半导体晶体管器件还包括覆盖图案化半导体结构的图案化栅极结构。

64. 发明申请

US20050077627A1 Copper wiring with high temperature superconductor (HTS) layer 有权
标题翻译：铜线与高温超导体（HTS）层
公开(公告)号：US20050077627A1
公开(公告)日：2005-04-14
申请号：US10684224
申请日：2003-10-10
申请人： Chen-Hua Yu , Horng-Huei Tseng , Chenming Hu , Chao-Hsiung Wang
发明人： Chen-Hua Yu , Horng-Huei Tseng , Chenming Hu , Chao-Hsiung Wang
IPC分类号： H01L21/768 , H01L23/532 , H01L21/4763 , H01L23/48
CPC分类号： H01L21/76846 , H01L21/76849 , H01L21/7685 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices and methods of forming the semiconductor devices using an HTS (High Temperature Superconductor) layer in combination with a typical diffusion layer between the dielectric material and the copper (or other metal) conductive wiring. The HTS layer includes a superconductor material comprised of barium copper oxide and a rare earth element. The rare earth element yttrium is particularly suitable. For semiconductor devices having other semiconductor circuits or elements above the wiring, a capping layer of HTS material is deposited over the wiring before a cover layer of dielectric is deposited.
摘要翻译：使用HTS（高温超导体）层与介电材料和铜（或其它金属）导电布线之间的典型扩散层组合形成半导体器件的半导体器件和方法。 HTS层包括由氧化钡钡和稀土元素构成的超导体材料。稀土元素钇特别适合。对于具有其它半导体电路或布线之上的元件的半导体器件，在沉积覆盖层的电介质之前，在布线上沉积HTS材料的覆盖层。

65. 发明授权

US06677224B2 Method of forming stacked gate for flash memories 有权
标题翻译：形成闪存存储堆叠栅的方法
公开(公告)号：US06677224B2
公开(公告)日：2004-01-13
申请号：US09976823
申请日：2001-10-12
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L213205
CPC分类号： H01L27/11521 , H01L21/76224 , H01L27/115
摘要： The method of the present invention includes the steps of forming doped regions in the semiconductor substrate. A pad oxide layer is formed on the semiconductor substrate. A masking layer is formed on the pad oxide layer. A masking layer, the pad oxide layer and the semiconductor substrate are patterned to form a trench therein. A gap-filling material is refilled into the trench and over the semiconductor substrate. A portion of the gap-filling material is removed to an upper surface of the masking layer. Next step is to remove the masking layer. A first conductive layer is formed along the surface of the substrate, then removing a portion of the first conductive layer to expose an upper surface of the gap-filling material. An inter polysilicon dielectric layer is formed on the first conductive layer and a second conductive layer is formed on the inter polysilicon dielectric layer.
摘要翻译：本发明的方法包括在半导体衬底中形成掺杂区的步骤。在半导体衬底上形成衬垫氧化物层。在衬垫氧化物层上形成掩模层。掩模层，衬垫氧化物层和半导体衬底被图案化以在其中形成沟槽。间隙填充材料被再填充到沟槽中并在半导体衬底上。间隙填充材料的一部分被去除到掩模层的上表面。下一步是去除掩模层。沿着衬底的表面形成第一导电层，然后去除第一导电层的一部分以暴露间隙填充材料的上表面。在第一导电层上形成多晶硅间介质层，在多晶硅间介质层上形成第二导电层。

66. 发明授权

US06589840B2 Nonvolatile memory device with reduced floating gate and increased coupling ratio and manufacturing method thereof 有权
标题翻译：具有减小的浮动栅极和增加耦合比的非易失性存储器件及其制造方法
公开(公告)号：US06589840B2
公开(公告)日：2003-07-08
申请号：US09891408
申请日：2001-06-27
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324 , Y10S257/90
摘要： A nonvolatile memory device with a reduced size floating gate and an increased coupling ratio is disclosed. The nonvolatile memory device includes two isolation structures protruding above a semiconductor substrate. Two dielectric spacers are disposed on a pair of opposing sidewalls of the two isolation structures. The two dielectric spacers are spaced from one another at a distance that defines a gate width which is beyond lithography limit. A tunnel dielectric and a floating gate are provided on substrate and confined between the two dielectric spacers. The floating gate has a smaller bottom surface area relative to its top surface area and has a surface substantially coplanar with a surface of the isolation structures. On the coplanar surface, an inter-gate dielectric and a control gate are provided. Optionally, a lightly doped region is provided beside the floating gate 118 and within the substrate. A manufacturing method for forming such memory device is also disclosed.
摘要翻译：公开了一种具有减小尺寸的浮动栅极和增加的耦合比的非易失性存储器件。非易失性存储器件包括在半导体衬底上突出的两个隔离结构。两个电介质间隔物设置在两个隔离结构的一对相对的侧壁上。两个电介质间隔物以限定超出光刻极限的栅极宽度的距离彼此间隔开。隧道电介质和浮栅设置在衬底上并被限制在两个电介质间隔物之间。浮动栅极相对于其顶表面区域具有较小的底表面积，并且具有与隔离结构的表面基本上共面的表面。在共面上设置栅极间电介质和控制栅极。可选地，在浮置栅极118旁边和衬底内设置轻掺杂区域。还公开了一种用于形成这种存储器件的制造方法。

67. 发明授权

US06537880B1 Method of fabricating a high density NAND stacked gate flash memory device having narrow pitch isolation and large capacitance between control and floating gates 有权
标题翻译：制造具有窄间隔隔离度的高密度NAND堆叠栅极闪存器件和控制和浮置栅极之间的大电容的方法
公开(公告)号：US06537880B1
公开(公告)日：2003-03-25
申请号：US09950609
申请日：2001-09-13
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L21336
CPC分类号： H01L29/66825 , H01L21/28273 , H01L21/32139 , H01L29/42324
摘要： A process for fabricating a flash memory cell with increased floating gate to control gate overlap, has been developed. The process features forming the active device region of the flash memory cell in a narrow space of a semiconductor substrate, located between STI regions. The increased overlap is achieved via formation of a floating gate structure comprised with vertical conductive spacers, extending upwards from the periphery of an underlying floating gate base structure. Novel process sequences are used to simultaneously form the vertical conductive spacers and the floating gate base structure.
摘要翻译：已经开发了用于制造具有增加的浮动栅极以控制栅极重叠的闪存单元的工艺。该工艺特征在于在位于STI区域之间的半导体衬底的狭窄空间中形成闪存单元的有源器件区域。增加的重叠通过形成由垂直导电间隔件构成的浮动栅极结构来实现，该浮动栅极结构从下面的浮动栅极基极结构的外围向上延伸。新的工艺顺序用于同时形成垂直导电间隔物和浮动栅极基底结构。

68. 发明授权

US06495420B2 Method of making a single transistor non-volatile memory device 有权
标题翻译：制造单晶体管非易失性存储器件的方法
公开(公告)号：US06495420B2
公开(公告)日：2002-12-17
申请号：US09782238
申请日：2001-02-12
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L21336
CPC分类号： H01L29/42324 , H01L21/28273
摘要： The present invention includes forming a first oxide layer as a sacrificial dielectric layer on a semiconductor substrate. A nitride layer is formed on the sacrificial dielectric layer. Then, the sacrificial dielectric layer and the nitride layer are patterned to form an opening. Next, a second oxide layer is formed on the nitride layer and along a surface of the opening. Side wall spacers are created by etching. Then, a gate dielectric layer is formed on the exposed semiconductor substrate. A first polysilicon layer is deposited on the nitride layer. Subsequently, the first polysilicon layer is polished by CMP, followed by removing the nitride layer, the spacers and the sacrificial dielectric layer. A tunneling dielectric layer and a control gate are respectively formed on a surface of the floating gate.
摘要翻译：本发明包括在半导体衬底上形成作为牺牲电介质层的第一氧化物层。在牺牲电介质层上形成氮化物层。然后，将牺牲介电层和氮化物层图案化以形成开口。接下来，在氮化物层上并且沿着开口的表面形成第二氧化物层。通过蚀刻产生侧壁间隔物。然后，在暴露的半导体衬底上形成栅介质层。第一多晶硅层沉积在氮化物层上。随后，通过CMP抛光第一多晶硅层，然后除去氮化物层，间隔物和牺牲介电层。隧道电介质层和控制栅分别形成在浮动栅极的表面上。

69. 发明授权

US06455428B1 Method of forming a metal silicide layer 有权
标题翻译：形成金属硅化物层的方法
公开(公告)号：US06455428B1
公开(公告)日：2002-09-24
申请号：US09696080
申请日：2000-10-26
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L21302
CPC分类号： H01L21/76802 , H01L21/31058 , H01L21/76814
摘要： A process for forming a metal silicide layer on the surface of a conductive region in a semiconductor substrate, located at the bottom of a contact hole formed in an insulator layer, has been developed. The process features the removal of a photoresist shape, used to define the contact hole, via removal procedures that avoid the formation of a substoichiometric, silicon oxide, native oxide layer, on the top surface of the conductive region. The removal of the contact hole defining photoresist shape is realized via a chemical mechanical polishing procedure, which results in no native oxide formation, or removal of the photoresist shape can be accomplished via a combination of chemical mechanical polishing and wet clean procedure, which will form a native oxide layer, however only comprised of easily removable stoichiometric silicon oxide. The inability to remove substoichiometric silicon oxide, formed from procedures such as plasma oxygen ashing, can deleteriously influence the formation of metal silicide layers on the surface of a conductive region.
摘要翻译：已经开发了在位于形成在绝缘体层中的接触孔的底部的半导体衬底的导电区域的表面上形成金属硅化物层的工艺。该方法的特征在于通过去除程序去除用于限定接触孔的光致抗蚀剂形状，该方法避免了在导电区域的顶表面上形成亚化学计量的氧化硅自然氧化物层。通过化学机械抛光程序实现了形成光刻胶形状的接触孔的去除，这导致没有自然氧化物形成，或者可以通过化学机械抛光和湿清洁程序的组合来实现光致抗蚀剂形状的去除，这将形成天然氧化物层，然而仅由易于除去的化学计量的氧化硅组成。不能除去由诸如等离子体氧灰化的过程形成的亚化学计量氧化硅可有害地影响导电区域表面上的金属硅化物层的形成。

70. 发明授权

US06395603B1 Method of forming a tunnel oxide layer of a non-volatile memory cell 有权
标题翻译：形成非易失性存储单元的隧道氧化物层的方法
公开(公告)号：US06395603B1
公开(公告)日：2002-05-28
申请号：US09745334
申请日：2000-12-20
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L213105
CPC分类号： H01L21/32135 , H01L21/28273 , H01L21/32105 , H01L21/32137 , Y10S438/964
摘要： A method of forming a tunnel oxide layer of a non-volatile memory cell is disclosed. First, a first dielectric layer and a second dielectric layer are formed on a semiconductor substrate. After patterning the second dielectric layer to form an opening, the semiconductor substrate is oxidized to form a non-tunnel oxide within the opening. After removing the second dielectric layer, source/drain regions are formed by performing an ion implantation process and an annealing process. After removing the first dielectric layer, an HSG layer with a plurality of HSG grains are formed on the source/drain regions. After that, the HSG layer is partially etched by HF vapor to enlarge a spacing between the HSG grains. Finally, the HSG layer is oxidized to form the tunnel oxide layer.
摘要翻译：公开了一种形成非易失性存储单元的隧道氧化物层的方法。首先，在半导体衬底上形成第一电介质层和第二电介质层。在图案化第二电介质层以形成开口之后，半导体衬底被氧化以在开口内形成非隧道氧化物。在去除第二电介质层之后，通过进行离子注入工艺和退火工艺形成源极/漏极区域。在去除第一电介质层之后，在源/漏区上形成具有多个HSG晶粒的HSG层。之后，HSG层被HF蒸汽部分蚀刻，以扩大HSG晶粒之间的间距。最后，HSG层被氧化形成隧道氧化层。

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