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61. 发明授权

US5514613A Parallel manufacturing of semiconductor devices and the resulting structure 失效
标题翻译：并联制造半导体器件及其结构
公开(公告)号：US5514613A
公开(公告)日：1996-05-07
申请号：US189024
申请日：1994-01-27
申请人： Joseph F. Santadrea , Ji-Min Lee , Chuen-Der Lien , Alan H. Huggins
发明人： Joseph F. Santadrea , Ji-Min Lee , Chuen-Der Lien , Alan H. Huggins
IPC分类号： H01L21/66 , H01L21/68 , H01L21/768
CPC分类号： H01L21/6835 , H01L22/20 , H01L2221/68359 , H01L2221/68363 , H01L2924/014 , H01L2924/10253 , H01L2924/19041 , H01L2924/30105
摘要： In accordance with this invention, integrated circuits are manufactured using parallel processing to manufacture separately selected parts of finished integrated circuits. Upon completion of the parts, the parts are joined together to form the completed integrated circuit. For example, a semiconductor wafer containing active and passive semiconductor regions is fabricated through the first layer of insulation and first conductive contacts. Separately, an interconnect structure is fabricated on a separate fabrication line to include all the layers of interconnects required to form a completed integrated circuit when joined to the wafer. The interconnect structure is joined to the wafer to form the complete integrated device. The interconnect structure can be fabricated to exclude from the integrated circuit those portions of the wafer which have been determined by test to be defective.
摘要翻译：根据本发明，使用并行处理制造集成电路，以制造成品集成电路的分开选择的部分。零件完成后，零件连接在一起形成完整的集成电路。例如，通过第一绝缘层和第一导电触点制造包含有源和无源半导体区域的半导体晶片。另外，在单独的制造线上制造互连结构，以包括当连接到晶片时形成完整的集成电路所需的所有互连层。互连结构连接到晶片以形成完整的集成器件。可以制造互连结构以从集成电路排除已经通过测试确定为缺陷的晶片的那些部分。

62. 发明授权

US5471094A Self-aligned via structure 失效
标题翻译：自对准通孔结构
公开(公告)号：US5471094A
公开(公告)日：1995-11-28
申请号：US201437
申请日：1994-02-24
申请人： Chuen-Der Lien
发明人： Chuen-Der Lien
IPC分类号： H01L23/522 , H01L27/11 , H01L23/48 , H01L23/52 , H01L29/76
CPC分类号： H01L27/1112 , H01L23/5226 , H01L27/11 , H01L2924/0002 , Y10S257/903
摘要： A self-aligned via between interconnect layers in an integrated circuit allows a less precise masking alignment to be used to fabricate an integrated circuit with increased packing density and improved yield. In one embodiment, self-aligned vias are used to connect first and second interconnect layers in an SRAM memory cell.
摘要翻译：集成电路中的互连层之间的自对准通孔允许使用较不精确的掩模对准来制造具有增加的封装密度和提高的产量的集成电路。在一个实施例中，自对准通孔用于连接SRAM存储单元中的第一和第二互连层。

63. 发明授权

US5182475A ECL to CMOS voltage translator with bipolar transistor 失效
标题翻译： ECL至CMOS电压转换器，带双极晶体管
公开(公告)号：US5182475A
公开(公告)日：1993-01-26
申请号：US762960
申请日：1991-09-20
申请人： Chuen-Der Lien
发明人： Chuen-Der Lien
IPC分类号： H03K19/017 , H03K19/0175
CPC分类号： H03K19/017518 , H03K19/01721
摘要： An improved circuit for translating ECL level voltages to CMOS level voltages. The circuit of the invention has a voltage gain stage with a bipolar transistor connected to a PMOS transistor, and a resistive loading stage including NMOS transistors. The bipolar transistor functions to increase the speed of the circuit (particularly at high temperatures) by increasing the driving capability of the voltage gain stage. The speed of the circuit will degrade very little at high temperature and high output load conditions, because the current driving capability of the bipolar transistor employed has low sensitivity to output loading and temperature.
摘要翻译：用于将ECL电平电压转换为CMOS电平电压的改进电路。本发明的电路具有连接到PMOS晶体管的双极晶体管和包括NMOS晶体管的电阻加载级的电压增益级。双极晶体管的作用是通过增加电压增益级的驱动能力来提高电路的速度（特别是在高温下）。由于采用的双极晶体管的电流驱动能力对输出负载和温度的敏感性低，所以在高温和高输出负载条件下，电路的速度将会很低。

64. 发明授权

US08028211B1 Look-ahead built-in self tests with temperature elevation of functional elements 有权
标题翻译：先进的内置自检与功能元素的温度升高
公开(公告)号：US08028211B1
公开(公告)日：2011-09-27
申请号：US12268854
申请日：2008-11-11
申请人： Michael Miller , Chuen-Der Lien
发明人： Michael Miller , Chuen-Der Lien
IPC分类号： G01R31/3187 , G01R31/40
CPC分类号： G01R31/3016 , G01R31/318519
摘要： A method and apparatus are disclosed for predicting the failure of a functional element of an integrated circuit during operation. The method includes determining whether the functional element of the integrated circuit device is in an idle cycle, elevating the temperature of the functional element above a normal operating temperature, performing a stress test of the functional element while the functional element is in the idle cycle, and indicating that the functional element, if it fails the stress test, is a potential future failing element. The stress test can include simultaneously providing a margining test voltage and a stress clock signal to the functional element while the temperature is elevated or at a normal operating temperature. The stress test is performed in the background, during continuous operation of the integrated circuit device, such that normal operation of the integrated circuit device is not interrupted. Thereby, the method and apparatus of the present invention allows for failure prediction in a device before it happens, allowing for planned outages or workarounds and avoiding system downtime for unplanned repairs.
摘要翻译：公开了一种用于在操作期间预测集成电路的功能元件的故障的方法和装置。该方法包括：确定集成电路器件的功能元件是否处于空闲周期，将功能元件的温度升高到正常工作温度以上，在功能元件处于空闲周期期间执行功能元件的压力测试，并指出功能元件（如果压力测试失败）是潜在的未来故障元素。应力测试可以包括在温度升高或在正常工作温度下同时向功能元件提供裕度测试电压和应力时钟信号。在集成电路装置的连续运行期间，在背景中执行应力测试，使得集成电路装置的正常操作不被中断。因此，本发明的方法和装置允许在装置发生之前对装置进行故障预测，从而允许计划中断或解决方案，并避免计划外维修的系统停机时间。

65. 发明授权

US07859876B1 Method and apparatus for CAM with reduced cross-coupling interference 有权
标题翻译：具有降低的交叉耦合干扰的CAM的方法和装置
公开(公告)号：US07859876B1
公开(公告)日：2010-12-28
申请号：US11765326
申请日：2007-06-19
申请人： Chuen-Der Lien , Chau-Chin Wu
发明人： Chuen-Der Lien , Chau-Chin Wu
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G11C7/02
摘要： A method and apparatus for a CAM with reduced cross-coupling interference have been disclosed.
摘要翻译：已经公开了一种具有减小的交叉耦合干扰的CAM的方法和装置。

66. 再颁专利

USRE41351E1 CAM arrays having CAM cells therein with match line and low match line connections and methods of operating same 失效
标题翻译： CAM阵列，其中具有匹配线和低匹配线路连接的CAM单元及其操作方法
公开(公告)号：USRE41351E1
公开(公告)日：2010-05-25
申请号：US10106420
申请日：2002-03-26
申请人： Chuen-Der Lien , Chau-Chin Wu
发明人： Chuen-Der Lien , Chau-Chin Wu
IPC分类号： G11C15/00
CPC分类号： G11C15/046 , G11C15/04 , G11C15/043
摘要： A CAM array including volatile or non-volatile ternary CAM cells that discharge their associated match line through a special discharge line (e.g., a low match line), instead of through the bit line, is disclosed. Each ternary CAM cell includes a pair of storage elements that are used to store a data bit value, a comparison element that is used to compare the stored value with an applied data value, and a discharge element that is coupled between the discharge line and the match line. During operation, when the applied data value matches the stored value, the discharge element de-couples the discharge line from the match line (i.e., a high voltage on the match line remains high). Conversely, when the applied data value does not match the stored value, the discharge elements couple the discharge line to the match line, thereby discharging the match line to the discharge line. By discharging the match line to the discharge line instead of the bit lines of the CAM array, the size of the CAM array is not limited by the length bit lines. Because the voltage on the match line is sensed to determine the match/no-match condition of a CAM cell, the match line does not need to be completely discharged.
摘要翻译：公开了一种包括挥发性或非挥发性三元CAM单元的CAM阵列，其通过特殊的放电线（例如，低匹配线）而不是通过位线而排出其相关匹配线。每个三元CAM单元包括用于存储数据位值的一对存储元件，用于将存储的值与应用的数据值进行比较的比较元件，以及耦合在放电线和匹配线。在操作期间，当所应用的数据值与存储的值匹配时，放电元件将放电线与匹配线解耦（即，匹配线上的高电压保持为高）。相反，当所施加的数据值与存储值不匹配时，放电元件将放电线耦合到匹配线，从而将匹配线放电到放电线。通过将匹配线排放到放电线而不是CAM阵列的位线，CAM阵列的大小不受长度位线的限制。由于感测匹配线上的电压以确定CAM单元的匹配/不匹配条件，所以匹配线不需要被完全放电。

67. 发明授权

US07706113B1 Electrical overstress (EOS) and electrostatic discharge (ESD) protection circuit and method of use 有权
标题翻译：电气应力（EOS）和静电放电（ESD）保护电路及其使用方法
公开(公告)号：US07706113B1
公开(公告)日：2010-04-27
申请号：US11668360
申请日：2007-01-29
申请人： Chuen-Der Lien , Ta-Ke Tien
发明人： Chuen-Der Lien , Ta-Ke Tien
IPC分类号： H02H9/00 , H02H3/22
CPC分类号： H01L27/0285
摘要： A system and method are provided for electrostatic discharge (ESD) protection circuit having overshoot and undershoot voltage protection during a power supply ramp-up of the circuit. In a specific embodiment, the ESD protection circuit of the present invention includes an ESD discharge circuit coupled between a power supply node and a ground supply node, a trigger circuit coupled to the ESD discharge circuit, the trigger circuit to turn the ESD discharge circuit on in the presence of a voltage spike during the power supply ramp-up and to turn the ESD discharge circuit off in the absence of a voltage spike during the power supply ramp-up, and a delay circuit coupled between the discharge circuit and the trigger circuit, the delay circuit to slow down the turn-off of the discharge circuit to prevent an overshoot or undershoot voltage condition during the power supply ramp-up of the circuit.
摘要翻译：提供一种用于在电路的电源斜升期间具有过冲和下冲电压保护的静电放电（ESD）保护电路的系统和方法。在具体实施例中，本发明的ESD保护电路包括耦合在电源节点和接地电源节点之间的ESD放电电路，耦合到ESD放电电路的触发电路，触发电路以使ESD放电电路转向在电源斜坡上升期间存在电压尖峰，并且在电源上升期间没有电压尖峰时将ESD放电电路断开，以及耦合在放电电路和触发电路之间的延迟电路延迟电路，以减缓放电电路的关断，以防止在电路的电源上升期间的过冲或下冲电压状况。

68. 发明授权

US07443747B2 Memory array bit line coupling capacitor cancellation 有权
标题翻译：存储阵列位线耦合电容器取消
公开(公告)号：US07443747B2
公开(公告)日：2008-10-28
申请号：US10997708
申请日：2004-11-23
申请人： Chuen-Der Lien , Tzong-Kwang Henry Yeh
发明人： Chuen-Der Lien , Tzong-Kwang Henry Yeh
IPC分类号： G11C7/00
CPC分类号： G11C8/16 , G11C5/063 , G11C7/02 , G11C7/12 , G11C11/419
摘要： Capacitive coupling correction circuits are coupled between adjacent parallel dynamic (pre-charged) or static conductors. The capacitive coupling correction circuits effectively isolate a low voltage applied to a first conductor from a high pre-charged voltage stored on an adjacent second conductor (or vice versa). The adjacent parallel conductors can be bit lines of a memory cell. Each capacitive coupling correction circuit can include an inverter having an input terminal coupled to the first conductor, and an output terminal coupled to a first plate of a capacitor. A second plate of the capacitor is coupled to the second conductor. The capacitance of the capacitor is selected to be identical to a parasitic capacitance between the first and second conductors. As a result, there is a zero net voltage effect between the first and second conductors. The capacitive coupling correction circuits may be distributed along the length of the first and second conductors.
摘要翻译：电容耦合校正电路耦合在相邻的并联动态（预充电）或静态导体之间。电容耦合校正电路有效地将施加到第一导体的低电压与存储在相邻的第二导体上的高预充电电压隔离（反之亦然）。相邻的平行导体可以是存储单元的位线。每个电容耦合校正电路可以包括具有耦合到第一导体的输入端的反相器和耦合到电容器的第一板的输出端。电容器的第二板耦合到第二导体。电容器的电容被选择为与第一和第二导体之间的寄生电容相同。结果，在第一和第二导体之间存在零净电压效应。电容耦合校正电路可以沿着第一和第二导体的长度分布。

69. 发明授权

US07102862B1 Electrostatic discharge protection circuit 有权
标题翻译：静电放电保护电路
公开(公告)号：US07102862B1
公开(公告)日：2006-09-05
申请号：US10283532
申请日：2002-10-29
申请人： Chuen-Der Lien , Ta-Ke Tien
发明人： Chuen-Der Lien , Ta-Ke Tien
IPC分类号： H02H9/00
CPC分类号： H01L27/0285
摘要： Circuits are disclosed for protecting internal circuitry of a semiconductor chip from increased power supply voltages due to electrostatic discharge (EDS). One example circuit includes a trigger circuit including a transistor and a capacitor arranged in series between DC pads. The trigger circuit generates a trigger signal to a discharge circuit connected between the DC pads to shunt charge from one of the DC pads to the other. The RC delay associated with the transistor and capacitor of the trigger circuit may be designed such that the trigger circuit generates the trigger signal in response to an ESD event, but not in response to high positive spikes on one of the DC pads during normal operation.
摘要翻译：公开了用于保护半导体芯片的内部电路免受由静电放电（EDS）引起的电源电压的电路。一个示例电路包括触发电路，其包括串联布置在DC焊盘之间的晶体管和电容器。触发电路产生触发信号到连接在DC焊盘之间的放电电路，以将电荷从DC焊盘之一分流到另一个。可以设计与触发电路的晶体管和电容器相关联的RC延迟，使得触发电路响应于ESD事件而产生触发信号，但不响应于在正常操作期间的一个DC焊盘上的高正尖峰。

70. 发明授权

US06924995B2 CAM circuit with radiation resistance 失效
标题翻译：具有辐射电阻的CAM电路
公开(公告)号：US06924995B2
公开(公告)日：2005-08-02
申请号：US10845654
申请日：2004-05-13
申请人： Chuen-Der Lien
发明人： Chuen-Der Lien
IPC分类号： G11C5/00 , G11C15/04 , G11C15/00
CPC分类号： G11C5/005 , G11C15/04 , G11C15/043
摘要： A CMOS CAM circuit an array of CAMs formed on a p-type substrate. Each CAM cell includes a logic portion and an SRAM cell, both having at least one n-channel transistor formed in a p-type well on the p-type substrate. An n-type doped layer is formed between the p-type well region and the p-substrate. The doped layer and well region are maintained at a voltage potential that is between a threshold voltage and a breakdown voltage defined the PN junction formed at their interface. The resulting structure attracts electron-hole pairs formed by alpha particles, thereby preventing soft errors. Alternatively, the logic portions and SRAM cells have p-channel transistors formed in n-type wells on an n-type substrate, and a p-type doped layer is formed between the n-type well region and the n-substrate.
摘要翻译： CMOS CAM电路形成在p型衬底上的CAM阵列。每个CAM单元包括逻辑部分和SRAM单元，它们都具有形成在p型衬底上的p型阱中的至少一个n沟道晶体管。在p型阱区和p型衬底之间形成n型掺杂层。掺杂层和阱区保持在阈值电压和击穿电压之间的电压电位，限定了在其界面处形成的PN结。所得结构吸引由α粒子形成的电子 - 空穴对，从而防止软错误。或者，逻辑部分和SRAM单元具有形成在n型衬底上的n型阱中的p沟道晶体管，并且在n型阱区和n衬底之间形成p型掺杂层。

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