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61. 发明授权

US5066995A Double level conductor structure 失效
标题翻译：双层导体结构
公开(公告)号：US5066995A
公开(公告)日：1991-11-19
申请号：US25435
申请日：1987-03-13
申请人： William R. Young , Anthony L. Rivoli
发明人： William R. Young , Anthony L. Rivoli
IPC分类号： H01L27/092
CPC分类号： H01L27/0928
摘要： A double level conductive structure is provided wherein one conductor layer permits impurities to pass therethrough in a given impurity introduction steph while double conductor level portion substantially prevents such impurities from passing therethrough due to a greater combined resistance to impurity penetration.
摘要翻译：提供了一种双层导电结构，其中一个导体层允许杂质在给定的杂质导入步骤中通过其中，而双导体水平部分由于更大的杂质渗透阻力而基本上防止这种杂质通过。

62. 发明授权

US5051949A Content addressable memory device 失效
标题翻译：内容可寻址存储设备
公开(公告)号：US5051949A
公开(公告)日：1991-09-24
申请号：US437472
申请日：1989-11-15
申请人： William R. Young
发明人： William R. Young
IPC分类号： G11C15/04
CPC分类号： G11C15/04
摘要： A memory device for a content addressable memory is configured of a pair of multibit memory cells which permits the memory to be programmably readable on an individual bit basis, whereby the memory may be selectively programmed to be fully content addressable, partially content addressable, or non-content addressable. The memory device is coupled to a complementary bit line pair and has a pair of word enable lines coupled to address lines and a respective row output line, the state of which is monitored during an associative read operation. Data is stored in a respective memory device in the form of complementary bit codes, individual components of which are written into the memory cells. The participation of each memory device during an associative read operation is controlled by means of a set of switching circuits that are coupled to each memory cell, the bit lines and the output line. Depending upon the multibit codes that have been stored in the memory cells and the contents of the bit lines, these controlled switching circuits controllably cause a prescribed logic potential to be applied by the memory device to the output line and thereby indicate the occurrence of a match.
摘要翻译：用于内容可寻址存储器的存储器设备由一对多位存储器单元构成，其允许存储器在单独的位基础上被可编程地读取，由此存储器可以被选择性地编程为完全内容可寻址，部分内容可寻址或非内容可寻址。存储器件耦合到互补位线对，并且具有耦合到地址线和相应行输出线的一对字使能线，其状态在关联读操作期间被监视。数据以互补位代码的形式存储在各自的存储器件中，其各个部件被写入存储器单元。在关联读取操作期间每个存储器件的参与通过耦合到每个存储器单元，位线和输出线的一组开关电路来控制。根据已经存储在存储单元中的多位代码和位线的内容，这些受控切换电路可控制地使规定的逻辑电位由存储器件施加到输出线，从而指示匹配的发生。

63. 发明授权

US5047974A Cell based adder with tree structured carry, inverting logic and balanced loading 失效
标题翻译：基于单元的加法器，具有树结构进位，反相逻辑和平衡负载
公开(公告)号：US5047974A
公开(公告)日：1991-09-10
申请号：US124807
申请日：1987-11-24
申请人： William R. Young
发明人： William R. Young
IPC分类号： G06F7/50 , G06F7/508 , H03K19/21
CPC分类号： G06F7/508 , H03K19/215 , G06F2207/5063
摘要： An adder comprising a tree-based carry structure, wherein the maximum fanout from any gate in the carry structure is three. When calculating optimized fanout, it is necessary to consider input capacitance to the following stage. In minimizing propagation delay, it is necessary to consider loading and the number of stages. It has been recognized that optimum fanout of e results in optimized propagation through the adder, thus fanout of three is the closest whole number. A cell has been designed which includes the necessary and sufficient circuitry for building multicell adders in a highly optimized structure. The cell provides individually accessible components and dedicated components for optimum layout in the end product.
摘要翻译：一种包括基于树的进位结构的加法器，其中来自进位结构中的任何门的最大扇出为三。在计算优化扇出时，需要考虑以下阶段的输入电容。在最小化传播延迟时，有必要考虑加载和级数。已经认识到，e的最佳扇出导致通过加法器的优化传播，因此三的扇出是最接近的整数。已经设计了一个电池，其中包括用于以高度优化的结构构建多单元加法器的必要和充分的电路。该电池提供可单独访问的组件和专用组件，以在最终产品中实现最佳布局。

64. 发明授权

US5021359A Radiation hardened complementary transistor integrated circuits 失效
标题翻译：辐射硬化互补晶体管集成电路
公开(公告)号：US5021359A
公开(公告)日：1991-06-04
申请号：US416419
申请日：1989-10-03
申请人： William R. Young , Anthony L. Rivoli , William W. Wiles, Jr.
发明人： William R. Young , Anthony L. Rivoli , William W. Wiles, Jr.
IPC分类号： H01L21/765 , H01L27/092 , H01L27/12
CPC分类号： H01L27/092 , H01L21/765 , H01L27/1203 , Y10S438/953
摘要： Integrated circuits with vertical isolated trenches are radiation hardened by providing vertical gate segments, preferably, of doped polycrystalline silicon, in the trenches and connected at the bottom of the trenches to a region of the same conductivity type. The surface devices may be complementary and the vertical gates may also be complementarily doped. A method of fabrication is described for a single crystal wafer, as well as SOI.
摘要翻译：具有垂直隔离沟槽的集成电路通过在沟槽中提供垂直栅极段（优选为掺杂多晶硅）而被辐射硬化，并且在沟槽的底部连接到相同导电类型的区域。表面器件可以是互补的，并且垂直栅极也可以是互补掺杂的。对于单晶晶片以及SOI，描述了制造方法。

65. 发明授权

US4914501A Vertical contact structure 失效
标题翻译：垂直接触结构
公开(公告)号：US4914501A
公开(公告)日：1990-04-03
申请号：US334148
申请日：1989-04-06
申请人： Anthony L. Rivoli , William R. Young
发明人： Anthony L. Rivoli , William R. Young
IPC分类号： H01L23/485 , H01L29/41
CPC分类号： H01L23/485 , H01L29/41 , H01L2924/0002 , Y10S257/90 , Y10S257/903
摘要： A compact vertical contact has lateral space requirements in the fabrication of semiconductor devices and is compatible with highly planarized processes. The contact is made from a foundation region having a top surface to an overlying layer separated from the foundation region by a dielectric. The overlying layer may be contacted at an edge rather than on its top surface in order to reduce the lateral expanse of the contact.
摘要翻译：紧凑的垂直接触在半导体器件的制造中具有横向空间要求，并且与高度平坦化的工艺兼容。接触由具有顶表面的基础区域到通过电介质与基础区域分离的上覆层制成。覆盖层可以在边缘而不是在其顶表面上接触，以便减少接触的横向膨胀。

66. 发明授权

US4882698A Cell based ALU with tree structured carry, inverting logic and balanced loading 失效
标题翻译：基于单元的ALU具有树结构进位，反相逻辑和平衡负载
公开(公告)号：US4882698A
公开(公告)日：1989-11-21
申请号：US106071
申请日：1987-10-07
申请人： William R. Young
发明人： William R. Young
IPC分类号： G06F7/50 , G06F7/508
CPC分类号： G06F7/508 , G06F2207/5063
摘要： An ALU comprising a tree-based carry structure, wherein the maximum fanout from any gate in the carry structure is three. When calculating optimized fanout, it is necessary to consider input capacitance to the following stage. In minimizing propagation delay, it is necessary to consider loading and the number of stages. It has been recognized that optimum fanout of results in optimized propagation through the ALU, thus fanout of three is the closest whole number. A cell has been designed which includes the necessary and sufficient circuitry for building multicell ALU's in a highly optimized structure. The cell provides individually accessible components and dedicated components for optimum layout in the end product.
摘要翻译：包括基于树的进位结构的ALU，其中来自进位结构中的任何门的最大扇出为三。在计算优化扇出时，需要考虑以下阶段的输入电容。在最小化传播延迟时，有必要考虑加载和级数。已经认识到，通过ALU优化传播的最佳扇出是最接近的整数。已经设计了一个单元，其中包括用于以高度优化的结构构建多单元ALU的必要和足够的电路。该电池提供可单独访问的组件和专用组件，以在最终产品中实现最佳布局。

67. 发明授权

US4830934A Alloy powder mixture for treating alloys 失效
标题翻译：用于处理合金的合金粉末混合物
公开(公告)号：US4830934A
公开(公告)日：1989-05-16
申请号：US56175
申请日：1987-06-01
申请人： Stephen J. Ferrigno , Mark Somerville , William R. Young
发明人： Stephen J. Ferrigno , Mark Somerville , William R. Young
IPC分类号： B23K1/00 , B22F1/00 , B22F7/08 , B23K35/30 , C22C19/05
CPC分类号： B23K35/304 , B23K35/30 , Y10T29/49746 , Y10T428/12861 , Y10T428/12931 , Y10T428/12944
摘要： An improved mixture of alloy powders is provied for use in treating a preselected article alloy, for example, to repair or join multiple components of the article. The mixture has at least three distinct groups of alloy powders which together define a mixture composition range, with each alloy powder of the groups characterized by a composition and melting range different from the others and from the article alloy. In a preferred form, the mixture composition range comprises, by weight, 15-30% Cr, 1.5-6% W, 0.4-4% Al, 1-11% Ti, 1-6% Ta, up to 1.5% B, up to 0.5% Si, up to 0.2% Zr, up to 3% Mo, up to 0.3% Hf, up to 6% Cb, up to 2% Re, with the balance selected from Co and Ni along with incidental impurities.

68. 发明授权

US4514802A Integrated program counter memory management register and incrementer 失效
标题翻译：集成程序计数器存储器管理寄存器和增量器
公开(公告)号：US4514802A
公开(公告)日：1985-04-30
申请号：US363815
申请日：1982-03-31
申请人： Paul Cohen , William R. Young
发明人： Paul Cohen , William R. Young
IPC分类号： G06F9/32
CPC分类号： G06F9/321
摘要： An integrated structure including a program counter, a memory management structure and an incrementer interconnected by an internal bus such that the logic value of the program counter may be read into the memory management register and the program counter can be incremented depending upon the value of the pre-incremented program counter logic level and an increment signal from the previous stage. External access to the program counter and the memory management register are provided by external buses. A sense amplifier is also provided so as to maintain the value of the pre-incremented program counter on the internal rail allowing the memory management register to be disconnected therefrom during the increment cycle.
摘要翻译：一种包括程序计数器，存储器管理结构和通过内部总线互连的增量器的集成结构，使得可以将程序计数器的逻辑值读入存储器管理寄存器，并且程序计数器可以根据预先递增的程序计数器逻辑电平和来自前一级的增量信号。程序计数器和存储器管理寄存器的外部访问由外部总线提供。还提供读出放大器，以便在内部轨道上保持预增量程序计数器的值，从而允许存储器管理寄存器在增量循环期间与其断开连接。

69. 发明授权

US4389721A Time-division multiplex serial loop 失效
标题翻译：时分复用串行回路
公开(公告)号：US4389721A
公开(公告)日：1983-06-21
申请号：US278990
申请日：1981-06-30
申请人： William R. Young , Stanley R. Zepp
发明人： William R. Young , Stanley R. Zepp
IPC分类号： H04L12/423 , H04J6/02 , G08B5/00
CPC分类号： H04L12/423
摘要： A loop controller transmits data to and receives data from a plurality of I/O ports on a TDM serial loop by generating a plurality of frames which include a frame control field followed by a plurality of dedicated time slot fields. Each time slot field includes an inbound data control bit or bits followed by a data field followed by an outbound data control bit or bits. The I/O port inputs and outputs data in its dedicated data field as dictated by the respective data control bit. The loop controller and I/O ports monitor the data control bit to request data, indicate insertion of data, indicate receipt of the data and acknowledge the receipt indication to achieve a complete handshake. During an initialization frame, the I/O ports set themselves into primary and secondary data modes based on sensing a prior I/O port with the same dedicated time slot. Separate primary, secondary, inbound and outbound data control bits permit interleaved communication by the loop controller to and from plural ports with the same dedicated time slot.
摘要翻译：环路控制器通过产生包括后面跟着多个专用时隙字段的帧控制字段的多个帧来向TDM串行环路上的多个I / O端口发送数据并从其接收数据。每个时隙字段包括一个入站数据控制位或位，后跟一个数据字段，后跟一个出站数据控制位或位。 I / O端口根据相应的数据控制位来指定其专用数据字段中的数据。环路控制器和I / O端口监视数据控制位以请求数据，指示数据插入，指示接收数据并确认收据指示以实现完全握手。在初始化帧期间，I / O端口基于感测具有相同专用时隙的先前I / O端口将其自身设置为主数据模式和辅助数据模式。独立的主，辅助，入站和出站数据控制位允许环路控制器与具有相同专用时隙的多个端口进行交织通信。

70. 发明授权

US4380710A TTL to CMOS Interface circuit 失效
标题翻译： TTL到CMOS接口电路
公开(公告)号：US4380710A
公开(公告)日：1983-04-19
申请号：US231671
申请日：1981-02-05
申请人： Paul B. Cohen , William R. Young , W. Dale Edwards
发明人： Paul B. Cohen , William R. Young , W. Dale Edwards
IPC分类号： H03K19/0185 , H03K19/092 , H03K17/04 , H03K19/094 , H03K19/20
CPC分类号： H03K19/018521
摘要： An interface circuit including a FET inverter with its N channel device being part of the controlled leg of a first current mirror and its P channel device being part of the controlled leg of a second current mirror. The operating point of the inverter is the reference signal applied on the input to the current mirrors. The controlled leg of the first current mirror includes a variable current source responsive to the input signal and the controlled leg of the second current mirror includes a variable current sink for improving the response time of the inverter and compensates the inverter for manufacturing tolerances.
摘要翻译：一种接口电路，其包括FET反相器，其N沟道器件是第一电流镜的受控支路的一部分，并且其P沟道器件是第二电流镜的受控支路的一部分。逆变器的工作点是施加在电流镜的输入端上的参考信号。第一电流镜的受控支路包括响应于输入信号的可变电流源，并且第二电流镜的受控支路包括可变电流吸收器，用于改善逆变器的响应时间并补偿逆变器的制造公差。

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