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61. 发明申请

US20060001109A1 High mobility tri-gate devices and methods of fabrication 失效
公开(公告)号：US20060001109A1
公开(公告)日：2006-01-05
申请号：US10883183
申请日：2004-06-30
申请人： Mohamad Shaheen , Brian Doyle , Suman Datta , Robert Chau , Peter Tolchinksy
发明人： Mohamad Shaheen , Brian Doyle , Suman Datta , Robert Chau , Peter Tolchinksy
IPC分类号： H01L21/336 , H01L29/94
CPC分类号： H01L29/785 , H01L21/76243 , H01L21/76254 , H01L21/76256 , H01L29/045 , H01L29/66772
摘要： A high mobility semiconductor assembly. In one exemplary aspect, the high mobility semiconductor assembly includes a first substrate having a first reference orientation located at a crystal plane location on the first substrate and a second substrate formed on top of the first substrate. The second substrate has a second reference orientation located at a crystal plane location on the second substrate, wherein the first reference orientation is aligned with the second reference orientation. In another exemplary aspect, the second substrate has a second reference orientation located at a crystal plane location on the second substrate, wherein the second substrate is formed over the first substrate with the second reference orientation being offset to the first reference orientation by about 45 degrees.

62. 发明申请

US20050272187A1 Process for ultra-thin body SOI devices that incorporate EPI silicon tips and article made thereby 有权
标题翻译：包含EPI硅尖端和由此制成的制品的超薄体SOI器件的工艺
公开(公告)号：US20050272187A1
公开(公告)日：2005-12-08
申请号：US11204418
申请日：2005-08-15
申请人： Anand Murthy , Brian Doyle , Jack Kavalieros , Robert Chau
发明人： Anand Murthy , Brian Doyle , Jack Kavalieros , Robert Chau
IPC分类号： H01L21/336 , H01L29/417 , H01L29/786
CPC分类号： H01L29/41733 , H01L29/665 , H01L29/6656 , H01L29/66636 , H01L29/66772 , H01L29/78618
摘要： The invention relates to a transistor that includes an ultra-thin body epitaxial layer that forms an embedded junction with a channel that has a length dictated by an undercut under the gate stack for the transistor. The invention also relates to a process of forming the transistor and to a system that incorporates the transistor.
摘要翻译：本发明涉及一种晶体管，其包括超薄体外延层，该超薄体外延层与具有由晶体管的栅极堆叠下方的底切指定的沟道的沟道形成嵌入的结。本发明还涉及一种形成晶体管的方法和涉及晶体管的系统。

63. 发明申请

US20050242406A1 Nonplanar device with stress incorporation layer and method of fabrication 有权
公开(公告)号：US20050242406A1
公开(公告)日：2005-11-03
申请号：US11173443
申请日：2005-06-30
申请人： Scott Hareland , Robert Chau , Brian Doyle , Suman Datta , Been-Yih Jin
发明人： Scott Hareland , Robert Chau , Brian Doyle , Suman Datta , Been-Yih Jin
IPC分类号： H01L21/336 , H01L29/10 , H01L29/423 , H01L29/76 , H01L29/786
CPC分类号： H01L29/785 , H01L29/1054 , H01L29/42384 , H01L29/66628 , H01L29/66795 , H01L29/7842 , H01L29/7843 , H01L29/7849
摘要： A semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls is formed on an insulating substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and is formed adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. A thin film is then formed adjacent to the semiconductor body wherein the thin film produces a stress in the semiconductor body.

64. 发明申请

US20050073060A1 Method and apparatus for improving stability of a 6T CMOS SRAM cell 有权
公开(公告)号：US20050073060A1
公开(公告)日：2005-04-07
申请号：US10679124
申请日：2003-10-02
申请人： Suman Datta , Brian Doyle , Robert Chau , Jack Kavalieros , Bo Zheng , Scott Hareland
发明人： Suman Datta , Brian Doyle , Robert Chau , Jack Kavalieros , Bo Zheng , Scott Hareland
IPC分类号： G11C11/412 , H01L21/336 , H01L21/8244 , H01L27/11 , H01L29/423 , H01L29/786
CPC分类号： G11C11/412 , H01L21/845 , H01L27/11 , H01L27/1104 , H01L27/1211 , H01L29/42384 , H01L29/66795 , H01L29/785 , H01L29/7854
摘要： The present invention is a CMOS SRAM cell comprising two access devices, each access device comprised of a tri-gate transistor having a single fin; two pull-up devices, each pull-up device comprised of a tri-gate transistor having a single fin; and two pull-down devices, each pull-down device comprised of a tri-gate transistor having multiple fins. A method for manufacturing the CMOS SRAM cell, including the dual fin tri-gate transistor is also provided.

65. 发明申请

US20050040469A1 Integrating N-type and P-type metal gate transistors 有权
标题翻译：集成N型和P型金属栅晶体管
公开(公告)号：US20050040469A1
公开(公告)日：2005-02-24
申请号：US10946502
申请日：2004-09-20
申请人： Mark Doczy , Justin Brask , Steven Keating , Chris Barns , Brian Doyle , Michael McSwiney , Jack Kavalieros , John Barnak
发明人： Mark Doczy , Justin Brask , Steven Keating , Chris Barns , Brian Doyle , Michael McSwiney , Jack Kavalieros , John Barnak
IPC分类号： H01L21/3213 , H01L21/336 , H01L21/8238 , H01L29/49 , H01L29/78
CPC分类号： H01L29/66545 , H01L21/32134 , H01L21/32137 , H01L21/823842 , H01L29/495 , H01L29/4966 , H01L29/7833 , Y10S438/926
摘要： At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.
摘要翻译：至少p型和n型半导体器件沉积在包含金属或金属合金栅极的半导体晶片上。更具体地，在具有n型和p型金属栅极的半导体晶片上形成互补金属氧化物半导体（CMOS）器件。

66. 发明授权

US06790731B2 Method for tuning a work function for MOSFET gate electrodes 有权
标题翻译：调整MOSFET栅电极功函数的方法
公开(公告)号：US06790731B2
公开(公告)日：2004-09-14
申请号：US10071144
申请日：2002-02-06
申请人： Jun-Fei Zheng , Brian Doyle , Gang Bai , Chunlin Liang
发明人： Jun-Fei Zheng , Brian Doyle , Gang Bai , Chunlin Liang
IPC分类号： H01L21336
CPC分类号： H01L21/82345 , H01L21/823425 , H01L27/088
摘要： A method for creating insulated gate field effect transistors having gate electrodes with at least two layers of materials to provide gate electrode work function values that are similar to those of doped polysilicon, to eliminate the poly depletion effect, and to substantially prevent impurity diffusion into the gate dielectric. Depositing bi-layer stacks of relatively thick Al and thin TiN for n-channel FETs and bi-layer stacks of relatively thick Pd and thin TiN, or relatively thick Pd and thin TaN for p-channel FETs is disclosed. Varying the thickness of the thin TiN or TaN layers between a first and second critical thickness may be used to modulate the work function of the gate electrode and thereby obtain the desired trade-off between channel doping and drive currents in FETs.
摘要翻译：一种用于制造具有至少两层材料的栅电极的绝缘栅场效应晶体管的方法，以提供类似于掺杂多晶硅的栅电极功函数值，以消除多余耗尽效应，并且基本上防止杂质扩散到栅电介质。公开了用于p沟道FET的n沟道FET和相对厚的Pd和薄TiN或相对厚的Pd和薄TaN的双层堆叠的相对厚的Al和薄TiN的双层堆叠。改变第一和第二临界厚度之间的薄TiN或TaN层的厚度可以用于调制栅电极的功函数，从而在FET中的沟道掺杂和驱动电流之间获得期望的权衡。

67. 发明授权

US06790704B2 Method for capacitively coupling electronic devices 有权
标题翻译：电容耦合电子器件的方法
公开(公告)号：US06790704B2
公开(公告)日：2004-09-14
申请号：US09908016
申请日：2001-07-17
申请人： Brian Doyle , Quat T. Vu , David B. Fraser
发明人： Brian Doyle , Quat T. Vu , David B. Fraser
IPC分类号： H01L2144
CPC分类号： H01L23/642 , H01L23/48 , H01L25/18 , H01L2224/16
摘要： A method for electrically coupling a first set of electrically conductive pads on a first semiconductor substrate to a second set of electrically conductive pads on a second semiconductor substrate is described. Dielectric material of a first thickness is deposited on at least one set of the first and second sets of electrically conductive pads. The first and second semiconductor substrates are then attached together such that such that the first and second sets of pads are substantially aligned parallel to one another and such that the dielectric material is disposed between the first and second sets of electrically conductive pads.
摘要翻译：描述了将第一半导体衬底上的第一组导电焊盘电耦合到第二半导体衬底上的第二组导电焊盘的方法。第一厚度的介电材料沉积在至少一组第一和第二组导电焊盘上。然后将第一和第二半导体衬底附接在一起，使得第一组和第二组衬垫基本上彼此平行对准，并且使得电介质材料设置在第一组和第二组导电衬垫之间。

68. 发明授权

US06784491B2 MOS devices with reduced fringing capacitance 失效
标题翻译：具有减小的边缘电容的MOS器件
公开(公告)号：US06784491B2
公开(公告)日：2004-08-31
申请号：US10256978
申请日：2002-09-27
申请人： Brian Doyle , Jack Kavalieros
发明人： Brian Doyle , Jack Kavalieros
IPC分类号： H01L2976
CPC分类号： H01L29/6653 , H01L21/28044 , H01L21/28114 , H01L29/42376 , H01L29/66545 , H01L29/66553 , Y10S438/926
摘要： An embodiment of the present invention includes a gate dielectric layer, a polysilicon layer, and a gate electrode. The gate dielectric layer is on a substrate. The substrate has a gate area, a source area, and a drain area. The polysilicon layer is on the gate dielectric layer at the gate area. The gate electrode is on the polysilicon layer and has arc-shaped sidewalls.
摘要翻译：本发明的实施例包括栅介电层，多晶硅层和栅电极。栅介电层位于基板上。衬底具有栅极区域，源极区域和漏极区域。多晶硅层位于栅极区域的栅极介质层上。栅电极在多晶硅层上并具有弧形侧壁。

69. 发明授权

US06228691B1 Silicon-on-insulator devices and method for producing the same 有权
标题翻译：绝缘体上硅器件及其制造方法
公开(公告)号：US06228691B1
公开(公告)日：2001-05-08
申请号：US09343221
申请日：1999-06-30
申请人： Brian Doyle
发明人： Brian Doyle
IPC分类号： H01L21339
CPC分类号： B82Y10/00 , H01L21/76264 , H01L21/76272
摘要： A process of producing controllable thicknesses of silicon-on-insulator (SOI) for fully-depleted double-gate applications is provided. The process comprises depositing an oxide layer on a silicon wafer, depositing a nitride layer of a controlled thickness on the oxide layer, etching the nitride layer to open a first trench of controlled thickness, opening a second trench down to the silicon substrate, growing epitaxial silicon using epitaxial lateral overgrowth (ELO) to fill the second trench and grow sideways to fill the first trench, perform planarization of ELO silicon using the nitride layer as a chemical-mechanical polishing (CMP) stop layer, and fabricating a SOI device in the first trench.
摘要翻译：提供了一种用于完全耗尽双栅极应用的用于制造绝缘体上硅（SOI）的可控厚度的工艺。该方法包括在硅晶片上沉积氧化物层，在氧化物层上沉积受控厚度的氮化物层，蚀刻氮化物层以打开受控厚度的第一沟槽，将第二沟槽向下打开至硅衬底，生长外延使用外延横向过度生长（ELO）来填充第二沟槽并横向生长以填充第一沟槽，使用氮化物层作为化学机械抛光（CMP）停止层来执行ELO硅的平坦化，并且在第一沟

70. 发明授权

US6025254A Low resistance gate electrode layer and method of making same 失效
标题翻译：低电阻栅电极层及其制造方法
公开(公告)号：US6025254A
公开(公告)日：2000-02-15
申请号：US997038
申请日：1997-12-23
申请人： Brian Doyle , Gang Bai
发明人： Brian Doyle , Gang Bai
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H01L21/283
CPC分类号： H01L29/66507 , H01L21/28052 , H01L29/4925
摘要： A MOSFET having a low resistance gate electrode structure includes silicided source and drain regions, and a silicided gate electrode wherein the thickness of the silicide layer superjacent the gate electrode is substantially thicker than the silicide layers overlying the source and drain regions.A process in accordance with the present invention decouples the silicidation of MOSFET source/drain regions from the silicidation of the gate electrode.
摘要翻译：具有低电阻栅电极结构的3A MOSFET包括硅化源极和漏极区以及硅化物栅极，其中超过栅电极的硅化物层的厚度基本上比覆盖源极和漏极区的硅化物层厚。根据本发明的方法将MOSFET源极/漏极区的硅化物与栅电极的硅化物解耦。

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