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61. 发明申请

US20100169628A1 Controlling non-redundant execution in a redundant multithreading (RMT) processor 有权
标题翻译：控制冗余多线程（RMT）处理器中的非冗余执行
公开(公告)号：US20100169628A1
公开(公告)日：2010-07-01
申请号：US12317802
申请日：2008-12-30
申请人： Glenn J. Hinton , Steven E. Raasch , Sebastien Hily , John G. Holm , Ronak Singhal , Avinash Sodani , Deborah T. Marr
发明人： Glenn J. Hinton , Steven E. Raasch , Sebastien Hily , John G. Holm , Ronak Singhal , Avinash Sodani , Deborah T. Marr
IPC分类号： G06F9/38
CPC分类号： G06F11/1683 , G06F9/30189 , G06F9/3851 , G06F9/3857 , G06F9/3861 , G06F9/3891 , G06F11/1641 , G06F11/1658
摘要： In one embodiment, the present invention includes a method for controlling redundant execution such that if an exceptional event occurs, the redundant execution is stopped, non-redundant execution is performed in one of the threads until the exceptional event has been-resolved, after which a state of the threads is synchronized, and redundant execution is continued. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于控制冗余执行的方法，使得如果出现异常事件，则停止冗余执行，在其中一个线程中执行非冗余执行，直到异常事件被解析为止线程的状态被同步，并且继续冗余执行。描述和要求保护其他实施例。

62. 发明授权

US06256745B1 Processor having execution core sections operating at different clock rates 有权
标题翻译：具有执行核心部分以不同时钟速率工作的处理器
公开(公告)号：US06256745B1
公开(公告)日：2001-07-03
申请号：US09527065
申请日：2000-03-16
申请人： David J. Sager , Thomas D. Fletcher , Glenn J. Hinton , Michael D. Upton
发明人： David J. Sager , Thomas D. Fletcher , Glenn J. Hinton , Michael D. Upton
IPC分类号： G06F106
CPC分类号： G06F1/02 , G06F1/06 , G06F1/08 , G06F9/30145 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3869 , G06F15/7832
摘要： A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.
摘要翻译：一种处理器，包括以第一时钟频率执行执行操作的第一执行核心部分和第二执行核心部分，其被计时以在与第一时钟频率不同的第二时钟频率执行执行操作。第二个执行核心部分运行速度更快，包括数据高速缓存和关键的ALU功能，而第一个执行核心部分包括延迟容忍功能，如指令提取和解码单元以及非关键ALU功能。处理器还可以包括可能比第一执行核心部分慢的I / O环，可选地，第一执行核心部分可以包括其时钟速率在第一和第二执行核心部分之间的时钟速率的第三执行核心部分。可以在各部分之间使用时钟乘法器/分频器，以从单个源（例如I / O时钟）导出其时钟。

63. 发明授权

US06185671B2 Checking data type of operands specified by an instruction using attributes in a tagged array architecture 失效
标题翻译：使用标记数组架构中的属性检查指令指定的操作数的数据类型
公开(公告)号：US06185671B2
公开(公告)日：2001-02-06
申请号：US09053358
申请日：1998-03-31
申请人： Vladimir Pentovski , Gerald Bennett , Stephen A. Fischer , Eric Heit , Glenn J. Hinton , Patrice L. Roussel
发明人： Vladimir Pentovski , Gerald Bennett , Stephen A. Fischer , Eric Heit , Glenn J. Hinton , Patrice L. Roussel
IPC分类号： G06F930
CPC分类号： G06F9/30192 , G06F9/30036 , G06F9/30105 , G06F9/30112 , G06F9/3013 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857 , G06F9/3863
摘要： The present invention discloses a method and apparatus for matching data types of operands in an instruction. A type code of an operand used by the instruction is determined. An attribute value of a storage element which corresponds to the operand is read from a speculative array. This attribute value is then compared with the type code.
摘要翻译：本发明公开了一种用于匹配指令中的操作数的数据类型的方法和装置。确定指令使用的操作数的类型代码。从推测阵列中读取对应于操作数的存储元件的属性值。然后将该属性值与类型代码进行比较。

64. 发明授权

US6018786A Trace based instruction caching 失效
标题翻译：基于跟踪的指令缓存
公开(公告)号：US6018786A
公开(公告)日：2000-01-25
申请号：US956375
申请日：1997-10-23
申请人： Robert F. Krick , Glenn J. Hinton , Michael D. Upton , David J. Sager , Chan W. Lee
发明人： Robert F. Krick , Glenn J. Hinton , Michael D. Upton , David J. Sager , Chan W. Lee
IPC分类号： G06F9/32 , G06F9/38 , G06F12/08 , G06F9/26 , G06F12/00
CPC分类号： G06F9/3808 , G06F12/0875 , G06F9/3802 , G06F9/3836
摘要： A cache memory is constituted with a data array and control logic. The data array includes a number of data lines, and the control logic operates to store a number of trace segments of instructions in the data lines, including trace segments that span multiple data lines. In one embodiment, each trace segment includes one or more trace segment members having one or more instructions, with each trace segment member occupying one data line, and the data lines of a multi-line trace segment being sequentially associated (logically). Retrieval of the trace segment members of a multi-line trace segment is accomplished by first locating the data line storing the first trace segment member of the trace segment, and then successively locating the remaining data lines storing the remaining trace segment members based on the data lines' logical sequential associations.
摘要翻译：高速缓冲存储器由数据阵列和控制逻辑构成。数据阵列包括许多数据线，并且控制逻辑操作以在数据线中存储多条迹线段，包括跨越多个数据线的迹线段。在一个实施例中，每个跟踪段包括具有一个或多个指令的一个或多个跟踪段成员，每个跟踪段成员占据一个数据线，并且多行跟踪段的数据线被顺序地相关联（逻辑地）。通过首先定位存储跟踪段的第一跟踪段成员的数据线，然后基于数据连续定位存储剩余跟踪段成员的剩余数据线，来检索多行跟踪段的跟踪段成员行的逻辑顺序关联。

65. 发明授权

US5870599A Computer system employing streaming buffer for instruction preetching 失效
标题翻译：计算机系统采用流缓冲器进行指令预处理
公开(公告)号：US5870599A
公开(公告)日：1999-02-09
申请号：US953226
申请日：1997-10-17
申请人： Glenn J. Hinton , Ashwani K. Gupta , Sunil R. Shenoy
发明人： Glenn J. Hinton , Ashwani K. Gupta , Sunil R. Shenoy
IPC分类号： G06F9/38 , G06F12/08 , G06F9/00 , G06F12/00
CPC分类号： G06F9/3814 , G06F12/0859 , G06F9/3802 , G06F12/0862 , G06F2212/6022
摘要： Streaming buffer renaming for memory accesses issued by a microprocessor to an external memory via a system bus allows up to N fetch accesses at any one time for M physical streaming buffer locations, where N is greater than M. When a fetch within the processor misses the instruction cache, the fetch address is placed in the streaming buffer. When the data has been fetched from the external memory, it is returned to the streaming buffer and placed into one of the M physical buffer locations. The data within the streaming buffer is returned to the instruction cache of the processor only if it is to be used in accordance with the computer program being executed.
摘要翻译：用于通过系统总线由微处理器发送到外部存储器的存储器访问的流缓冲器重命名允许在任何一个时间对于N个大于M的物理流缓冲器位置进行N次获取访问。当处理器中的提取错过指令缓存，将获取地址放置在流缓冲区中。当从外部存储器中取出数据时，它返回到流缓冲器并放入M个物理缓冲区之一。流缓冲器中的数据只有在要根据正在执行的计算机程序使用时才返回到处理器的指令高速缓存。

66. 发明授权

US5623628A Computer system and method for maintaining memory consistency in a pipelined, non-blocking caching bus request queue 失效
标题翻译：用于维持流水线，非阻塞缓存总线请求队列中的内存一致性的计算机系统和方法
公开(公告)号：US5623628A
公开(公告)日：1997-04-22
申请号：US205040
申请日：1994-03-02
申请人： James M. Brayton , Michael W. Rhodehamel , Nitin V. Sarangdhar , Glenn J. Hinton
发明人： James M. Brayton , Michael W. Rhodehamel , Nitin V. Sarangdhar , Glenn J. Hinton
IPC分类号： G06F9/38 , G06F12/08 , G06F13/18 , G06F12/00
CPC分类号： G06F12/0831 , G06F13/18 , G06F9/3017 , G06F9/3824 , G06F9/3828 , G06F9/3834
摘要： A computer system, and a method performed by it, having a mechanism for ensuring consistency of data among various level(s) of caching in a multi-level hierarchical memory system. The cache consistency mechanism includes an external bus request queue which and associated mechanism, which cooperate to monitor and control the issuance of data requests, such as read requests and write requests, onto an external bus. The computer system includes one or more CPUs each having this consistency mechanism.
摘要翻译：一种计算机系统及其执行的方法，具有用于确保在多级分层存储器系统中的各种级别的高速缓存之间的数据的一致性的机制。高速缓存一致性机制包括一个外部总线请求队列及其相关联的机制，它们协调监视和控制诸如读请求和写请求之类的数据请求的发布到外部总线上。计算机系统包括一个或多个具有这一一致性机制的CPU。

67. 发明授权

US5586278A Method and apparatus for state recovery following branch misprediction in an out-of-order microprocessor 失效
标题翻译：在无序微处理器中的分支错误预测之后状态恢复的方法和装置
公开(公告)号：US5586278A
公开(公告)日：1996-12-17
申请号：US639244
申请日：1996-04-22
申请人： David B. Papworth , Glenn J. Hinton
发明人： David B. Papworth , Glenn J. Hinton
IPC分类号： G06F9/38
CPC分类号： G06F9/3863
摘要： A method of state recovery following a branch misprediction or an undetected branch instruction. If, during execution of a branch instruction in an out-of-order unit, it is determined that the branch has been mispredicted, or if a taken branch has not been detected, then a JEClear signal is asserted to flush the instruction fetch unit and decoder section, and to change the instruction pointer to the actual target address. Within the out-of-order section, the instructions preceding the branch instruction are allowed to continue execution and proceed to in-order retirement. Simultaneously, instructions fetched at the actual target address are decoded, but not allowed to issue therefrom until the branch instruction has been retired from the out-of-order section, after which all instructions within the out-of-order section are flushed, and then decoded instructions are allowed to issue from the decoder. The state recovery method advantageously provides efficient utilization of processor time.
摘要翻译：分支错误预测或未检测到的分支指令之后的状态恢复方法。如果在执行无序单元中的分支指令时，确定分支已经被错误预测，或者如果未被检测到被采取的分支，则断言JEClear信号以刷新指令获取单元，并且解码器部分，并将指令指针更改为实际目标地址。在无序部分中，分支指令之前的指令被允许继续执行，并进行到订单退休。同时，在实际目标地址处获取的指令被解码，但是在分支指令已经从无序部分退出之前不允许发出指令，之后清除无序部分内的所有指令，以及则解码指令被允许从解码器发出。状态恢复方法有利地提供了处理器时间的有效利用。

68. 发明授权

US08407489B2 Method and apparatus for quick resumption 有权
公开(公告)号：US08407489B2
公开(公告)日：2013-03-26
申请号：US12384673
申请日：2009-04-07
申请人： Michael A. Rothman , Glenn J. Hinton , Mark S. Doran , Vincent J. Zimmer , Michael D. Kinney
发明人： Michael A. Rothman , Glenn J. Hinton , Mark S. Doran , Vincent J. Zimmer , Michael D. Kinney
IPC分类号： G06F9/24 , G06F15/177
CPC分类号： G06F1/3234 , G06F9/4418
摘要： When transitioning from sleep mode to active mode, a processing system loads first stage resume content and second stage resume content into a volatile memory of the processing system. The first stage resume content may contain contextual data for a first program that was in use before the processing system transitioned to sleep mode. The second stage resume content may contain contextual data for another program that was in use before the processing system transitioned to sleep mode. The processing system may provide a user interface for the first program before all of the second stage resume content has been loaded into the volatile memory. Other embodiments are described and claimed.

69. 发明申请

US20120166891A1 TWO-LEVEL SYSTEM MAIN MEMORY 有权
标题翻译：两级系统主要内存
公开(公告)号：US20120166891A1
公开(公告)日：2012-06-28
申请号：US12976545
申请日：2010-12-22
申请人： Eric J. Dahlen , Glenn J. Hinton , Raj K. Ramanujan
发明人： Eric J. Dahlen , Glenn J. Hinton , Raj K. Ramanujan
IPC分类号： G06F11/16 , G06F12/00
CPC分类号： G06F3/0611 , G06F3/0647 , G06F3/0685 , G06F11/0766 , G06F12/0246 , G06F12/0638 , G06F12/0868 , G06F12/0893 , G06F2212/1024 , G06F2212/313 , G06F2212/7203 , G06F2212/7208 , G06F2212/7209 , G06F2212/7211 , G11C14/009
摘要： Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes “near memory” comprising memory made of volatile memory, and “far memory” comprising volatile or nonvolatile memory storage that is larger and slower than the near memory.The far memory is presented as “main memory” to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.
摘要翻译：本发明的实施例描述了包括两级存储器的系统主存储器，其包括系统盘级存储器的缓存子集。该主存储器包括包括由易失性存储器构成的存储器的“近存储器”，以及包括比近存储器更大和更慢的易失性或非易失性存储器存储器的“远存储器”。远端存储器被呈现为主机OS的“主存储器”，而近端存储器是对于对OS是透明的远存储器的高速缓存，因此与OS显示与现有技术主存储器解决方案相同的高速缓存。两级存储器的管理可以通过经由主机CPU执行的逻辑和模块的组合来完成。靠近存储器可以通过高带宽，低延迟的方式耦合到主机系统CPU，用于有效处理。远存储器可以经由低带宽，高延迟装置耦合到CPU。

70. 发明授权

US08171219B2 Method and system to perform caching based on file-level heuristics 有权
标题翻译：基于文件级启发式方法和系统执行缓存
公开(公告)号：US08171219B2
公开(公告)日：2012-05-01
申请号：US12415595
申请日：2009-03-31
申请人： Sanjeev N. Trika , Amber D. Huffman , James A. Boyd , Frank T. Hady , Glenn J. Hinton , Dale J. Juenemann , Oscar P. Pinto , Scott R. Tetrick , Thomas J. Barnes , Scott E. Burridge
发明人： Sanjeev N. Trika , Amber D. Huffman , James A. Boyd , Frank T. Hady , Glenn J. Hinton , Dale J. Juenemann , Oscar P. Pinto , Scott R. Tetrick , Thomas J. Barnes , Scott E. Burridge
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F12/0866 , G06F12/0888 , G06F12/121 , G06F2212/222 , G06F2212/6028
摘要： A method and system to perform caching based at least on one or more file-level heuristics. The caching of a storage medium in a caching device is performed by a cache policy engine. The cache policy engine receives file-level information of input/output access of data of the storage medium and caches or evicts the data of the storage medium in the caching device based on the received file-level information. By utilizing information about the files and file operations associated with the disk sectors or logical block addresses of the storage medium, the cache policy engine can make a better decision on the data selection of the storage medium to be cached in or evicted from the caching device in one embodiment of the invention. Higher cache hit rates can be achieved and the performance of the system utilizing the cache policy engine is improved.
摘要翻译：至少基于一个或多个文件级启发式方法和系统执行缓存。缓存设备中的存储介质的缓存由高速缓存策略引擎执行。高速缓存策略引擎接收存储介质的数据的输入/输出访问的文件级信息，并基于接收到的文件级信息来高速缓存或者将高速缓存设备中的存储介质的数据移出。通过利用关于与存储介质的磁盘扇区或逻辑块地址相关联的文件和文件操作的信息，高速缓存策略引擎可以更好地决定要缓存到缓存设备或从高速缓存设备移出的存储介质的数据选择在本发明的一个实施例中。可以实现更高的缓存命中率，并提高利用缓存策略引擎的系统的性能。

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