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61. 发明申请

US20120193631A1 POLYSILICON CONTROL ETCH BACK INDICATOR 失效
标题翻译：多晶硅控制回退指示器
公开(公告)号：US20120193631A1
公开(公告)日：2012-08-02
申请号：US13431551
申请日：2012-03-27
申请人： Yu Wang , Tiesheng Li , Sung-Shan Tai , Hong Chang
发明人： Yu Wang , Tiesheng Li , Sung-Shan Tai , Hong Chang
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L22/12 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/66734 , H01L2924/0002 , H01L2924/00
摘要： This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions.
摘要翻译：本发明公开了一种用于在其上制造电子电路的半导体晶片。半导体衬底还包括回蚀指示器，其包括不同尺寸的沟槽，其具有填充在沟槽中的多晶硅，然后从更大的平面沟槽尺寸的一些沟槽中完全去除，并且多晶硅仍保留在一些沟槽中的底部具有较小的平面沟槽尺寸。

62. 发明授权

US08058687B2 Split gate with different gate materials and work functions to reduce gate resistance of ultra high density MOSFET 有权
标题翻译：分闸具有不同的栅极材料和工作功能，可降低超高密度MOSFET的栅极电阻
公开(公告)号：US08058687B2
公开(公告)日：2011-11-15
申请号：US11700688
申请日：2007-01-30
申请人： Sung-Shan Tai , YongZhong Hu
发明人： Sung-Shan Tai , YongZhong Hu
IPC分类号： H01L29/66
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/41766 , H01L29/4958 , H01L29/66727 , H01L29/66734
摘要： This invention discloses a trenched metal oxide semiconductor field effect transistor (MOSFET) cell. The trenched MOSFET cell includes a trenched gate opened from a top surface of the semiconductor substrate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The trenched gate further includes at least two mutually insulated trench-filling segments each filled with materials of different work functions. In an exemplary embodiment, the trenched gate includes a polysilicon segment at a bottom portion of the trenched gate and a metal segment at a top portion of the trenched gate.
摘要翻译：本发明公开了一种沟槽金属氧化物半导体场效应晶体管（MOSFET）单元。沟槽MOSFET单元包括从半导体衬底的顶表面开口的沟槽栅极，该沟槽被包围在布置在衬底底表面上的漏区以上的体区中的源极区围绕。沟槽栅还包括至少两个相互绝缘的沟槽填充段，每个填充段具有不同功函数的材料。在示例性实施例中，沟槽栅极包括在沟槽栅极的底部处的多晶硅段和在沟槽栅极顶部的金属段。

63. 发明授权

US08022482B2 Device configuration of asymmetrical DMOSFET with schottky barrier source 有权
标题翻译：具有肖特基势垒源的非对称DMOSFET的器件配置
公开(公告)号：US08022482B2
公开(公告)日：2011-09-20
申请号：US11355128
申请日：2006-02-14
申请人： Yongzhong Hu , Sung-Shan Tai
发明人： Yongzhong Hu , Sung-Shan Tai
IPC分类号： H01L27/108 , H01L29/94 , H01L21/08 , H01L27/088 , H01L29/40 , H01L23/12 , H01L23/48 , H01L23/52 , H01L29/417 , H01L29/45 , H01L29/78 , H01L29/812
CPC分类号： H01L29/7813 , H01L21/28518 , H01L21/823418 , H01L29/41766 , H01L29/456 , H01L29/665 , H01L29/66507 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7839 , H01L29/7845 , H01L2924/0002 , H01L2924/00 , H01L2924/1082
摘要： A trenched semiconductor power device includes a trenched gate insulated by a gate insulation layer and surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a semiconductor substrate. The source region surrounding the trenched gate includes a metal of low barrier height to function as a Schottky source. The metal of low barrier height further may include a PtSi or ErSi layer. In a preferred embodiment, the metal of low barrier height further includes an ErSi layer. The metal of low barrier height further may be a metal silicide layer having the low barrier height. A top oxide layer is disposed under a silicon nitride spacer on top of the trenched gate for insulating the trenched gate from the source region. A source contact disposed in a trench opened into the body region for contacting a body-contact dopant region and covering with a conductive metal layer such as a Ti/TiN layer. In a preferred embodiment, the semiconductor power device constitutes an asymmetrical double diffusion metal oxide semiconductor field effect transistor (DMOSFET) device.
摘要翻译：沟槽半导体功率器件包括由栅极绝缘层绝缘并被包围在设置在半导体衬底的底表面上的漏极区域上方的体区中的源极区包围的沟槽栅极。围绕沟槽栅极的源极区域包括具有低势垒高度的金属，用作肖特基源。低阻挡高度的金属还可以包括PtSi或ErSi层。在优选实施例中，低势垒高度的金属还包括ErSi层。低势垒高度的金属还可以是具有低势垒高度的金属硅化物层。顶部氧化物层设置在沟槽栅极顶部的氮化硅间隔物下方，用于使沟槽栅极与源极区域绝缘。源极接触件，设置在沟槽内，开口到体区，用于接触体接触掺杂区域并用诸如Ti / TiN层的导电金属层覆盖。在优选实施例中，半导体功率器件构成非对称双扩散金属氧化物半导体场效应晶体管（DMOSFET）器件。

64. 发明授权

US07928507B2 Polysilicon control etch-back indicator 有权
公开(公告)号：US07928507B2
公开(公告)日：2011-04-19
申请号：US12653130
申请日：2009-12-09
申请人： Yu Wang , Tiesheng Li , Sung-Shan Tai , Hong Chang
发明人： Yu Wang , Tiesheng Li , Sung-Shan Tai , Hong Chang
IPC分类号： H01L29/66 , H01L29/06
CPC分类号： H01L29/7813 , H01L22/12 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/66734 , H01L2924/0002 , H01L2924/00
摘要： This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions.

65. 发明申请

US20110049618A1 FABRICATION OF TRENCH DMOS DEVICE HAVING THICK BOTTOM SHIELDING OXIDE 有权
标题翻译：具有厚度底层氧化物的TRENCH DMOS器件的制造
公开(公告)号：US20110049618A1
公开(公告)日：2011-03-03
申请号：US12551417
申请日：2009-08-31
申请人： Yeeheng Lee , Sung-Shan Tai , Hong Chang , John Chen
发明人： Yeeheng Lee , Sung-Shan Tai , Hong Chang , John Chen
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/513 , H01L29/66719 , H01L29/66734
摘要： Semiconductor device fabrication method and devices are disclosed. A device may be fabricated by forming in a semiconductor layer; filling the trench with an insulating material; removing selected portions of the insulating material leaving a portion of the insulating material in a bottom portion of the trench; forming one or more spacers on one or more sidewalls of a remaining portion of the trench; anisotropically etching the insulating material in the bottom portion of the trench using the spacers as a mask to form a trench in the insulator; removing the spacers; and filling the trench in the insulator with a conductive material. Alternatively, an oxide-nitride-oxide (ONO) structure may be formed on a sidewall and at a bottom of the trench and one or more conductive structures may be formed in a portion of the trench not occupied by the ONO structure.
摘要翻译：公开了半导体器件制造方法和器件。可以通过在半导体层中形成来制造器件; 用绝缘材料填充沟槽; 去除所述绝缘材料的选定部分，使所述绝缘材料的一部分留在所述沟槽的底部; 在所述沟槽的剩余部分的一个或多个侧壁上形成一个或多个间隔物; 使用间隔物作为掩模对沟槽的底部中的绝缘材料进行各向异性蚀刻，以在绝缘体中形成沟槽; 去除垫片; 并用导电材料填充绝缘体中的沟槽。或者，可以在沟槽的侧壁和底部形成氧化物 - 氧化物（ONO）结构，并且可以在未被ONO结构占据的沟槽的一部分中形成一个或多个导电结构。

66. 发明申请

US20080179668A1 Split gate with different gate materials and work functions to reduce gate resistance of ultra high density MOSFET 有权
标题翻译：分闸具有不同的栅极材料和工作功能，可降低超高密度MOSFET的栅极电阻
公开(公告)号：US20080179668A1
公开(公告)日：2008-07-31
申请号：US11700688
申请日：2007-01-30
申请人： Sung-Shan Tai , YongZhong Hu
发明人： Sung-Shan Tai , YongZhong Hu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/41766 , H01L29/4958 , H01L29/66727 , H01L29/66734
摘要： This invention discloses a trenched metal oxide semiconductor field effect transistor (MOSFET) cell. The trenched MOSFET cell includes a trenched gate opened from a top surface of the semiconductor substrate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The trenched gate further includes at least two mutually insulated trench-filling segments each filled with materials of different work functions. In an exemplary embodiment, the trenched gate includes a polysilicon segment at a bottom portion of the trenched gate and a metal segment at a top portion of the trenched gate.
摘要翻译：本发明公开了一种沟槽金属氧化物半导体场效应晶体管（MOSFET）单元。沟槽MOSFET单元包括从半导体衬底的顶表面开口的沟槽栅极，该沟槽被包围在布置在衬底底表面上的漏区以上的体区中的源极区围绕。沟槽栅还包括至少两个相互绝缘的沟槽填充段，每个填充段具有不同功函数的材料。在示例性实施例中，沟槽栅极包括在沟槽栅极的底部处的多晶硅段和在沟槽栅极顶部的金属段。

67. 发明申请

US20070281418A1 Formation of high sheet resistance resistors and high capacitance capacitors by a single polysilicon process 有权
标题翻译：通过单个多晶硅工艺形成高电阻电阻器和高容量电容器
公开(公告)号：US20070281418A1
公开(公告)日：2007-12-06
申请号：US11444852
申请日：2006-05-31
申请人： YongZhong Hu , Sung-Shan Tai
发明人： YongZhong Hu , Sung-Shan Tai
IPC分类号： H01L21/8244
CPC分类号： H01L27/0629 , H01L28/20 , H01L28/60 , Y10S438/957
摘要： A semiconductor device includes a transistor, a capacitor and a resistor wherein the capacitor includes a doped polysilicon layer to function as a bottom conductive layer with a salicide block (SAB) layer as a dielectric layer covered by a Ti/TiN layer as a top conductive layer thus constituting a single polysilicon layer metal-insulator-polysilicon (MIP) structure. While the high sheet rho resistor is also formed on the same single polysilicon layer with differential doping of the polysilicon layer.
摘要翻译：半导体器件包括晶体管，电容器和电阻器，其中电容器包括用作底部导电层的掺杂多晶硅层，其中具有作为顶部导电的Ti / TiN层覆盖的电介质层的硅化物块（SAB）层从而构成单个多晶硅层金属 - 绝缘体 - 多晶硅（MIP）结构。虽然高片rho电阻也形成在同一个多晶硅层上，多晶硅层的差分掺杂。

68. 发明申请

US20070158701A1 Excessive round-hole shielded gate trench (SGT) MOSFET devices and manufacturing processes 有权
标题翻译：过多的圆孔屏蔽栅沟槽（SGT）MOSFET器件和制造工艺
公开(公告)号：US20070158701A1
公开(公告)日：2007-07-12
申请号：US11321957
申请日：2005-12-28
申请人： Hong Chang , Sung-Shan Tai , Tiesheng Li , Yu Wang
发明人： Hong Chang , Sung-Shan Tai , Tiesheng Li , Yu Wang
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L21/76232 , H01L29/4236 , H01L29/42376 , H01L29/66621 , H01L29/7834
摘要： This invention discloses an improved trenched metal oxide semiconductor field effect transistor (MOSFET) device that includes a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The MOSFET cell further includes a shielded gate trench (SGT) structure below and insulated from the trenched gate. The SGT structure is formed substantially as a round hole having a lateral expansion extended beyond the trench gate and covered by a dielectric linen layer filled with a trenched gate material. The round hole is formed by an isotropic etch at the bottom of the trenched gate and is insulated from the trenched gate by an oxide insulation layer. The round hole has a lateral expansion beyond the trench walls and the lateral expansion serves as a vertical alignment landmark for controlling the depth of the trenched gate. The MOSFET device has a reduced gate to drain capacitance Cgd depending on the controllable depth of the trenched gate disposed above the SGT structure formed as a round hole below the trenched gate.
摘要翻译：本发明公开了一种改进的沟槽金属氧化物半导体场效应晶体管（MOSFET）器件，其包括被包围在设置在衬底的底表面上的漏区以上的体区中的源极区包围的沟槽栅极。 MOSFET单元进一步包括屏蔽栅极沟槽（SGT）结构，并且与沟槽栅极绝缘。 SGT结构基本上形成为具有延伸超过沟槽栅极并由填充有沟槽栅极材料的电介质亚麻层覆盖的圆形孔。圆形孔通过在沟槽底部的各向同性蚀刻形成，并且通过氧化物绝缘层与沟槽栅极绝缘。圆孔具有超出沟槽壁的横向膨胀，并且横向膨胀用作用于控制沟槽浇口的深度的垂直对准界标。 MOSFET器件具有减小的栅极到漏极电容Cgd，这取决于设置在形成为沟槽栅极下方的圆孔的SGT结构之上的沟槽栅极的可控深度。

69. 发明申请

US20070069297A1 Tri-states one-time programmable memory (OTP) cell 有权
标题翻译：三态一次可编程存储器（OTP）单元
公开(公告)号：US20070069297A1
公开(公告)日：2007-03-29
申请号：US11541369
申请日：2006-09-30
申请人： YongZhong Hu , Yu Chang , Sung-Shan Tai
发明人： YongZhong Hu , Yu Chang , Sung-Shan Tai
IPC分类号： H01L23/62
CPC分类号： G11C17/16 , G11C17/18 , H01L27/112 , H01L27/11206
摘要： A method of performing a programming, testing and trimming operation is disclosed in this invention. The method includes a step of applying a programming circuit for programming an OTP memory for probing and sensing one of three different states of the OTP memory for carrying out a trimming operation using one of the three states of the OTP memory whereby a higher utilization of OTP memory cells is achieved. Selecting and programming two conductive circuits of the OTP into two different operational characteristics thus enables the storing and sensing one of the three different states of the OTP memory. These two conductive circuits may include two different transistors for programming into a linear resistor and a nonlinear resistor with different current conducting characteristics. The programming processes include application of a high voltage and different programming currents thus generating different operational characteristics of these two transistors.
摘要翻译：在本发明中公开了执行编程，测试和修整操作的方法。该方法包括应用用于对OTP存储器进行编程的编程电路的步骤，用于探测和感测OTP存储器的三种不同状态之一，以使用OTP存储器的三种状态之一进行修整操作，由此OTP的较高利用率实现了存储单元。将OTP的两个导电电路选择和编程成两个不同的操作特性，因此能够存储和感测OTP存储器的三种不同状态之一。这两个导电电路可以包括用于编程成线性电阻器的两个不同晶体管和具有不同电流传导特性的非线性电阻器。编程过程包括应用高电压和不同的编程电流，从而产生这两个晶体管的不同操作特性。

70. 发明授权

US09337329B2 Method of fabrication and device configuration of asymmetrical DMOSFET with schottky barrier source 有权
标题翻译：具有肖特基势垒源的非对称DMOSFET的制造方法和器件配置
公开(公告)号：US09337329B2
公开(公告)日：2016-05-10
申请号：US13199795
申请日：2011-09-08
申请人： Yongzhong Hu , Sung-Shan Tai
发明人： Yongzhong Hu , Sung-Shan Tai
IPC分类号： H01L21/8234 , H01L29/78 , H01L29/66 , H01L21/285 , H01L29/417 , H01L29/45
CPC分类号： H01L29/7813 , H01L21/28518 , H01L21/823418 , H01L29/41766 , H01L29/456 , H01L29/665 , H01L29/66507 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7839 , H01L29/7845 , H01L2924/0002 , H01L2924/00 , H01L2924/1082
摘要： A trenched semiconductor power device includes a trenched gate insulated by a gate insulation layer and surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a semiconductor substrate. The source region surrounding the trenched gate includes a metal of low barrier height to function as a Schottky source and that may include a PtSi, ErSi layer and may further be a metal silicide layer having the low barrier height. A top oxide layer is disposed under a silicon nitride spacer on top of the trenched gate for insulating the trenched gate from the source region. A source contact disposed in a trench opened into the body region for contacting a body-contact dopant region and covering with a conductive metal layer such as a Ti/TiN layer.
摘要翻译：沟槽半导体功率器件包括由栅极绝缘层绝缘并被包围在设置在半导体衬底的底表面上的漏极区域上方的体区中的源极区包围的沟槽栅极。围绕沟槽栅极的源极区域包括低势垒高度的金属，用作肖特基源并且可以包括PtSi，ErSi层，并且还可以是具有低势垒高度的金属硅化物层。顶部氧化物层设置在沟槽栅极顶部的氮化硅间隔物下方，用于使沟槽栅极与源极区域绝缘。源极接触件，设置在沟槽内，开口到体区，用于接触体接触掺杂区域并用诸如Ti / TiN层的导电金属层覆盖。

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