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1. 发明授权

US08252647B2 Fabrication of trench DMOS device having thick bottom shielding oxide 有权
标题翻译：具有厚底层屏蔽氧化物的沟槽DMOS器件的制造
公开(公告)号：US08252647B2
公开(公告)日：2012-08-28
申请号：US12551417
申请日：2009-08-31
申请人： Yeeheng Lee , Sung-Shan Tai , Hong Chang , John Chen
发明人： Yeeheng Lee , Sung-Shan Tai , Hong Chang , John Chen
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/513 , H01L29/66719 , H01L29/66734
摘要： Semiconductor device fabrication method and devices are disclosed. A device may be fabricated by forming in a semiconductor layer; filling the trench with an insulating material; removing selected portions of the insulating material leaving a portion of the insulating material in a bottom portion of the trench; forming one or more spacers on one or more sidewalls of a remaining portion of the trench; anisotropically etching the insulating material in the bottom portion of the trench using the spacers as a mask to form a trench in the insulator; removing the spacers; and filling the trench in the insulator with a conductive material. Alternatively, an oxide-nitride-oxide (ONO) structure may be formed on a sidewall and at a bottom of the trench and one or more conductive structures may be formed in a portion of the trench not occupied by the ONO structure.
摘要翻译：公开了半导体器件制造方法和器件。可以通过在半导体层中形成来制造器件; 用绝缘材料填充沟槽; 去除所述绝缘材料的选定部分，使所述绝缘材料的一部分留在所述沟槽的底部; 在所述沟槽的剩余部分的一个或多个侧壁上形成一个或多个间隔物; 使用间隔物作为掩模对沟槽的底部中的绝缘材料进行各向异性蚀刻，以在绝缘体中形成沟槽; 去除垫片; 并用导电材料填充绝缘体中的沟槽。或者，可以在沟槽的侧壁和底部形成氧化物 - 氧化物（ONO）结构，并且可以在未被ONO结构占据的沟槽的一部分中形成一个或多个导电结构。

2. 发明申请

US20110049618A1 FABRICATION OF TRENCH DMOS DEVICE HAVING THICK BOTTOM SHIELDING OXIDE 有权
标题翻译：具有厚度底层氧化物的TRENCH DMOS器件的制造
公开(公告)号：US20110049618A1
公开(公告)日：2011-03-03
申请号：US12551417
申请日：2009-08-31
申请人： Yeeheng Lee , Sung-Shan Tai , Hong Chang , John Chen
发明人： Yeeheng Lee , Sung-Shan Tai , Hong Chang , John Chen
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/513 , H01L29/66719 , H01L29/66734
摘要： Semiconductor device fabrication method and devices are disclosed. A device may be fabricated by forming in a semiconductor layer; filling the trench with an insulating material; removing selected portions of the insulating material leaving a portion of the insulating material in a bottom portion of the trench; forming one or more spacers on one or more sidewalls of a remaining portion of the trench; anisotropically etching the insulating material in the bottom portion of the trench using the spacers as a mask to form a trench in the insulator; removing the spacers; and filling the trench in the insulator with a conductive material. Alternatively, an oxide-nitride-oxide (ONO) structure may be formed on a sidewall and at a bottom of the trench and one or more conductive structures may be formed in a portion of the trench not occupied by the ONO structure.
摘要翻译：公开了半导体器件制造方法和器件。可以通过在半导体层中形成来制造器件; 用绝缘材料填充沟槽; 去除所述绝缘材料的选定部分，使所述绝缘材料的一部分留在所述沟槽的底部; 在所述沟槽的剩余部分的一个或多个侧壁上形成一个或多个间隔物; 使用间隔物作为掩模对沟槽的底部中的绝缘材料进行各向异性蚀刻，以在绝缘体中形成沟槽; 去除垫片; 并用导电材料填充绝缘体中的沟槽。或者，可以在沟槽的侧壁和底部形成氧化物 - 氧化物（ONO）结构，并且可以在未被ONO结构占据的沟槽的一部分中形成一个或多个导电结构。

3. 发明授权

US09000514B2 Fabrication of trench DMOS device having thick bottom shielding oxide 有权
标题翻译：具有厚底层屏蔽氧化物的沟槽DMOS器件的制造
公开(公告)号：US09000514B2
公开(公告)日：2015-04-07
申请号：US13560247
申请日：2012-07-27
申请人： Yeeheng Lee , Sung-Shan Tai , Hong Chang , John Chen
发明人： Yeeheng Lee , Sung-Shan Tai , Hong Chang , John Chen
IPC分类号： H01L29/78 , H01L29/40 , H01L29/423 , H01L29/66 , H01L29/51
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/513 , H01L29/66719 , H01L29/66734
摘要： Semiconductor device fabrication method and devices are disclosed. A device may be fabricated by forming in a semiconductor layer; filling the trench with an insulating material; removing selected portions of the insulating material leaving a portion of the insulating material in a bottom portion of the trench; forming one or more spacers on one or more sidewalls of a remaining portion of the trench; anisotropically etching the insulating material in the bottom portion of the trench using the spacers as a mask to form a trench in the insulator; removing the spacers; and filling the trench in the insulator with a conductive material. Alternatively, an oxide-nitride-oxide (ONO) structure may be formed on a sidewall and at a bottom of the trench and one or more conductive structures may be formed in a portion of the trench not occupied by the ONO structure.
摘要翻译：公开了半导体器件制造方法和器件。可以通过在半导体层中形成来制造器件; 用绝缘材料填充沟槽; 去除所述绝缘材料的选定部分，使所述绝缘材料的一部分留在所述沟槽的底部; 在所述沟槽的剩余部分的一个或多个侧壁上形成一个或多个间隔物; 使用间隔物作为掩模对沟槽的底部中的绝缘材料进行各向异性蚀刻，以在绝缘体中形成沟槽; 去除垫片; 并用导电材料填充绝缘体中的沟槽。或者，氧化物 - 氧化物 - 氧化物（ONO）结构可以形成在沟槽的侧壁和底部，并且可以在不被ONO结构占据的沟槽的一部分中形成一个或多个导电结构。

4. 发明授权

US08847306B2 Direct contact in trench with three-mask shield gate process 有权
标题翻译：直接接触沟槽与三屏蔽屏蔽门工艺
公开(公告)号：US08847306B2
公开(公告)日：2014-09-30
申请号：US13343666
申请日：2012-01-04
申请人： Sung-Shan Tai , Hamza Yilmaz , Anup Bhalla , Hong Chang , John Chen
发明人： Sung-Shan Tai , Hamza Yilmaz , Anup Bhalla , Hong Chang , John Chen
IPC分类号： H01L29/66 , H01L21/336 , H01L29/423 , H01L29/78 , H01L29/40 , H01L29/45 , H01L29/49 , H01L29/08 , H01L21/265
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0869 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/456 , H01L29/4933 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A semiconductor substrate may be etched to form trenches with three different widths. A first conductive material is formed at the bottom of the trenches. A second conductive material separated by an insulator is formed over the first conductive material. A first insulator layer is formed on the trenches. A body layer is formed in the substrate. A source is formed in the body layer. A second insulator layer is formed on the trenches and source. Source and gate contacts are formed through the second insulator layer. Source and gate metal are formed on the second insulator layer. This abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
摘要翻译：可以蚀刻半导体衬底以形成具有三个不同宽度的沟槽。第一导电材料形成在沟槽的底部。在第一导电材料上方形成由绝缘体隔开的第二导电材料。在沟槽上形成第一绝缘体层。在衬底中形成体层。源体形成在体层中。在沟槽和源极上形成第二绝缘体层。源极和栅极触点通过第二绝缘体层形成。源极和栅极金属形成在第二绝缘体层上。提供该摘要以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

5. 发明申请

US20120098059A1 DIRECT CONTACT IN TRENCH WITH THREE-MASK SHIELD GATE PROCESS 有权
标题翻译：直接与三层屏蔽门过程接触
公开(公告)号：US20120098059A1
公开(公告)日：2012-04-26
申请号：US13343666
申请日：2012-01-04
申请人： Sung-Shan Tai , Hamza Yilmaz , Anup Bhalla , Hong Chang , John Chen
发明人： Sung-Shan Tai , Hamza Yilmaz , Anup Bhalla , Hong Chang , John Chen
IPC分类号： H01L21/28 , H01L29/78
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0869 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/456 , H01L29/4933 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A semiconductor substrate may be etched to form trenches with three different widths. A first conductive material is formed at the bottom of the trenches. A second conductive material separated by an insulator is formed over the first conductive material. A first insulator layer is formed on the trenches. A body layer is formed in the substrate. A source is formed in the body layer. A second insulator layer is formed on the trenches and source. Source and gate contacts are formed through the second insulator layer. Source and gate metal are formed on the second insulator layer. This abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
摘要翻译：可以蚀刻半导体衬底以形成具有三个不同宽度的沟槽。第一导电材料形成在沟槽的底部。在第一导电材料上方形成由绝缘体隔开的第二导电材料。在沟槽上形成第一绝缘体层。在衬底中形成体层。源体形成在体层中。在沟槽和源极上形成第二绝缘体层。源极和栅极触点通过第二绝缘体层形成。在第二绝缘体层上形成源极和栅极金属。提供该摘要以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

6. 发明授权

US08187939B2 Direct contact in trench with three-mask shield gate process 有权
标题翻译：直接接触沟槽与三屏蔽屏蔽门工艺
公开(公告)号：US08187939B2
公开(公告)日：2012-05-29
申请号：US12565611
申请日：2009-09-23
申请人： Sung-Shan Tai , Hamza Yilmaz , Anup Bhalla , Hong Chang , John Chen
发明人： Sung-Shan Tai , Hamza Yilmaz , Anup Bhalla , Hong Chang , John Chen
IPC分类号： H01L21/336 , H01L29/66
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0869 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/456 , H01L29/4933 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A semiconductor device and a method for making a semiconductor device are disclosed. A trench mask may be applied to a semiconductor substrate, which is etched to form trenches with three different widths. A first conductive material is formed at the bottom of the trenches. A second conductive material is formed over the first conductive material. An insulator layer separates the first and second conductive materials. A first insulator layer is deposited on top of the trenches. A body layer is formed in a top portion of the substrate. A source is formed in the body layer. A second insulator layer is applied on top of the trenches and the source. A contact mask is applied on top of the second insulator layer. Source and gate contacts are formed through the second insulator layer. Source and gate metal are formed on top of the second insulator layer.
摘要翻译：公开了半导体器件和制造半导体器件的方法。可以将沟槽掩模施加到半导体衬底，其被蚀刻以形成具有三个不同宽度的沟槽。第一导电材料形成在沟槽的底部。在第一导电材料上形成第二导电材料。绝缘体层分离第一和第二导电材料。第一绝缘体层沉积在沟槽的顶部。主体层形成在基板的顶部。源体形成在体层中。第二绝缘体层被施加在沟槽和源的顶部上。接触掩模施加在第二绝缘体层的顶部。源极和栅极触点通过第二绝缘体层形成。源极和栅极金属形成在第二绝缘体层的顶部上。

7. 发明申请

US20110068386A1 DIRECT CONTACT IN TRENCH WITH THREE-MASK SHIELD GATE PROCESS 有权
标题翻译：直接与三层屏蔽门过程接触
公开(公告)号：US20110068386A1
公开(公告)日：2011-03-24
申请号：US12565611
申请日：2009-09-23
申请人： Sung-Shan Tai , Hamza Yilmaz , Anup Bhalla , Hong Chang , John Chen
发明人： Sung-Shan Tai , Hamza Yilmaz , Anup Bhalla , Hong Chang , John Chen
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0869 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/456 , H01L29/4933 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A semiconductor device and a method for making a semiconductor device are disclosed. A trench mask may be applied to a semiconductor substrate, which is etched to form trenches with three different widths. A first conductive material is formed at the bottom of the trenches. A second conductive material is formed over the first conductive material. An insulator layer separates the first and second conductive materials. A first insulator layer is deposited on top of the trenches. A body layer is formed in a top portion of the substrate. A source is formed in the body layer. A second insulator layer is applied on top of the trenches and the source. A contact mask is applied on top of the second insulator layer. Source and gate contacts are formed through the second insulator layer. Source and gate metal are formed on top of the second insulator layer.
摘要翻译：公开了半导体器件和制造半导体器件的方法。可以将沟槽掩模施加到半导体衬底，其被蚀刻以形成具有三个不同宽度的沟槽。第一导电材料形成在沟槽的底部。在第一导电材料上形成第二导电材料。绝缘体层分离第一和第二导电材料。第一绝缘体层沉积在沟槽的顶部。主体层形成在基板的顶部。源体形成在体层中。第二绝缘体层被施加在沟槽和源的顶部上。接触掩模施加在第二绝缘体层的顶部。源极和栅极触点通过第二绝缘体层形成。源极和栅极金属形成在第二绝缘体层的顶部上。

8. 发明申请

US20100291744A1 HIGH DENSITY TRENCH MOSFET WITH SINGLE MASK PRE-DEFINED GATE AND CONTACT TRENCHES 有权
标题翻译：高密度TRENCH MOSFET，具有单面罩预定门和接触孔
公开(公告)号：US20100291744A1
公开(公告)日：2010-11-18
申请号：US12847863
申请日：2010-07-30
申请人： Yeeheng Lee , Hong Chang , Tiesheng Li , John Chen , Anup Bhalla
发明人： Yeeheng Lee , Hong Chang , Tiesheng Li , John Chen , Anup Bhalla
IPC分类号： H01L21/336
CPC分类号： H01L29/66621 , H01L21/26586 , H01L29/4236 , H01L29/78
摘要： Trench gate MOSFET devices may be formed using a single mask to define gate trenches and body contact trenches. A hard mask is formed on a surface of a semiconductor substrate. A trench mask is applied on the hard mask to predefine a body contact trench and a gate trench. These predefined trenches are simultaneously etched into the substrate to a first predetermined depth. A gate trench mask is next applied on top of the hard mask. The gate trench mask covers the body contact trenches and has openings at the gate trenches. The gate trench, but not the body contact trench, is etched to a second predetermined depth. Conductive material of a first kind may fill the gate trench to form a gate. Conductive material of a second kind may fill the body contact trench to form a body contact.
摘要翻译：沟槽栅极MOSFET器件可以使用单个掩模形成以限定栅极沟槽和主体接触沟槽。在半导体基板的表面上形成硬掩模。在硬掩模上施加沟槽掩模以预定义接触沟槽和栅极沟槽。这些预定沟槽同时被蚀刻到衬底中到达第一预定深度。接下来将栅极沟槽掩模施加在硬掩模的顶部上。栅极沟槽掩模覆盖主体接触沟槽并且在栅极沟槽处具有开口。栅极沟槽而不是体接触沟槽被蚀刻到第二预定深度。第一种导电材料可以填充栅沟以形成栅极。第二种导电材料可以填充身体接触沟槽以形成身体接触。

9. 发明授权

US07879676B2 High density trench mosfet with single mask pre-defined gate and contact trenches 有权
标题翻译：高密度沟槽mosfet与单一掩模预定义的门和接触沟槽
公开(公告)号：US07879676B2
公开(公告)日：2011-02-01
申请号：US12847863
申请日：2010-07-30
申请人： Yeeheng Lee , Hong Chang , Tiesheng Li , John Chen , Anup Bhalla
发明人： Yeeheng Lee , Hong Chang , Tiesheng Li , John Chen , Anup Bhalla
IPC分类号： H01L21/336
CPC分类号： H01L29/66621 , H01L21/26586 , H01L29/4236 , H01L29/78
摘要： Trench gate MOSFET devices may be formed using a single mask to define gate trenches and body contact trenches. A hard mask is formed on a surface of a semiconductor substrate. A trench mask is applied on the hard mask to predefine a body contact trench and a gate trench. These predefined trenches are simultaneously etched into the substrate to a first predetermined depth. A gate trench mask is next applied on top of the hard mask. The gate trench mask covers the body contact trenches and has openings at the gate trenches. The gate trench, but not the body contact trench, is etched to a second predetermined depth. Conductive material of a first kind may fill the gate trench to form a gate. Conductive material of a second kind may fill the body contact trench to form a body contact.
摘要翻译：沟槽栅极MOSFET器件可以使用单个掩模形成以限定栅极沟槽和主体接触沟槽。在半导体基板的表面上形成硬掩模。在硬掩模上施加沟槽掩模以预定义接触沟槽和栅极沟槽。这些预定沟槽同时被蚀刻到衬底中到达第一预定深度。接下来将栅极沟槽掩模施加在硬掩模的顶部上。栅极沟槽掩模覆盖主体接触沟槽并且在栅极沟槽处具有开口。栅极沟槽而不是体接触沟槽被蚀刻到第二预定深度。第一种导电材料可以填充栅沟以形成栅极。第二种导电材料可以填充身体接触沟槽以形成身体接触。

10. 发明申请

US20100190307A1 HIGH DENSITY TRENCH MOSFET WITH SINGLE MASK PRE-DEFINED GATE AND CONTACT TRENCHES 有权
标题翻译：高密度TRENCH MOSFET，具有单面罩预定门和接触孔
公开(公告)号：US20100190307A1
公开(公告)日：2010-07-29
申请号：US12362414
申请日：2009-01-29
申请人： Yeeheng Lee , Hong Chang , Tiesheng Li , John Chen , Anup Bhalla
发明人： Yeeheng Lee , Hong Chang , Tiesheng Li , John Chen , Anup Bhalla
IPC分类号： H01L21/336
CPC分类号： H01L29/66621 , H01L21/26586 , H01L29/4236 , H01L29/78
摘要： Trench gate MOSFET devices may be formed using a single mask to define gate trenches and body contact trenches. A hard mask is formed on a surface of a semiconductor substrate. A trench mask is applied on the hard mask to predefine a body contact trench and a gate trench. These predefined trenches are simultaneously etched into the substrate to a first predetermined depth. A gate trench mask is next applied on top of the hard mask. The gate trench mask covers the body contact trenches and has openings at the gate trenches that are wider than those trenches. The gate trench, but not the body contact trench, is etched to a second predetermined depth. Conductive material of a first kind may fill the gate trench to form a gate. Conductive material of a second kind may fill the body contact trench to form a body contact.
摘要翻译：沟槽栅极MOSFET器件可以使用单个掩模形成以限定栅极沟槽和主体接触沟槽。在半导体基板的表面上形成硬掩模。在硬掩模上施加沟槽掩模以预定义接触沟槽和栅极沟槽。这些预定沟槽同时被蚀刻到衬底中到达第一预定深度。接下来将栅极沟槽掩模施加在硬掩模的顶部上。栅极沟槽掩模覆盖主体接触沟槽，并且在栅极沟槽处具有比那些沟槽更宽的开口。栅极沟槽而不是体接触沟槽被蚀刻到第二预定深度。第一种导电材料可以填充栅沟以形成栅极。第二种导电材料可以填充身体接触沟槽以形成身体接触。

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