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61. 发明授权

US09214783B2 Light emitting device, lighting system, headlight, and vehicle 有权
标题翻译：发光装置，照明系统，大灯和车辆
公开(公告)号：US09214783B2
公开(公告)日：2015-12-15
申请号：US14004527
申请日：2012-03-05
申请人： Masaru Nomura , Yoshifumi Yaoi , Kohichiroh Adachi , Kohtaroh Kataoka , Takeshi Shiomi , Hiroshi Iwata , Yoshiji Ohta
发明人： Masaru Nomura , Yoshifumi Yaoi , Kohichiroh Adachi , Kohtaroh Kataoka , Takeshi Shiomi , Hiroshi Iwata , Yoshiji Ohta
IPC分类号： F21S8/10 , H01S5/00 , H01S5/042 , F21V9/16 , F21Y101/02 , H01S5/068 , H01S5/40
CPC分类号： H01S5/00 , F21S41/14 , F21S41/147 , F21S41/16 , F21V9/30 , F21Y2101/00 , F21Y2115/30 , H01S5/005 , H01S5/0078 , H01S5/042 , H01S5/06825 , H01S5/4018
摘要： A light emitting device which includes at least one of a laser light source (1), wiring (9), a lens for excitation (2), a luminous body (4), a laser cut filter (6), a half parabolic mirror (5P), and a base (5h), in which a part of the wiring (9) is installed at a portion in which a breakage easily occurs due to at least one deformation of the laser light source (1), the lens for excitation (2), the luminous body (4), the laser cut filter (6), the half parabolic mirror (5P), and the base (5h), or a change in an installation position thereof.
摘要翻译：一种发光器件，其包括激光源（1），布线（9），激发透镜（2），发光体（4），激光截止滤光器（6），半抛物面镜（5P）和基部（5h），其中一部分布线（9）安装在由于激光光源（1）的至少一个变形容易发生断裂的部分，用于激光（2），发光体（4），激光切割滤光片（6），半抛物面镜（5P）和基底（5h），或其安装位置的变化。

62. 发明申请

US20140168940A1 LASER-BEAM UTILIZATION DEVICE AND VEHICLE HEADLIGHT 有权
标题翻译：激光束利用装置和车辆头灯
公开(公告)号：US20140168940A1
公开(公告)日：2014-06-19
申请号：US14127127
申请日：2012-05-25
申请人： Takeshi Shiomi , Masaru Nomura , Yoshiji Ohta , Hiroshi Iwata , Koji Takahashi , Katsuhiko Kishimoto
发明人： Takeshi Shiomi , Masaru Nomura , Yoshiji Ohta , Hiroshi Iwata , Koji Takahashi , Katsuhiko Kishimoto
IPC分类号： F21V9/08 , F21S8/10
CPC分类号： F21V9/08 , B60Q1/0023 , F21S41/14 , F21S41/141 , F21S41/16 , F21S41/285 , F21V7/22 , F21V9/30 , F21Y2115/10 , F21Y2115/30
摘要： A headlamp (1) that utilizes a laser beam includes a scattered-light emitting unit (21) that emits scattered light upon receipt of a laser beam deviated from a predetermined path through which the laser beam is to pass or a predetermined irradiation region that is to be irradiated by the laser beam.
摘要翻译：使用激光束的前照灯（1）包括散射光发射单元（21），该散射光发射单元（21）在接收到从激光束将要通过的预定路径偏离的激光束时发射散射光，或者预定的照射区域是被激光束照射。

63. 发明授权

US08508978B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08508978B2
公开(公告)日：2013-08-13
申请号：US13114507
申请日：2011-05-24
申请人： Kazuya Ishihara , Mitsuru Nakura , Yoshiji Ohta
发明人： Kazuya Ishihara , Mitsuru Nakura , Yoshiji Ohta
IPC分类号： G11C11/00
CPC分类号： G11C7/12 , G11C8/08 , G11C13/0004 , G11C13/0007 , G11C13/0026 , G11C13/0069 , G11C2013/0071 , G11C2213/79 , G11C2213/82
摘要： A semiconductor memory device includes a memory cell array in which a plurality of memory cells is aligned in a matrix shape, each memory cell including a two-terminal memory element and a transistor for selection connected in series; a first voltage applying circuit that applies a writing voltage pulse to first bit lines; and a second voltage applying circuit that applies a pre-charge voltage to the first bit lines and second bit lines, wherein in a writing of a memory cell, after the second voltage applying circuit has pre-charged both ends of the memory cell to a same voltage, the first voltage applying circuit applies the writing voltage pulse via the first bit line that is directly connected to the transistor for selection, and the second voltage applying circuit applies the pre-charge voltage to the second bit line directly connected to the memory element.
摘要翻译：半导体存储器件包括其中多个存储器单元以矩阵形状排列的存储单元阵列，每个存储单元包括串联连接的两端存储元件和选择晶体管; 对第一位线施加写入电压脉冲的第一电压施加电路; 以及施加预充电电压到第一位线和第二位线的第二电压施加电路，其中在存储单元的写入中，在所述第二电压施加电路将所述存储器单元的两端预充电到第一电压施加电路经由直接连接到晶体管的第一位线施加写入电压脉冲用于选择，并且第二电压施加电路将预充电电压施加到直接连接到存储器的第二位线元件。

64. 发明申请

US20130049620A1 ILLUMINATION APPARATUS AND POWER SUPPLY CIRCUIT 有权
标题翻译：照明设备和电源电路
公开(公告)号：US20130049620A1
公开(公告)日：2013-02-28
申请号：US13598363
申请日：2012-08-29
申请人： Kenji KOMIYA , Takeshi Shiomi , Yoshifumi Yaoi , Masaru Nomura , Kohichiroh Adachi , Yoshiji Ohta , Hiroshi Iwata
发明人： Kenji KOMIYA , Takeshi Shiomi , Yoshifumi Yaoi , Masaru Nomura , Kohichiroh Adachi , Yoshiji Ohta , Hiroshi Iwata
IPC分类号： G05F3/08 , H02M7/04 , H05B37/00 , H02M7/217
CPC分类号： H02M1/4225 , H02M3/1582 , H02M2001/4291 , H05B33/0815 , Y02B20/346 , Y02B70/126
摘要： In order to offer a power supply circuit that can minimize the drop in efficiency by reducing losses during voltage conversion, in an improved-power factor circuit, a control circuit performs a step-up operation in which a control signal for turning on a first switching element (Tr1) and switching a second switching element (Tr2) is output, and a step-down operation in which a control signal for turning off the second switching element (Tr2) and switching the first switching element (Tr1) is output.
摘要翻译：为了提供能够通过减少电压转换时的损耗来最小化效率下降的电源电路，在改进的功率因数电路中，控制电路执行升压操作，其中用于接通第一开关的控制信号输出元件（Tr1）并切换第二开关元件（Tr2），并且输出用于关闭第二开关元件（Tr2）的控制信号和切换第一开关元件（Tr1）的降压操作。

65. 发明授权

US08120944B2 Control circuit for forming process on nonvolatile variable resistive element and control method for forming process 有权
标题翻译：用于在非易失性可变电阻元件上形成工艺的控制电路和用于形成工艺的控制方法
公开(公告)号：US08120944B2
公开(公告)日：2012-02-21
申请号：US12722851
申请日：2010-03-12
申请人： Suguru Kawabata , Kazuya Ishihara , Yoshiji Ohta
发明人： Suguru Kawabata , Kazuya Ishihara , Yoshiji Ohta
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0011 , G11C13/0064 , G11C13/0069 , G11C2013/0083 , G11C2213/34 , G11C2213/72 , G11C2213/79 , H01L27/24
摘要： A nonvolatile semiconductor memory device can carry out a forming process simultaneously on the nonvolatile variable resistive elements of memory cells and make the forming time shorter. The nonvolatile semiconductor memory device has a forming detection circuit provided between the memory cell array and the second selection line (bit line) decoder. The forming detection circuit detects the completion of the forming process for memory cells by measuring the fluctuation in the potential of second selection lines or the current flowing through the second selection lines when applying a voltage pulse for a forming process through the second selection lines simultaneously to the memory cells on which a forming process is to be carried out connected to the same first selection line (word line), and prevents a voltage from being applied to the second selection lines connected to the memory cells where the completion of the forming process is detected.
摘要翻译：非易失性半导体存储器件可以在存储单元的非易失性可变电阻元件上同时进行形成处理，并且使形成时间更短。非易失性半导体存储器件具有设置在存储单元阵列和第二选择线（位线））解码器之间的形成检测电路。形成检测电路通过测量当通过第二选择线同时施加用于形成处理的电压脉冲时第二选择线的电位的波动或流过第二选择线的电流来检测存储单元的形成处理的完成，要在其上执行形成处理的存储单元连接到相同的第一选择线（字线），并且防止电压施加到连接到形成处理完成的存储单元的第二选择线检测到。

66. 发明授权

US08111573B2 Nonvolatile semiconductor memory device and method of controlling the same 有权
标题翻译：非易失性半导体存储器件及其控制方法
公开(公告)号：US08111573B2
公开(公告)日：2012-02-07
申请号：US12611279
申请日：2009-11-03
申请人： Kazuya Ishihara , Yutaka Ishikawa , Yoshiji Ohta
发明人： Kazuya Ishihara , Yutaka Ishikawa , Yoshiji Ohta
IPC分类号： G11C7/00
CPC分类号： G11C8/12 , G11C8/18 , G11C13/0007 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/0064 , G11C13/0069 , G11C2213/32 , G11C2216/22
摘要： Provided is a nonvolatile semiconductor memory device capable of performing a writing action for a memory cell at high speed. The device includes a memory cell array having a first sub-bank and a second sub-bank each having a plurality of nonvolatile memory cells arranged in a form of a matrix; a row decoder shared by the first sub-bank and the second sub-bank; a first column decoder and a second column decoder provided in the first sub-bank and the second sub-bank, respectively; and a control circuit arranged to execute alternately a first action cycle to perform a programming action in the first sub-bank and a reading action for a programming verifying action in the second sub-bank and a second action cycle to perform the reading action for the programming verifying action in the first sub-bank and the programming action in the second sub-bank.
摘要翻译：提供了一种能够高速地对存储单元执行写入动作的非易失性半导体存储器件。该装置包括具有第一子库和第二子库的存储单元阵列，每个存储单元具有以矩阵形式布置的多个非易失性存储单元; 由第一子银行和第二子银行共享的行解码器; 分别设置在第一子行和第二子行中的第一列解码器和第二列解码器; 以及控制电路，被配置为交替地执行第一动作循环以在第一子存储体中执行编程动作，以及执行用于第二子存储体中的编程验证动作的读取动作和第二动作循环，以执行用于在第一子行中编程验证动作和第二子行中的编程动作。

67. 发明申请

US20120014163A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DRIVING THE SAME 有权
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US20120014163A1
公开(公告)日：2012-01-19
申请号：US13179839
申请日：2011-07-11
申请人： Shinobu Yamazaki , Yoshiji Ohta , Kazuya Ishihara , Mitsuru Nakura , Suguru Kawabata , Nobuyoshi Awaya
发明人： Shinobu Yamazaki , Yoshiji Ohta , Kazuya Ishihara , Mitsuru Nakura , Suguru Kawabata , Nobuyoshi Awaya
IPC分类号： G11C11/21
CPC分类号： G11C13/0007 , G11C7/1048 , G11C7/12 , G11C13/0004 , G11C13/0026 , G11C13/0038 , G11C13/0069 , G11C2013/0071 , G11C2213/79 , G11C2213/82
摘要： A semiconductor memory device includes a memory cell array where a plurality of memory cells are arranged in a matrix, each of the memory cells serially connecting a two-terminal type memory element and a transistor for selection, a first voltage applying circuit that applies a write voltage pulse to a bit line, and a second voltage applying circuit that applies a precharge voltage to a bit line and a common line. In writing the memory cell, after the second voltage applying circuit has both terminals of the memory cell previously precharged to the same voltage, the first voltage applying circuit applies the write voltage pulse to one terminal of the writing target memory cell via the bit line, and while the write voltage pulse is applied, the second voltage applying circuit maintains the application of the precharge voltage to the other terminal of the memory cell via the common line.
摘要翻译：半导体存储器件包括：存储单元阵列，其中多个存储单元以矩阵形式布置，每个存储单元串联连接两端型存储元件和晶体管供选择;第一施加电压电路，电压脉冲到位线，以及第二电压施加电路，其向位线和公共线施加预充电电压。在写入存储单元时，在第二电压施加电路具有先前预充电至相同电压的存储单元的两端，第一电压施加电路经由位线将写入电压脉冲施加到写入目标存储单元的一个端子，并且当施加写入电压脉冲时，第二电压施加电路通过公共线路将预充电电压保持到存储单元的另一个端子。

68. 发明申请

US20090237154A1 SEMICONDUCTOR DEVICE, LIQUID CRYSTAL DISPLAY DEVICE AND ELECTRONIC EQUIPMENT 有权
标题翻译：半导体器件，液晶显示器件和电子设备
公开(公告)号：US20090237154A1
公开(公告)日：2009-09-24
申请号：US12022785
申请日：2008-01-30
申请人： Hiroshi Iwata , Yoshiji Ohta
发明人： Hiroshi Iwata , Yoshiji Ohta
IPC分类号： H01L25/00
CPC分类号： G09G3/3648 , G09G2300/0809 , G09G2320/0214
摘要： The semiconductor device of the present invention has a circuit block in which m (m is an integer of not smaller than two) sets of first through m-th transistor columns where two or more transistors are connected in series, one terminal of the first through m-th transistor columns is connected to a first output node, and the other terminal of the first through m-th transistor columns is connected to a second output node. A control signal for substantially simultaneously turning on and off all the transistors of the first through m-th transistor columns is inputted to the control input terminals of the transistors of the first through m-th transistor columns.
摘要翻译：本发明的半导体器件具有其中两个或多个晶体管串联连接的第一至第m晶体管列的m（m为不小于2的整数）的电路块，第一至第第m晶体管列连接到第一输出节点，第一至第m晶体管列的另一端连接到第二输出节点。用于基本上同时导通和关断第一至第m晶体管列的所有晶体管的控制信号被输入到第一至第三晶体管列的晶体管的控制输入端。

69. 发明申请

US20070086238A1 Semiconductor memory device and electronic apparatus 失效
标题翻译：半导体存储器件和电子设备
公开(公告)号：US20070086238A1
公开(公告)日：2007-04-19
申请号：US11541719
申请日：2006-10-03
申请人： Yoshiji Ohta
发明人： Yoshiji Ohta
IPC分类号： G11C16/06
CPC分类号： G11C16/28
摘要： In the semiconductor storage device, in a read operation, a bit line charging/discharging section 101 performs discharge of bit lines of a memory cell array 100, and a counter counts discharge periods over which the potentials of bit lines come to a specified potential, based on a comparison result of a comparator comparing a potential of a bit line with a reference potential. Based on the comparison result, a reference value generation section 104 generates a reference value (RCi) for determining information stored in each of the memory cells. The above count value (CBUSi) and the above reference value (RCi) are compared with each other by a data decision circuit 108. Based on the comparison result, an output data control circuit 109 outputs information stored in each of the memory cells. This semiconductor storage device suppresses increases in chip area and power consumption and outputs memory cell information accurately.
摘要翻译：在半导体存储装置中，在读取操作中，位线充电/放电部分101执行存储单元阵列100的位线的放电，并且计数器计数位线的电位达到指定电位的放电周期，基于比较器将比特线的电位与参考电位进行比较的比较结果。基于比较结果，参考值生成部104生成用于确定存储在每个存储单元中的信息的参考值（RCi）。通过数据判定电路108将上述计数值（CBUSi）和上述参考值（RCi）相互比较。根据比较结果，输出数据控制电路109输出存储在每个存储单元中的信息。该半导体存储装置抑制芯片面积和功耗的增加，并且准确地输出存储单元信息。

70. 发明申请

US20060217843A1 Group robot system, and sensing robot and base station used therefor 有权
公开(公告)号：US20060217843A1
公开(公告)日：2006-09-28
申请号：US11440958
申请日：2006-05-24
申请人： Keita Hara , Masaki Hamamoto , Yoshiji Ohta , Kenji Ohta
发明人： Keita Hara , Masaki Hamamoto , Yoshiji Ohta , Kenji Ohta
IPC分类号： G05B19/418
CPC分类号： G05D1/104 , B25J9/1682 , G05B2219/39155 , G05B2219/39168 , G05D2201/0207
摘要： Communication system of a group robot system is made hierarchical, having a base station as an uppermost layer and a plurality of layers formed by a plurality of sensing robots, and the plurality of sensing robots are controlled such that a sensing robot belonging to an upper layer of the hierarchical structure has higher sensing resolution than a sensing robot belonging to a lower layer of the hierarchical structure. Thus, a group robot system capable of efficiently searching for an object can be obtained.

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