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61. 发明授权

US5854510A Low power programmable fuse structures 失效
标题翻译：低功耗可编程保险丝结构
公开(公告)号：US5854510A
公开(公告)日：1998-12-29
申请号：US883403
申请日：1997-06-26
申请人： Harlan Lee Sur, Jr. , Subhas Bothra , Xi-Wei Lin , Martin H. Manley , Robert Payne
发明人： Harlan Lee Sur, Jr. , Subhas Bothra , Xi-Wei Lin , Martin H. Manley , Robert Payne
IPC分类号： H01C13/00 , H01L21/822 , H01L23/525 , H01L27/04 , H01L27/10 , H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/3011
摘要： Disclosed is a semiconductor fuse structure having a low power programming threshold and anti-reverse engineering characteristics. The fuse structure includes a substrate having a field oxide region. A polysilicon strip that has an increased dopant concentration region lies over the field oxide region. The fuse structure further includes a silicided metallization layer having first and second regions lying over the polysilicon strip. The first region has a first thickness, and the second region has a second thickness that is less than the first thickness and is positioned substantially over the increased dopant concentration region of the polysilicon strip. Preferably, the first region of the silicided metallization layer has a first side and a second side located on opposite sides of the second region, and the resulting fuse structure is substantially rectangular in shape. Therefore, the semiconductor fuse structure can be programmed by breaking the second region.
摘要翻译：公开了具有低功率编程阈值和抗逆向工程特性的半导体熔丝结构。熔丝结构包括具有场氧化物区域的衬底。具有增加的掺杂剂浓度区域的多晶硅条带位于场氧化物区域之上。熔丝结构还包括具有位于多晶硅条上的第一和第二区域的硅化金属化层。第一区域具有第一厚度，并且第二区域具有小于第一厚度的第二厚度，并且基本上位于多晶硅条的增加的掺杂剂浓度区域之上。优选地，硅化金属化层的第一区域具有位于第二区域的相对侧上的第一侧和第二侧，并且所得到的熔丝结构的形状基本上是矩形。因此，可以通过断开第二区域来编程半导体熔丝结构。

62. 发明授权

US5804502A Tungsten plugs for integrated circuits and methods for making same 失效
公开(公告)号：US5804502A
公开(公告)日：1998-09-08
申请号：US786366
申请日：1997-01-16
申请人： Calvin T. Gabriel , Dipankar Pramanik , Xi-Wei Lin
发明人： Calvin T. Gabriel , Dipankar Pramanik , Xi-Wei Lin
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/44
CPC分类号： H01L21/76843 , H01L21/76877 , H01L23/5226 , H01L23/53257 , H01L2924/0002
摘要： A method for producing a glue layer for an integrated circuit which uses tungsten plugs in accordance with the present invention includes: (A) providing a substrate which has a surface, a center, an edge, and a direction normal to the surface; and (B) sputter depositing a glue layer over the surface of the substrate such that an edge thickness of the glue layer measured in the direction normal to the surface at the edge of the substrate is at least 105% of a center thickness of the glue layer measured in the direction normal to the surface at the center of the substrate. In some embodiments, the edge thickness of said glue layer measured in the direction normal to the surface at the edge of the substrate is in the range of approximately 105% to 150% of the center thickness of the glue layer measured in the direction normal to the surface at the center of the substrate, as for example in the range of approximately 110% to 120% of the center thickness of the glue layer measured in the direction normal to the surface at the center of the substrate.

63. 发明授权

US08035168B2 Elevation of transistor channels to reduce impact of shallow trench isolation on transistor performance 有权
标题翻译：提高晶体管通道，减少浅沟槽隔离对晶体管性能的影响
公开(公告)号：US08035168B2
公开(公告)日：2011-10-11
申请号：US11364391
申请日：2006-02-27
申请人： Victor Moroz , Dipankar Pramanik , Xi-Wei Lin
发明人： Victor Moroz , Dipankar Pramanik , Xi-Wei Lin
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L21/823878 , H01L29/7846
摘要： Roughly described, transistor channel regions are elevated over the level of certain adjacent STI regions. Preferably the STI regions that are transversely adjacent to the diffusion regions are suppressed, as are STI regions that are longitudinally adjacent to N-channel diffusion regions. Preferably STI regions that are longitudinally adjacent to P-channel diffusions are not suppressed; preferably they have an elevation that is at least as high as that of the diffusion regions.
摘要翻译：粗略描述，晶体管沟道区域在某些相邻STI区域的水平上升高。优选地，与扩散区横向相邻的STI区域被抑制，与N沟道扩散区域纵向相邻的STI区也是如此。优选地，与P沟道扩散纵向相邻的STI区域不被抑制; 优选地，它们具有至少与扩散区域相同的高度。

64. 发明授权

US07949985B2 Method for compensation of process-induced performance variation in a MOSFET integrated circuit 有权
标题翻译： MOSFET集成电路中过程引起的性能变化的补偿方法
公开(公告)号：US07949985B2
公开(公告)日：2011-05-24
申请号：US11757338
申请日：2007-06-01
申请人： Victor Moroz , Dipankar Pramanik , Kishore Singhal , Xi-Wei Lin
发明人： Victor Moroz , Dipankar Pramanik , Kishore Singhal , Xi-Wei Lin
IPC分类号： G06F9/455 , G06F17/50 , G06F11/22
CPC分类号： G06F17/5068 , G06F17/5036
摘要： An automated method for compensating for process-induced variations in threshold voltage and drive current in a MOSFET integrated circuit. The method's first step is selecting a transistor for analysis from the array. The method loops among the transistors of the array as desired. Next the design of the selected transistor is analyzed, including the steps of determining threshold voltage variations induced by layout neighborhood; determining drive current variations induced by layout neighborhood. The method then proceeds by attempting to compensate for any determined variations by varying the length of the transistor gate. The method can further include the step of identifying any shortcoming in compensation by varying contact spacing.
摘要翻译：用于补偿MOSFET集成电路中阈值电压和驱动电流的过程引起的变化的自动化方法。该方法的第一步是从阵列中选择一个用于分析的晶体管。该方法根据需要在阵列的晶体管之间循环。接下来分析所选择的晶体管的设计，包括确定由布局邻域引起的阈值电压变化的步骤; 确定由布局邻域引起的驱动电流变化。该方法然后通过改变晶体管栅极的长度来尝试补偿任何确定的变化。该方法还可以包括通过改变接触间距来识别补偿中的任何缺点的步骤。

65. 发明授权

US07863146B2 Elevation of transistor channels to reduce impact of shallow trench isolation on transistor performance 有权
公开(公告)号：US07863146B2
公开(公告)日：2011-01-04
申请号：US11851325
申请日：2007-09-06
申请人： Victor Moroz , Dipankar Pramanik , Xi Wei Lin
发明人： Victor Moroz , Dipankar Pramanik , Xi Wei Lin
IPC分类号： H01L21/336 , H01L21/8238 , H01L21/76
CPC分类号： H01L21/823807 , H01L21/823878 , H01L29/7846
摘要： Roughly described, transistor channel regions are elevated over the level of certain adjacent STI regions. Preferably the STI regions that are transversely adjacent to the diffusion regions are suppressed, as are STI regions that are longitudinally adjacent to N-channel diffusion regions. Preferably STI regions that are longitudinally adjacent to P-channel diffusions are not suppressed; preferably they have an elevation that is at least as high as that of the diffusion regions.

66. 发明授权

US07767515B2 Managing integrated circuit stress using stress adjustment trenches 有权
标题翻译：使用应力调整沟槽管理集成电路应力
公开(公告)号：US07767515B2
公开(公告)日：2010-08-03
申请号：US11364392
申请日：2006-02-27
申请人： Victor Moroz , Dipankar Pramanik , Xi-Wei Lin
发明人： Victor Moroz , Dipankar Pramanik , Xi-Wei Lin
IPC分类号： H01L21/8238 , H01L21/76 , H01L21/4763 , G06F17/50
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/7846 , H01L29/7848
摘要： Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features can include dummy diffusion regions added to relax stress, and dummy trenches added either to relax or enhance stress. A trench can relax stress by filling it with a stress-neutral material or a tensile strained material. A trench can increase stress by filling it with a compressive strained material. Preferably dummy diffusion regions and stress relaxation trenches are disposed longitudinally to at least the channel regions of N-channel transistors, and transversely to at least the channel regions of both N-channel and P-channel transistors. Preferably stress enhancement trenches are disposed longitudinally to at least the channel regions of P-channel transistors.
摘要翻译：大致描述了改进集成电路布局和制造工艺的方法和系统，以便更好地解决应力影响。为了改善均匀性或放松已知的不良应力或引入已知的所需应力，可将虚拟特征添加到布局中。虚拟特征可以包括添加以放松应力的虚拟扩散区域，并且添加虚拟沟槽以放松或增强应力。沟槽可以通过用应力中性材料或拉伸应变材料填充来缓解应力。沟槽可以通过用压缩应变材料填充来增加应力。优选地，虚拟扩散区域和应力松弛沟槽纵向设置在N沟道晶体管的至少沟道区域上，并横向于N沟道和P沟道晶体管的至少沟道区域。优选地，应力增强沟槽纵向设置在至少P沟道晶体管的沟道区域上。

67. 发明授权

US07635618B2 Integrated circuit devices with high and low voltage components and processes for manufacturing these devices 有权
公开(公告)号：US07635618B2
公开(公告)日：2009-12-22
申请号：US11250118
申请日：2005-10-12
申请人： Xi-Wei Lin , Gwo-Chung Tai
发明人： Xi-Wei Lin , Gwo-Chung Tai
IPC分类号： H01L21/00
CPC分类号： H01L21/823462 , H01L21/82345 , H01L21/823456
摘要： The present invention includes a technique for making a dual voltage integrated circuit device. A gate dielectric layer is formed on a semiconductor substrate and a gate material layer is formed on the dielectric layer. A first region of the gate material layer is doped to a first nonzero level and a second region of the gate material level is doped to a second nonzero level greater than the first level. A first field effect transistor is defined that has a first gate formed from the first region. Also, a second field effect transistor is defined that has a second gate formed from the second region. The first transistor is operable at a gate threshold voltage greater than the second transistor in accordance with a difference between the first level and the second level.

68. 发明申请

US20090313595A1 STRESS-MANAGED REVISION OF INTEGRATED CIRCUIT LAYOUTS 有权
标题翻译：集成电路的应力管理修订
公开(公告)号：US20090313595A1
公开(公告)日：2009-12-17
申请号：US12546959
申请日：2009-08-25
申请人： Victor Moroz , Dipankar Pramanik , Xi-Wei Lin
发明人： Victor Moroz , Dipankar Pramanik , Xi-Wei Lin
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L21/823807
摘要： Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features can include dummy diffusion regions added to relax stress, and dummy trenches added either to relax or enhance stress. A trench can relax stress by filling it with a stress-neutral material or a tensile strained material. A trench can increase stress by filling it with a compressive strained material. Preferably dummy diffusion regions and stress relaxation trenches are disposed longitudinally to at least the channel regions of N-channel transistors, and transversely to at least the channel regions of both N-channel and P-channel transistors. Preferably stress enhancement trenches are disposed longitudinally to at least the channel regions of P-channel transistors.
摘要翻译：大致描述了改进集成电路布局和制造工艺的方法和系统，以便更好地解决应力影响。为了改善均匀性或放松已知的不良应力或引入已知的所需应力，可将虚拟特征添加到布局中。虚拟特征可以包括添加以放松应力的虚拟扩散区域，并且添加虚拟沟槽以放松或增强应力。沟槽可以通过用应力中性材料或拉伸应变材料填充来缓解应力。沟槽可以通过用压缩应变材料填充来增加应力。优选地，虚拟扩散区域和应力松弛沟槽纵向设置在N沟道晶体管的至少沟道区域上，并横向于N沟道和P沟道晶体管的至少沟道区域。优选地，应力增强沟槽纵向设置在至少P沟道晶体管的沟道区域上。

69. 发明授权

US07600207B2 Stress-managed revision of integrated circuit layouts 有权
标题翻译：集成电路布局的压力管理修订
公开(公告)号：US07600207B2
公开(公告)日：2009-10-06
申请号：US11363889
申请日：2006-02-27
申请人： Victor Moroz , Dipankar Pramanik , Xi-Wei Lin
发明人： Victor Moroz , Dipankar Pramanik , Xi-Wei Lin
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L21/823807
摘要： Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features can include dummy diffusion regions added to relax stress, and dummy trenches added either to relax or enhance stress. A trench can relax stress by filling it with a stress-neutral material or a tensile strained material. A trench can increase stress by filling it with a compressive strained material. Preferably dummy diffusion regions and stress relaxation trenches are disposed longitudinally to at least the channel regions of N-channel transistors, and transversely to at least the channel regions of both N-channel and P-channel transistors. Preferably stress enhancement trenches are disposed longitudinally to at least the channel regions of P-channel transistors.
摘要翻译：大致描述了改进集成电路布局和制造工艺的方法和系统，以便更好地解决应力影响。为了改善均匀性或放松已知的不良应力或引入已知的所需应力，可将虚拟特征添加到布局中。虚拟特征可以包括添加以放松应力的虚拟扩散区域，并且添加虚拟沟槽以放松或增强应力。沟槽可以通过用应力中性材料或拉伸应变材料填充来缓解应力。沟槽可以通过用压缩应变材料填充来增加应力。优选地，虚拟扩散区域和应力松弛沟槽纵向设置在N沟道晶体管的至少沟道区域上，并横向于N沟道和P沟道晶体管的至少沟道区域。优选地，应力增强沟槽纵向设置在至少P沟道晶体管的沟道区域上。

70. 发明申请

US20090083688A1 METHOD AND APPARATUS FOR GENERATING A LAYOUT FOR A TRANSISTOR 有权
标题翻译：用于生成晶体管布局的方法和装置
公开(公告)号：US20090083688A1
公开(公告)日：2009-03-26
申请号：US11860775
申请日：2007-09-25
申请人： Victor Moroz , Xi-Wei Lin , Mark Rubin
发明人： Victor Moroz , Xi-Wei Lin , Mark Rubin
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A system that generates a layout for a transistor is presented. During operation, the system receives a transistor library which includes operating characteristics of fabricated transistors correlated to transistor gate shapes. The system also receives one or more desired operating characteristics for the transistor. Next, the system determines a transistor gate shape for the transistor based on the transistor library so that a fabricated transistor with the transistor gate shape substantially achieves the one or more desired operating characteristics. The system then generates the layout for the transistor which includes the transistor gate shape.
摘要翻译：提出了一种产生晶体管布局的系统。在操作期间，系统接收晶体管库，其包括与晶体管栅极形状相关的制造晶体管的工作特性。该系统还接收晶体管的一个或多个期望的工作特性。接下来，系统基于晶体管库确定用于晶体管的晶体管栅极形状，使得具有晶体管栅极形状的制造晶体管基本上实现一个或多个期望的工作特性。然后，系统产生包括晶体管栅极形状的晶体管的布局。

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