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61. 发明授权

US10439024B2 Integrated circuit with triple guard wall pocket isolation 有权
公开(公告)号：US10439024B2
公开(公告)日：2019-10-08
申请号：US15180592
申请日：2016-06-13
申请人： Texas Instruments Incorporated , Texas Instruments Deutschland GmbH
发明人： Karim-Thomas Taghizadeh Kaschani , Antonio Gallerano
IPC分类号： H01L27/02 , H01L29/06
摘要： A semiconductor device includes a substrate having a semiconductor surface doped a second dopant type with a buried layer (BL) doped a first dopant type. First, second and third well regions doped the second dopant type are on top of the BL. Second doped regions doped the first dopant type on top of and contacting the BL arraigned as a first well ring and second well ring are around the first and third well regions respectively. At least one high-injection component including the first well region is surrounded by the first well ring. At least one component including the third well region is surrounded by the second well ring. An npn or pnp guard wall pocket including a wall of the first and second well rings, and the second well region is between the high-injection component and the component.

62. 发明申请

US20180231424A1 DEVICE AND METHOD FOR ON-CHIP MECHANICAL STRESS SENSING 审中-公开
公开(公告)号：US20180231424A1
公开(公告)日：2018-08-16
申请号：US15649934
申请日：2017-07-14
申请人： Texas Instruments Incorporated , Texas Instruments Deutschland, GMBH
发明人： Umidjon Nurmetov , Ralf Peter Brederlow , Baher Haroun
IPC分类号： G01L1/22 , H01L27/06 , G01L1/16 , H01L29/84 , G01L5/16 , H01L27/22 , G01L25/00
CPC分类号： G01L1/2293 , G01L1/162 , G01L1/2281 , G01L5/162 , G01L25/006 , H01L22/34 , H01L27/0647 , H01L27/0802 , H01L27/22 , H01L29/84 , H01L29/8605
摘要： An integrated circuit (IC) chip includes a substrate of a piezo-electric material having a first resistivity coefficient associated with a first direction that is longitudinal to a first crystal axis and a second resistivity coefficient associated with a second direction that is transverse to the first crystal axis. The first and second resistivity coefficients have opposite signs. The IC chip also includes a first stress sensing element formed in the substrate and coupled to pass a first current therethrough. The first stress sensing element includes a first resistor aligned such that the major direction of current flow through the first resistor is in the first direction and a second resistor coupled in series with the first resistor and aligned such that the major direction of current flow through the second resistor is in the second direction. A ratio of the resistance of the second resistor to the resistance of the first resistor is equal to a value α, where α is equal to the ratio of the first resistivity coefficient to the second resistivity coefficient.

63. 发明申请

US20180183266A1 METHODS AND APPARATUS FOR ANTENNA SIGNAL LIMITER FOR RADIO FREQUENCY IDENTIFICATION TRANSPONDER 审中-公开
公开(公告)号：US20180183266A1
公开(公告)日：2018-06-28
申请号：US15392234
申请日：2016-12-28
申请人： TEXAS INSTRUMENTS DEUTSCHLAND GMBH
发明人： Ernst Georg Muellner
IPC分类号： H02J50/12
CPC分类号： H02J50/12 , G06K19/0712 , G06K19/0715
摘要： In described examples, an apparatus includes: at least one resonant circuit for receiving a radio frequency signal; a rectifier coupled to the resonant circuit to output a first rectified signal with a constant level portion and a portion matching a first portion of the radio frequency signal, and to output a second rectified signal having a constant level portion and a portion that matches a second portion of the radio frequency signal; a first limiter circuit to limit a voltage of the first rectified signal to a predetermined maximum voltage level; a second limiter circuit to limit the voltage of the second rectified signal to the predetermined maximum voltage level; a third limiter circuit to limit a voltage of the first rectified signal to a predetermined minimum voltage level; and a fourth limiter circuit to limit the voltage of the second rectified signal to the predetermined minimum voltage level.

64. 发明申请

US20180152099A1 Switched Converter Control Using Adaptive Load Current Sensing and Feedforward Technique 审中-公开
公开(公告)号：US20180152099A1
公开(公告)日：2018-05-31
申请号：US15591107
申请日：2017-05-10
申请人： Texas Instruments Deutschland GMBH , Texas Instruments Incorporated
发明人： Filip Savic , Giacomo Calabrese , Giovanni Frattini
IPC分类号： H02M3/04 , H02M1/08 , H02M1/14
CPC分类号： H02M3/156 , H02M2001/0009 , H02M2001/0019
摘要： A switched voltage converter may be controlled with load current feedforward control loop in addition to an output voltage feedback loop. The converter includes a first switch device that is controlled to open and close at a selected switching rate with a selected duty cycle. The first switch device is coupled in series with an inductor and conducts current through the inductor while the first switch is closed. A second switch device conducts current from the inductor to an output capacitor and to load while the first switch is open to produce an output voltage and a resulting load current through the load. The load current is measured in a continuous manner and a load current feedforward control signal is generated that is representative of the load current. The switch rate and/or duty cycle of the first switch is adjusted in response to the load current feedforward control signal.

65. 发明授权

US09899466B2 Head resistance buffer 有权
公开(公告)号：US09899466B2
公开(公告)日：2018-02-20
申请号：US15335818
申请日：2016-10-27
申请人： Texas Instruments Deutschland GMBH
发明人： Josef Muenz
IPC分类号： H01L27/02 , H01L49/02
CPC分类号： H01L28/20 , H01L27/0207 , H01L28/00
摘要： An integrated circuit with first and second resistors comprised of resistor bodies, resistor heads, and resistor buffer regions wherein the resistor buffer regions are disposed between the resistor body and the resistor heads. The width of the first and second resistors is different. The length of the first and second resistor buffer regions is different. The total head resistance which is equal to the resistor head resistance plus the resistor buffer region is equal for both the first and second resistors. A method is described for forming an integrated circuit with first and second resistors comprised of resistor bodies, resistor heads, and resistor buffer regions disposed between the resistor body and the resistor head wherein the width of the first and second resistors is different, wherein the length of the resistor buffer regions of the first and second resistors is different, and wherein the total head resistance which is equal to the resistor head resistance plus the resistor buffer region is equal for both the first and second resistors. A method is described for calculating the length of a resistor buffer region as a function of resistor width so that the resistance of the resistor head plus the resistor buffer region remains the same as resistor body width changes.

66. 发明申请

US20180019297A1 METHOD AND STRUCTURE FOR DUAL SHEET RESISTANCE TRIMMABLE THIN FILM RESISTORS AT SAME LEVEL 有权
公开(公告)号：US20180019297A1
公开(公告)日：2018-01-18
申请号：US15209696
申请日：2016-07-13
申请人： Texas Instruments Incorporated , TEXAS INSTRUMENTS DEUTSCHLAND GMBH
发明人： Christoph Andreas Othmar Dirnecker , Wolfgang Schwartz , Doug Weiser , Joel Martin Halbert , Joseph Anthony DeSantis , Karsten Jens Spinger
IPC分类号： H01L49/02 , H01L23/522 , H01L21/268 , H01L21/027 , H01L21/3213 , H01L21/3205 , H01L23/528 , H01L21/768
CPC分类号： H01L28/24 , H01L21/0273 , H01L21/268 , H01L21/32051 , H01L21/32139 , H01L21/76802 , H01L21/76877 , H01L23/5226 , H01L23/5228 , H01L23/528
摘要： An integrated circuit includes a higher sheet resistance resistor and a lower sheet resistance resistor, disposed in a same level of dielectric layers of the integrated circuit. The higher sheet resistor has a body region and head regions in a higher sheet resistance layer. The lower sheet resistor has a body region and head regions in a lower sheet resistance layer, which is thicker than the higher sheet layer. The higher sheet resistor has an upper head layer contacting the higher sheet layer at each head region of the higher sheet layer. Each upper head layer has a same composition and thickness as the lower sheet layer of the lower sheet resistor. The lower sheet resistor is free of head layers over the lower sheet resistance layer.

67. 发明授权

US09864420B2 Energy tracking circuit 有权
公开(公告)号：US09864420B2
公开(公告)日：2018-01-09
申请号：US14517257
申请日：2014-10-17
申请人： TEXAS INSTRUMENTS DEUTSCHLAND GMBH
发明人： Horst Diewald , Johann Zipperer , Peter Weber , Anton Brauchle
IPC分类号： G01R1/20 , G06F1/26 , G06F1/32
CPC分类号： G06F1/26 , G06F1/3212 , Y02B70/16 , Y02D10/174
摘要： A circuit, system, and method for tracking energy use in a electronic circuit. A circuit includes a DC-DC converter and a comparator. The DC-DC converter is configured to maintain a desired output voltage by switching energy to an energy storage device based on an output voltage of the energy storage device. The DC-DC converter includes an output driver configured to source current to the energy storage device. The comparator is coupled to the DC-DC converter. The comparator is configured to identify a drive state of the output driver, and to generate a signal indicative of amount of energy transferred from the DC-DC converter to a load circuit. The signal corresponds to the identified drive state.

68. 发明申请

US20170358570A1 INTEGRATED CIRCUIT WITH TRIPLE GUARD WALL POCKET ISOLATION 审中-公开
公开(公告)号：US20170358570A1
公开(公告)日：2017-12-14
申请号：US15180592
申请日：2016-06-13
申请人： Texas Instruments Incorporated , Texas Instruments Deutschland GmbH
发明人： KARIM-THOMAS TAGHIZADEH KASCHANI , ANTONIO GALLERANO
IPC分类号： H01L27/02 , H01L29/06
CPC分类号： H01L29/0623 , H01L27/0248 , H01L27/0255 , H01L27/0262 , H01L27/027 , H01L27/0285
摘要： A semiconductor device includes a substrate having a semiconductor surface doped a second dopant type with a buried layer (BL) doped a first dopant type. First, second and third well regions doped the second dopant type are on top of the BL. Second doped regions doped the first dopant type on top of and contacting the BL arraigned as a first well ring and second well ring are around the first and third well regions respectively. At least one high-injection component including the first well region is surrounded by the first well ring. At least one component including the third well region is surrounded by the second well ring. An npn or pnp guard wall pocket including a wall of the first and second well rings, and the second well region is between the high-injection component and the component.

69. 发明授权

US09817791B2 Low energy accelerator processor architecture with short parallel instruction word 有权
公开(公告)号：US09817791B2
公开(公告)日：2017-11-14
申请号：US14678939
申请日：2015-04-04
申请人： Texas Instruments Incorporated , Texas Instruments Deutschland, GMBH
发明人： Srinivas Lingam , Seok-Jun Lee , Johann Zipperer , Manish Goel
IPC分类号： G06F9/30 , G06F15/80 , G06F9/32 , G06F9/38
CPC分类号： G06F15/80 , G06F9/30014 , G06F9/30094 , G06F9/30145 , G06F9/325 , G06F9/3822 , G06F9/3853 , G06F9/3877
摘要： Methods and apparatus for a low energy accelerator processor architecture with short parallel instruction word. An integrated circuit includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory coupled to the system bus; and a low energy accelerator processor coupled to the system bus and configured to execute instruction words retrieved from a low energy accelerator code memory, the low energy accelerator processor having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to op-codes decoded from the retrieved instruction words, wherein the width of the instruction words is equal to the data width N. Additional methods and apparatus are disclosed.

70. 发明申请

US20170310216A1 DC-TO-DC CONVERTER 审中-公开
公开(公告)号：US20170310216A1
公开(公告)日：2017-10-26
申请号：US15135987
申请日：2016-04-22
申请人： Texas Instruments Deutschland GMBH
发明人： Neil Gibson , Michael Couleur , Antonio Priego , Stefan Herzer
IPC分类号： H02M3/158
CPC分类号： H02M3/1588 , H02M3/158 , H02M2001/0009 , H02M2001/0032 , Y02B70/1466 , Y02B70/16
摘要： A DC-to-DC voltage converter includes a converter input for receiving a DC voltage. A first switch is coupled between the input and a first node. A second switch is coupled between the first node and a ground. An inductor is coupled between the first node and a converter output. A capacitor is coupled between the converter output and ground. An output voltage synthesizer is coupled to the converter input and the converter output for synthesizing the voltage at the first node and for generating a control signal for at least one of the first switch and the second switch in response to the voltages at the converter input and the converter output.

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