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61. 发明授权

US07868361B2 Semiconductor device with both I/O and core components and method of fabricating same 有权
公开(公告)号：US07868361B2
公开(公告)日：2011-01-11
申请号：US11766425
申请日：2007-06-21
申请人： Chung Long Cheng , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang , Mong Song Liang
发明人： Chung Long Cheng , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang , Mong Song Liang
IPC分类号： H01L21/76
CPC分类号： H01L29/66477 , H01L21/823412 , H01L21/823418 , H01L21/823462 , H01L27/0629 , H01L27/088 , H01L27/0922 , H01L29/7848
摘要： A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.

62. 发明授权

US07833848B2 Method for removing hard masks on gates in semiconductor manufacturing process 有权
标题翻译：在半导体制造工艺中去除门上的硬掩模的方法
公开(公告)号：US07833848B2
公开(公告)日：2010-11-16
申请号：US11864415
申请日：2007-09-28
申请人： Hung Chih Tsai , Chih Chieh Chen , Sheng Chen Chung , Kong Beng Thei , Harry Chuang
发明人： Hung Chih Tsai , Chih Chieh Chen , Sheng Chen Chung , Kong Beng Thei , Harry Chuang
IPC分类号： H01L21/339 , H01L21/00 , H01L21/8238
CPC分类号： H01L21/82385 , H01L21/31144 , H01L21/823814 , H01L29/165 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A method for removing hard masks on gates in a semiconductor manufacturing process is conducted as follows. First of all, a first gate and a second gate with hard masks are formed on a semiconductor substrate, wherein the second gate is larger than the first gate. The first gate and second gate could be associated with silicon-germanium (SiGe) source and drain regions to form p-type transistors. Next, a photoresist layer is deposited, and an opening of the photoresist layer is formed on the hard mask of the second gate. Then, the photoresist layer on the first and second gates is removed completely by etching back. Because there is no photoresist residue, the hard masks on the first and second gates can be removed completely afterwards.
摘要翻译：如下进行半导体制造工序中的门上去除硬掩模的方法。首先，在半导体衬底上形成具有硬掩模的第一栅极和第二栅极，其中第二栅极大于第一栅极。第一栅极和第二栅极可以与硅 - 锗（SiGe）源极和漏极区域相关联以形成p型晶体管。接下来，沉积光致抗蚀剂层，并且在第二栅极的硬掩模上形成光致抗蚀剂层的开口。然后，通过蚀刻完全去除第一和第二栅极上的光致抗蚀剂层。因为没有光致抗蚀剂残留物，所以第一和第二栅极上的硬掩模可以被完全去除。

63. 发明授权

US07803674B2 Methods for fabricating SOI devices 有权
标题翻译：制造SOI器件的方法
公开(公告)号：US07803674B2
公开(公告)日：2010-09-28
申请号：US12468131
申请日：2009-05-19
申请人： Chung-Long Cheng , Kong-Beng Thei , Sheng-Chen Chung , Tzung-Chi Lee , Harry Chuang
发明人： Chung-Long Cheng , Kong-Beng Thei , Sheng-Chen Chung , Tzung-Chi Lee , Harry Chuang
IPC分类号： H01L21/84
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/4238 , H01L29/78636
摘要： Silicon on insulator (SOI) devices and methods for fabricating the same are provided. An exemplary embodiment of a SOI device comprises a substrate. A first insulating layer is formed over the substrate. A plurality of semiconductor islands is formed over the first insulating layer, wherein the semiconductor islands are isolated from each other. A second insulating layer is formed over the first insulating layer, protruding over the semiconductor islands and surrounding thereof. At least one recess is formed in a portion of the second insulating layer adjacent to a pair of the semiconductor islands. A first dielectric layer is formed on a portion of each of the semiconductor islands. A conductive layer is formed over the first dielectric layer and over the second insulating layer exposed by the recess. A pair of source/drain regions is oppositely formed in portions of each of the semiconductor islands not covered by the first dielectric layer and the conductive layer.
摘要翻译：提供绝缘体上硅（SOI）器件及其制造方法。 SOI器件的示例性实施例包括衬底。在衬底上形成第一绝缘层。在第一绝缘层上形成多个半导体岛，其中半导体岛彼此隔离。在第一绝缘层上形成第二绝缘层，突出在半岛上并围绕它们。在与一对半导体岛相邻的第二绝缘层的一部分中形成至少一个凹部。第一电介质层形成在每个半导体岛的一部分上。导电层形成在第一电介质层之上，并在由凹部露出的第二绝缘层之上。一对源极/漏极区域相对地形成在未被第一介电层和导电层覆盖的半导体岛的每一个的部分中。

64. 发明申请

US20100087056A1 METHOD FOR GATE HEIGHT CONTROL IN A GATE LAST PROCESS 有权
标题翻译：门窗高度控制方法
公开(公告)号：US20100087056A1
公开(公告)日：2010-04-08
申请号：US12489053
申请日：2009-06-22
申请人： Sheng-Chen CHUNG , Kong-Beng THEI , Harry CHUANG
发明人： Sheng-Chen CHUNG , Kong-Beng THEI , Harry CHUANG
IPC分类号： H01L21/28
CPC分类号： H01L29/4966 , H01L21/28088 , H01L29/51 , H01L29/513 , H01L29/66545 , H01L29/78
摘要： A method is provided for fabricating a semiconductor device that includes providing a semiconductor substrate, forming a transistor in the substrate, the transistor having a gate structure that includes a dummy gate structure, forming an inter-layer dielectric (ILD), performing a first chemical mechanical polishing (CMP) to expose a top surface of the dummy gate structure, removing a portion of the ILD such that a top surface of the ILD is at a distance below the top surface of the dummy gate structure, forming a material layer over the ILD and dummy gate structure, performing a second CMP on the material layer to expose the top surface of the dummy gate structure, removing the dummy gate structure thereby forming a trench, forming a metal layer to fill in the trench, and performing a third CMP that substantially stops at the top surface of the ILD.
摘要翻译：提供了一种用于制造半导体器件的方法，该半导体器件包括提供半导体衬底，在衬底中形成晶体管，晶体管具有包括虚拟栅极结构的栅极结构，形成层间电介质（ILD），执行第一化学机械抛光（CMP）以暴露伪栅极结构的顶表面，去除ILD的一部分，使得ILD的顶表面在虚拟栅极结构的顶表面下方的距离处，形成在 ILD和虚拟栅极结构，在材料层上执行第二CMP以暴露虚拟栅极结构的顶表面，去除伪栅极结构从而形成沟槽，形成金属层以填充沟槽，以及执行第三CMP 其基本上停留在ILD的顶表面。

65. 发明申请

US20100001332A1 INTEGRATING A CAPACITOR IN A METAL GATE LAST PROCESS 有权
标题翻译：在金属门最后过程中集成电容器
公开(公告)号：US20100001332A1
公开(公告)日：2010-01-07
申请号：US12256132
申请日：2008-10-22
申请人： Harry Chuang , Tzung-Chi Lee , Kong-Beng Thei , Sheng-Chen Chung , Mong-Song Liang
发明人： Harry Chuang , Tzung-Chi Lee , Kong-Beng Thei , Sheng-Chen Chung , Mong-Song Liang
IPC分类号： H01L29/92 , H01L21/34
CPC分类号： H01L27/0629 , H01L27/11 , H01L29/94
摘要： A semiconductor device is provided which includes a semiconductor substrate having a first region and a second region, transistors having metal gates formed in the first region, and at least one capacitor formed in the second region. The capacitor includes a top electrode having at least one stopping structure formed in the top electrode, the at least one stopping structure being of a different material from the top electrode, a bottom electrode, and a dielectric layer interposed between the top electrode and the bottom electrode.
摘要翻译：提供一种半导体器件，其包括具有第一区域和第二区域的半导体衬底，在第一区域中形成有金属栅极的晶体管，以及形成在第二区域中的至少一个电容器。所述电容器包括顶电极，所述顶电极具有形成在所述顶电极中的至少一个止动结构，所述至少一个止动结构与所述顶电极，底电极和介于所述顶电极和所述底电极之间的电介质层具有不同的材料电极。

66. 发明申请

US20080003734A1 Selective formation of stress memorization layer 失效
标题翻译：选择性形成应力记忆层
公开(公告)号：US20080003734A1
公开(公告)日：2008-01-03
申请号：US11520377
申请日：2006-09-13
申请人： Harry Chuang , Mong-Song Liang , Kong-Beng Thei , Jung-Hui Kao , Chung Long Cheng , Sheng-Chen Chung , Wen-Huei Guo
发明人： Harry Chuang , Mong-Song Liang , Kong-Beng Thei , Jung-Hui Kao , Chung Long Cheng , Sheng-Chen Chung , Wen-Huei Guo
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823864 , H01L21/823878 , H01L21/84 , H01L27/0629 , H01L27/1203 , H01L29/7843
摘要： A method of forming a semiconductor structure includes providing a semiconductor substrate comprising a first region and a second region, forming a first PMOS device in the first region wherein a first gate electrode of the first PMOS device has a first p-type impurity concentration, forming a stress memorization layer over the first PMOS device, reducing the stress memorization layer in the first region, performing an annealing after the step of reducing the stress memorization layer in the first region, and removing the stress memorization layer. The same stress memorization layer is not reduced in a region having an NMOS device. The same stress memorization layer may not be reduced in a region including a second PMOS device.
摘要翻译：一种形成半导体结构的方法包括提供包括第一区域和第二区域的半导体衬底，在第一区域中形成第一PMOS器件，其中第一PMOS器件的第一栅电极具有第一p型杂质浓度，形成在第一PMOS器件上方的应力记忆层，减小第一区域中的应力存储层，在减少第一区域中的应力存储层的步骤之后进行退火，以及去除应力存储层。在具有NMOS器件的区域中，相同的应力记忆层没有减小。在包括第二PMOS器件的区域中，相同的应力记忆层可能不会减小。

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