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61. 发明申请

US20100273303A1 Memory Arrays and Methods of Fabricating Memory Arrays 有权
标题翻译：内存数组和内存数组制作方法
公开(公告)号：US20100273303A1
公开(公告)日：2010-10-28
申请号：US12828915
申请日：2010-07-01
申请人： Gordon A. Haller , Sanh D. Tang
发明人： Gordon A. Haller , Sanh D. Tang
IPC分类号： H01L21/8242
CPC分类号： H01L29/66621 , G11C11/405 , H01L27/10823 , H01L27/10844 , H01L27/10876 , H01L27/10891
摘要： A memory array includes a plurality of memory cells formed on a semiconductor substrate. Individual of the memory cells include first and second field effect transistors respectively comprising a gate, a channel region, and a pair of source/drain regions. The gates of the first and second field effect transistors are hard wired together. A conductive data line is hard wired to two of the source/drain regions. A charge storage device is hard wired to at least one of the source/drain regions other than the two. Other aspects and implementations are contemplated, including methods of fabricating memory arrays.
摘要翻译：存储器阵列包括形成在半导体衬底上的多个存储单元。存储单元的个体包括分别包括栅极，沟道区和一对源极/漏极区的第一和第二场效应晶体管。第一和第二场效应晶体管的栅极被硬连线在一起。导电数据线硬连接到两个源极/漏极区域。电荷存储装置硬连接到除二者之外的源极/漏极区域中的至少一个。考虑了其他方面和实现方式，包括制造存储器阵列的方法。

62. 发明授权

US07745319B2 System and method for fabricating a fin field effect transistor 有权
标题翻译：用于制造鳍式场效应晶体管的系统和方法
公开(公告)号：US07745319B2
公开(公告)日：2010-06-29
申请号：US11508047
申请日：2006-08-22
申请人： Sanh D. Tang , Gordon Haller
发明人： Sanh D. Tang , Gordon Haller
IPC分类号： H01L21/428
CPC分类号： H01L29/785 , H01L21/3086 , H01L27/0886 , H01L29/0649 , H01L29/66795 , H01L29/7851
摘要： There is provided a system and method for fabricating a fin field effect transistor. More specifically, in one embodiment, there is provided a method comprising depositing a layer of nitride on a substrate, applying a photolithographic mask on the layer of nitride to define a location of a wall, etching the layer of nitride to create the wall, removing the photolithographic mask, depositing a spacer layer adjacent to the wall, etching the spacer layer to create a spacer adjacent to the wall, wherein the spacer and the wall cover a first portion of the substrate, and etching a second portion of the substrate not covered by the spacer to create a trench.
摘要翻译：提供了制造鳍式场效应晶体管的系统和方法。更具体地，在一个实施例中，提供了一种方法，包括在衬底上沉积氮化物层，在氮化层上施加光刻掩模以限定壁的位置，蚀刻氮化物层以产生壁，去除光刻掩模，在壁附近沉积间隔层，蚀刻间隔层以产生邻近壁的隔离物，其中间隔物和壁覆盖基底的第一部分，并蚀刻未被覆盖的基底的第二部分通过间隔件形成沟槽。

63. 发明授权

US07687857B2 Integrated circuits 有权
标题翻译：集成电路
公开(公告)号：US07687857B2
公开(公告)日：2010-03-30
申请号：US11957013
申请日：2007-12-14
申请人： Sanh D. Tang , Gordon Haller
发明人： Sanh D. Tang , Gordon Haller
IPC分类号： H01L29/786
CPC分类号： H01L29/0653 , H01L21/0237 , H01L21/02532 , H01L21/02595 , H01L21/0262 , H01L21/823412 , H01L21/823418 , H01L21/823481 , H01L21/84 , H01L27/1203
摘要： Integrated circuits and methods of forming field effect transistors are disclosed. In one aspect, an integrated circuit includes a semiconductor substrate comprising bulk semiconductive material. Electrically insulative material is received within the bulk semiconductive material. Semiconductor material is formed on the insulative material. A field effect transistor is included and comprises a gate, a channel region, and a pair of source/drain regions. In one implementation, one of the source/drain regions is formed in the semiconductor material, and the other of the source/drain regions is formed in the bulk semiconductive material. In one implementation, the electrically insulative material extends from beneath one of the source/drain regions to beneath only a portion of the channel region. Other aspects and implementations, including methodical aspects, are disclosed.
摘要翻译：公开了形成场效应晶体管的集成电路和方法。在一个方面，集成电路包括包括本体半导体材料的半导体衬底。电绝缘材料容纳在本体半导体材料内。在绝缘材料上形成半导体材料。包括场效应晶体管，并包括栅极，沟道区和一对源极/漏极区。在一个实施方案中，源/漏区中的一个形成在半导体材料中，并且源/漏区中的另一个在体半导体材料中形成。在一个实施方案中，电绝缘材料从源极/漏极区域之一延伸到仅沟道区域的仅一部分的下方。公开了其他方面和实施方式，包括方法方面。

64. 发明授权

US07659560B2 Transistor structures 有权
标题翻译：晶体管结构
公开(公告)号：US07659560B2
公开(公告)日：2010-02-09
申请号：US11716433
申请日：2007-03-08
申请人： Sanh D. Tang , Gordon A. Haller , Prashant Raghu , Ravi Iyer
发明人： Sanh D. Tang , Gordon A. Haller , Prashant Raghu , Ravi Iyer
IPC分类号： H01L21/8238
CPC分类号： H01L29/78696 , H01L29/42392 , H01L29/66787
摘要： A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within the opening, a metal layer over the dielectric layer within the opening, and a fill layer over the metal layer within the opening. The metal layer/fill layer combination exhibits less intrinsic less than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer. The inventions apply at least to 3-D transistor structures.
摘要翻译：晶体管栅极形成方法包括在线路开口内形成金属层，并在金属层的开口内形成填充层。填充层相对于金属层基本上可选择性地蚀刻。晶体管结构包括线路开口，开口内的电介质层，开口内的电介质层上的金属层，以及开口内的金属层上的填充层。如果填充层被金属层的增加的厚度代替，则金属层/填充层组合的内在特性小于否则会存在。本发明至少应用于三维晶体管结构。

65. 发明授权

US07488651B2 Method of making vertical transistor structures having vertical-surrounding-gates with self-aligned features 有权
标题翻译：制造垂直晶体管结构的方法，其具有具有自对准特征的垂直环形栅极
公开(公告)号：US07488651B2
公开(公告)日：2009-02-10
申请号：US11495473
申请日：2006-07-28
申请人： Sanh D. Tang , Grant S. Huglin
发明人： Sanh D. Tang , Grant S. Huglin
IPC分类号： H01L21/336
CPC分类号： H01L29/42392 , H01L29/66666 , H01L29/7827
摘要： The present inventions include a vertical transistor formed by defining a channel length of the vertical-surrounding-gate field effect transistor with self-aligning features. The method provides process steps to define the transistor channel length and recess silicon pillars used to form the vertical-surrounding gate field effect transistor structure for use in the manufacture of semiconductor devices.
摘要翻译：本发明包括通过定义具有自对准特征的垂直环绕栅极场效应晶体管的沟道长度而形成的垂直晶体管。该方法提供了定义晶体管沟道长度的工艺步骤和用于形成用于制造半导体器件的垂直周围栅极场效应晶体管结构的凹槽硅柱。

66. 发明申请

US20080311719A1 Method Of Forming A Field Effect Transistor 有权
标题翻译：形成场效应晶体管的方法
公开(公告)号：US20080311719A1
公开(公告)日：2008-12-18
申请号：US12191119
申请日：2008-08-13
申请人： Sanh D. Tang , Michael P. Violette , Robert Burke
发明人： Sanh D. Tang , Michael P. Violette , Robert Burke
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , G06K19/0723 , G06K19/0726 , G06K19/07771 , H01L21/76229 , H01L21/76232 , H01L21/76264 , H01L21/823418 , H01L21/823437 , H01L21/823481 , H01L21/823814 , H01L21/823828 , H01L29/1083 , H01L29/41783 , H01L29/66545 , H01L29/66583 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening has a base comprising semiconductive material. After the etching, insulative material is formed within the opening over the semiconductive material base. The insulative material less than completely fills the opening and has a substantially uniform thickness across the opening. Semiconductive source/drain material is formed within the opening over the insulative material within the opening. A transistor gate is provided operatively proximate the semiconductive source/drain material. Other aspects and implementations are contemplated.
摘要翻译：在一个实施方案中，形成场效应晶体管的方法包括蚀刻半导体衬底的源/漏区的开口。开口具有包括半导体材料的基底。在蚀刻之后，在半导体材料基体的开口内形成绝缘材料。绝缘材料小于完全填充开口并且在开口上具有基本均匀的厚度。在开口内的绝缘材料的开口内形成半导电源极/漏极材料。半导体源极/漏极材料可操作地提供晶体管栅极。考虑了其他方面和实现。

67. 发明授权

US07384849B2 Methods of forming recessed access devices associated with semiconductor constructions 有权
标题翻译：形成与半导体结构相关联的凹陷接入设备的方法
公开(公告)号：US07384849B2
公开(公告)日：2008-06-10
申请号：US11090529
申请日：2005-03-25
申请人： Kunal R. Parekh , Suraj Mathew , Jigish D. Trivedi , John K. Zahurak , Sanh D. Tang
发明人： Kunal R. Parekh , Suraj Mathew , Jigish D. Trivedi , John K. Zahurak , Sanh D. Tang
IPC分类号： H01L21/336
CPC分类号： H01L27/10876 , H01L27/10823
摘要： The invention includes methods of forming recessed access devices. A substrate is provided to have recessed access device trenches therein. A pair of the recessed access device trenches are adjacent one another. Electrically conductive material is formed within the recessed access device trenches, and source/drain regions are formed proximate the electrically conductive material. The electrically conductive material and source/drain regions together are incorporated into a pair of adjacent recessed access devices. After the recessed access device trenches are formed within the substrate, an isolation region trench is formed between the adjacent recessed access devices and filled with electrically insulative material to form a trenched isolation region.
摘要翻译：本发明包括形成凹入进入装置的方法。提供基板以在其中具有凹入的接入装置沟槽。一对凹进的接入设备沟槽彼此相邻。导电材料形成在凹进的存取装置沟槽内，源极/漏极区域靠近导电材料形成。导电材料和源极/漏极区域一起被并入一对相邻的凹进入器件中。在凹陷的访问设备沟槽形成在衬底内之后，在相邻的凹进的访问设备之间形成隔离区沟槽，并且填充有电绝缘材料以形成沟槽隔离区域。

68. 发明申请

US20080050885A1 System and method for fabricating a fin field effect transistor 有权
标题翻译：用于制造鳍式场效应晶体管的系统和方法
公开(公告)号：US20080050885A1
公开(公告)日：2008-02-28
申请号：US11508047
申请日：2006-08-22
申请人： Sanh D. Tang , Gordon Haller
发明人： Sanh D. Tang , Gordon Haller
IPC分类号： H01L21/76
CPC分类号： H01L29/785 , H01L21/3086 , H01L27/0886 , H01L29/0649 , H01L29/66795 , H01L29/7851
摘要： There is provided a system and method for fabricating a fin field effect transistor. More specifically, in one embodiment, there is provided a method comprising depositing a layer of nitride on a substrate, applying a photolithographic mask on the layer of nitride to define a location of a wall, etching the layer of nitride to create the wall, removing the photolithographic mask, depositing a spacer layer adjacent to the wall, etching the spacer layer to create a spacer adjacent to the wall, wherein the spacer and the wall cover a first portion of the substrate, and etching a second portion of the substrate not covered by the spacer to create a trench.
摘要翻译：提供了制造鳍式场效应晶体管的系统和方法。更具体地，在一个实施例中，提供了一种方法，包括在衬底上沉积氮化物层，在氮化层上施加光刻掩模以限定壁的位置，蚀刻氮化物层以产生壁，去除光刻掩模，在壁附近沉积间隔层，蚀刻间隔层以产生邻近壁的隔离物，其中间隔物和壁覆盖基底的第一部分，并蚀刻未被覆盖的基底的第二部分通过间隔件形成沟槽。

69. 发明授权

US07332811B2 Integrated circuit interconnect 有权
标题翻译：集成电路互连
公开(公告)号：US07332811B2
公开(公告)日：2008-02-19
申请号：US11427746
申请日：2006-06-29
申请人： Martin C. Roberts , Sanh D. Tang
发明人： Martin C. Roberts , Sanh D. Tang
IPC分类号： H01L23/40 , H01L23/48 , H01L23/52
CPC分类号： H01L27/10882 , H01L21/76838 , H01L23/485 , H01L27/11 , H01L2924/0002 , H01L2924/00
摘要： A method for forming an electrical interconnect overlying a buried contact region of a substrate is characterized by a deposition of a first polycrystalline silicon layer and the patterning and etching of same to form a via. The via is formed in the first polycrystalline silicon layer to expose the substrate and a second polycrystalline silicon layer is formed in the via to contact the substrate. Portions of the second polycrystalline silicon layer overlying the first polycrystalline silicon layer are removed eliminating any horizontal interface between the two polycrystalline silicon layers. The first polycrystalline silicon layer remaining after the etch is then patterned to form an electrical interconnect.
摘要翻译：用于形成覆盖衬底的掩埋接触区域的电互连的方法的特征在于沉积第一多晶硅层及其图案化和蚀刻以形成通孔。通孔形成在第一多晶硅层中以露出衬底，并且在通孔中形成第二多晶硅层以接触衬底。去除覆盖在第一多晶硅层上的第二多晶硅层的部分，消除了两个多晶硅层之间的任何水平界面。然后在蚀刻之后残留的第一多晶硅层被图案化以形成电互连。

70. 发明授权

US07282433B2 Interconnect structures with bond-pads and methods of forming bump sites on bond-pads 有权
标题翻译：具有接合焊盘的互连结构和在焊盘上形成凸点位置的方法
公开(公告)号：US07282433B2
公开(公告)日：2007-10-16
申请号：US11032975
申请日：2005-01-10
申请人： Sanh D. Tang , Mark E. Tuttle , Keith R. Cook
发明人： Sanh D. Tang , Mark E. Tuttle , Keith R. Cook
IPC分类号： H01L21/44
CPC分类号： H01L24/11 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/0401 , H01L2224/04073 , H01L2224/05018 , H01L2224/05026 , H01L2224/05082 , H01L2224/05181 , H01L2224/05187 , H01L2224/05558 , H01L2224/05559 , H01L2224/05571 , H01L2224/05624 , H01L2224/13099 , H01L2224/131 , H01L2924/0001 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/0496 , H01L2924/05042 , H01L2924/14 , H01L2924/04941 , H01L2224/05552
摘要： Microelectronic workpieces that have bump sites over bond-pads and methods of fabricating such bump sites. One embodiment of such a workpiece, for example, includes a substrate having a plurality of microelectronic dies comprising integrated circuitry and bond-pads, such as copper bond-pads, electrically coupled to the integrated circuitry. The workpiece further includes (a) a dielectric structure having a plurality of openings with sidewalls projecting from corresponding bond-pads, and (b) a plurality of caps over corresponding bond-pads. The individual caps can include a discrete portion of a barrier layer attached to the bond-pads and the sidewalls of the openings, and a discrete portion of a cap layer on the barrier layer. The caps are electrically isolated from each other and self-aligned with corresponding bond-pads without forming a mask layer over the cap layer.
摘要翻译：在焊盘上具有凸起部位的微电子工件以及制造这种凹凸点的方法。例如，这种工件的一个实施例包括具有多个微电子管芯的衬底，该多个微电子管芯包括集成电路和电耦合到集成电路的接合焊盘，例如铜接合焊盘。工件还包括（a）具有多个开口的电介质结构，其中侧壁从相应的接合焊盘突出，以及（b）在相应的接合焊盘上的多个盖。各个盖可以包括附着到接合焊盘和开口的侧壁的阻挡层的分立部分，以及阻挡层上的覆盖层的离散部分。盖子彼此电隔离并且与相应的接合焊盘自对准，而不在盖层上形成掩模层。

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