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1. 发明申请

US20080311719A1 Method Of Forming A Field Effect Transistor 有权
标题翻译：形成场效应晶体管的方法
公开(公告)号：US20080311719A1
公开(公告)日：2008-12-18
申请号：US12191119
申请日：2008-08-13
申请人： Sanh D. Tang , Michael P. Violette , Robert Burke
发明人： Sanh D. Tang , Michael P. Violette , Robert Burke
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , G06K19/0723 , G06K19/0726 , G06K19/07771 , H01L21/76229 , H01L21/76232 , H01L21/76264 , H01L21/823418 , H01L21/823437 , H01L21/823481 , H01L21/823814 , H01L21/823828 , H01L29/1083 , H01L29/41783 , H01L29/66545 , H01L29/66583 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening has a base comprising semiconductive material. After the etching, insulative material is formed within the opening over the semiconductive material base. The insulative material less than completely fills the opening and has a substantially uniform thickness across the opening. Semiconductive source/drain material is formed within the opening over the insulative material within the opening. A transistor gate is provided operatively proximate the semiconductive source/drain material. Other aspects and implementations are contemplated.
摘要翻译：在一个实施方案中，形成场效应晶体管的方法包括蚀刻半导体衬底的源/漏区的开口。开口具有包括半导体材料的基底。在蚀刻之后，在半导体材料基体的开口内形成绝缘材料。绝缘材料小于完全填充开口并且在开口上具有基本均匀的厚度。在开口内的绝缘材料的开口内形成半导电源极/漏极材料。半导体源极/漏极材料可操作地提供晶体管栅极。考虑了其他方面和实现。

2. 发明授权

US08440515B2 Method of forming a field effect transistor 有权
标题翻译：形成场效应晶体管的方法
公开(公告)号：US08440515B2
公开(公告)日：2013-05-14
申请号：US12191119
申请日：2008-08-13
申请人： Sanh D. Tang , Michael P. Violette , Robert Burke
发明人： Sanh D. Tang , Michael P. Violette , Robert Burke
IPC分类号： H01L21/00
CPC分类号： H01L29/7833 , G06K19/0723 , G06K19/0726 , G06K19/07771 , H01L21/76229 , H01L21/76232 , H01L21/76264 , H01L21/823418 , H01L21/823437 , H01L21/823481 , H01L21/823814 , H01L21/823828 , H01L29/1083 , H01L29/41783 , H01L29/66545 , H01L29/66583 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening has a base comprising semiconductive material. After the etching, insulative material is formed within the opening over the semiconductive material base. The insulative material less than completely fills the opening and has a substantially uniform thickness across the opening. Semiconductive source/drain material is formed within the opening over the insulative material within the opening. A transistor gate is provided operatively proximate the semiconductive source/drain material. Other aspects and implementations are contemplated.
摘要翻译：在一个实施方案中，形成场效应晶体管的方法包括蚀刻半导体衬底的源/漏区的开口。开口具有包括半导体材料的基底。在蚀刻之后，在半导体材料基体的开口内形成绝缘材料。绝缘材料小于完全填充开口并且在开口上具有基本均匀的厚度。在开口内的绝缘材料的开口内形成半导电源极/漏极材料。半导体源极/漏极材料可操作地提供晶体管栅极。考虑了其他方面和实现。

3. 发明授权

US07470576B2 Methods of forming field effect transistor gate lines 有权
标题翻译：形成场效应晶体管栅极线的方法
公开(公告)号：US07470576B2
公开(公告)日：2008-12-30
申请号：US11000786
申请日：2004-11-30
申请人： Sanh D. Tang , Michael P. Violette , Robert Burke
发明人： Sanh D. Tang , Michael P. Violette , Robert Burke
IPC分类号： H01L21/8234
CPC分类号： H01L29/7833 , G06K19/0723 , G06K19/0726 , G06K19/07771 , H01L21/76229 , H01L21/76232 , H01L21/76264 , H01L21/823418 , H01L21/823437 , H01L21/823481 , H01L21/823814 , H01L21/823828 , H01L29/1083 , H01L29/41783 , H01L29/66545 , H01L29/66583 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening has a base comprising semiconductive material. After the etching, insulative material is formed within the opening over the semiconductive material base. The insulative material less than completely fills the opening and has a substantially uniform thickness across the opening. Semiconductive source/drain material is formed within the opening over the insulative material within the opening. A transistor gate is provided operatively proximate the semiconductive source/drain material. Other aspects and implementations are contemplated.
摘要翻译：在一个实施方案中，形成场效应晶体管的方法包括蚀刻半导体衬底的源/漏区的开口。开口具有包括半导体材料的基底。在蚀刻之后，在半导体材料基体的开口内形成绝缘材料。绝缘材料小于完全填充开口并且在开口上具有基本均匀的厚度。在开口内的绝缘材料的开口内形成半导电源极/漏极材料。半导体源极/漏极材料可操作地提供晶体管栅极。考虑了其他方面和实现。

4. 发明授权

US07465616B2 Method of forming a field effect transistor 有权
标题翻译：形成场效应晶体管的方法
公开(公告)号：US07465616B2
公开(公告)日：2008-12-16
申请号：US11000809
申请日：2004-11-30
申请人： Sanh D. Tang , Michael P. Violette , Robert Burke
发明人： Sanh D. Tang , Michael P. Violette , Robert Burke
IPC分类号： H01L21/00
CPC分类号： H01L29/7833 , G06K19/0723 , G06K19/0726 , G06K19/07771 , H01L21/76229 , H01L21/76232 , H01L21/76264 , H01L21/823418 , H01L21/823437 , H01L21/823481 , H01L21/823814 , H01L21/823828 , H01L29/1083 , H01L29/41783 , H01L29/66545 , H01L29/66583 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening has a base comprising semiconductive material. After the etching, insulative material is formed within the opening over the semiconductive material base. The insulative material less than completely fills the opening and has a substantially uniform thickness across the opening. Semiconductive source/drain material is formed within the opening over the insulative material within the opening. A transistor gate is provided operatively proximate the semiconductive source/drain material. Other aspects and implementations are contemplated.
摘要翻译：在一个实施方案中，形成场效应晶体管的方法包括蚀刻半导体衬底的源/漏区的开口。开口具有包括半导体材料的基底。在蚀刻之后，在半导体材料基体的开口内形成绝缘材料。绝缘材料小于完全填充开口并且在开口上具有基本均匀的厚度。在开口内的绝缘材料的开口内形成半导电源极/漏极材料。半导体源极/漏极材料可操作地提供晶体管栅极。考虑了其他方面和实现。

5. 发明授权

US07071043B2 Methods of forming a field effect transistor having source/drain material over insulative material 失效
标题翻译：在绝缘材料上形成具有源极/漏极材料的场效应晶体管的方法
公开(公告)号：US07071043B2
公开(公告)日：2006-07-04
申请号：US10222326
申请日：2002-08-15
申请人： Sanh D. Tang , Michael P. Violette , Robert Burke
发明人： Sanh D. Tang , Michael P. Violette , Robert Burke
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , G06K19/0723 , G06K19/0726 , G06K19/07771 , H01L21/76229 , H01L21/76232 , H01L21/76264 , H01L21/823418 , H01L21/823437 , H01L21/823481 , H01L21/823814 , H01L21/823828 , H01L29/1083 , H01L29/41783 , H01L29/66545 , H01L29/66583 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening has a base comprising semiconductive material. After the etching, insulative material is formed within the opening over the semiconductive material base. The insulative material less than completely fills the opening and has a substantially uniform thickness across the opening. Semiconductive source/drain material is formed within the opening over the insulative material within the opening. A transistor gate is provided operatively proximate the semiconductive source/drain material. Other aspects and implementations are contemplated.
摘要翻译：在一个实施方案中，形成场效应晶体管的方法包括蚀刻半导体衬底的源/漏区的开口。开口具有包括半导体材料的基底。在蚀刻之后，在半导体材料基体的开口内形成绝缘材料。绝缘材料小于完全填充开口并且在开口上具有基本均匀的厚度。在开口内的绝缘材料的开口内形成半导电源极/漏极材料。半导体源极/漏极材料可操作地提供晶体管栅极。考虑了其他方面和实现。

6. 发明授权

US06936507B2 Method of forming field effect transistors 有权
标题翻译：形成场效应晶体管的方法
公开(公告)号：US06936507B2
公开(公告)日：2005-08-30
申请号：US11001145
申请日：2004-11-30
申请人： Sanh D. Tang , Michael P. Violette , Robert Burke
发明人： Sanh D. Tang , Michael P. Violette , Robert Burke
IPC分类号： G06K19/07 , H01L21/336 , H01L21/762 , H01L21/8234
CPC分类号： H01L29/7833 , G06K19/0723 , G06K19/0726 , G06K19/07771 , H01L21/76229 , H01L21/76232 , H01L21/76264 , H01L21/823418 , H01L21/823437 , H01L21/823481 , H01L21/823814 , H01L21/823828 , H01L29/1083 , H01L29/41783 , H01L29/66545 , H01L29/66583 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening has a base comprising semiconductive material. After the etching, insulative material is formed within the opening over the semiconductive material base. The insulative material less than completely fills the opening and has a substantially uniform thickness across the opening. Semiconductive source/drain material is formed within the opening over the insulative material within the opening. A transistor gate is provided operatively proximate the semiconductive source/drain material. Other aspects and implementations are contemplated.
摘要翻译：在一个实施方案中，形成场效应晶体管的方法包括蚀刻半导体衬底的源/漏区的开口。开口具有包括半导体材料的基底。在蚀刻之后，在半导体材料基体的开口内形成绝缘材料。绝缘材料小于完全填充开口并且在开口上具有基本均匀的厚度。在开口内的绝缘材料的开口内形成半导电源极/漏极材料。半导体源极/漏极材料可操作地提供晶体管栅极。考虑了其他方面和实现。

7. 发明授权

US07118950B2 Method of forming a field effect transistor 有权
公开(公告)号：US07118950B2
公开(公告)日：2006-10-10
申请号：US11000588
申请日：2004-11-30
申请人： Sanh D. Tang , Michael P. Violette , Robert Burke
发明人： Sanh D. Tang , Michael P. Violette , Robert Burke
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , G06K19/0723 , G06K19/0726 , G06K19/07771 , H01L21/76229 , H01L21/76232 , H01L21/76264 , H01L21/823418 , H01L21/823437 , H01L21/823481 , H01L21/823814 , H01L21/823828 , H01L29/1083 , H01L29/41783 , H01L29/66545 , H01L29/66583 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening has a base comprising semiconductive material. After the etching, insulative material is formed within the opening over the semiconductive material base. The insulative material less than completely fills the opening and has a substantially uniform thickness across the opening. Semiconductive source/drain material is formed within the opening over the insulative material within the opening. A transistor gate is provided operatively proximate the semiconductive source/drain material. Other aspects and implementations are contemplated.

8. 发明授权

US07166896B2 Cross diffusion barrier layer in polysilicon 有权
标题翻译：多晶硅中的交叉扩散阻挡层
公开(公告)号：US07166896B2
公开(公告)日：2007-01-23
申请号：US10228839
申请日：2002-08-26
申请人： Sanh D. Tang , Chih-Chen Cho , Robert Burke , Anuradha Iyengar , Eugene R. Gifford
发明人： Sanh D. Tang , Chih-Chen Cho , Robert Burke , Anuradha Iyengar , Eugene R. Gifford
IPC分类号： H01L27/11
CPC分类号： H01L27/11 , H01L21/823842 , H01L21/823871 , H01L27/1104 , H01L29/4941 , Y10S257/903 , Y10S438/927
摘要： A semiconductor device includes a cross diffusion barrier layer sandwiched between a gate layer and an electrode layer. The gate layer has a first gate portion of doped polysilicon of first conductivity type adjacent to a second gate portion doped polysilicon of second conductivity type. The cross diffusion barrier layer includes a combination of silicon and nitrogen. The cross diffusion barrier layer adequately prevents cross diffusion between the first and second gate portions while causing no substantial increase in the resistance of the gate layer.
摘要翻译：半导体器件包括夹在栅极层和电极层之间的交叉扩散阻挡层。栅极层具有与第二导电类型的掺杂多晶硅的第二栅极部分相邻的第一导电类型的掺杂多晶硅的第一栅极部分。交叉扩散阻挡层包括硅和氮的组合。交叉扩散阻挡层充分地防止了第一和第二栅极部分之间的交叉扩散，同时不会显着增加栅极层的电阻。

9. 发明授权

US07214613B2 Cross diffusion barrier layer in polysilicon 有权
公开(公告)号：US07214613B2
公开(公告)日：2007-05-08
申请号：US10931377
申请日：2004-08-31
申请人： Sanh D. Tang , Chih-Chen Cho , Robert Burke , Anuradha Iyengar , Eugene R. Gifford
发明人： Sanh D. Tang , Chih-Chen Cho , Robert Burke , Anuradha Iyengar , Eugene R. Gifford
IPC分类号： H01L21/321
CPC分类号： H01L27/11 , H01L21/823842 , H01L21/823871 , H01L27/1104 , H01L29/4941 , Y10S257/903 , Y10S438/927
摘要： A semiconductor device includes a cross diffusion barrier layer sandwiched between a gate layer and an electrode layer. The gate layer has a first gate portion of doped polysilicon of first conductivity type adjacent to a second gate portion doped polysilicon of second conductivity type. The cross diffusion barrier layer includes a combination of silicon and nitrogen. The cross diffusion barrier layer adequately prevents cross diffusion between the first and second gate portions while causing no substantial increase in the resistance of the gate layer.

10. 发明申请

US20130060720A1 ESTIMATING AND OPTIMIZING COST SAVINGS FOR LARGE SCALE DEPLOYMENTS USING LOAD PROFILE OPTIMIZATION 审中-公开
标题翻译：使用负载轮廓优化估算和优化大规模部署的成本节省
公开(公告)号：US20130060720A1
公开(公告)日：2013-03-07
申请号：US13465326
申请日：2012-05-07
申请人： Robert Burke
发明人： Robert Burke
IPC分类号： G06Q40/00
CPC分类号： G06Q10/063
摘要： A system, computer-implemented method, and a computer program product are provided for estimating and optimizing cost savings for large scale deployments using load profile optimization. Selections are received, via a user interface, of a primary load profile and multiple secondary load profiles. The primary load profile is input from a first external source and the multiple secondary load profiles are input from a second external source. The primary load profile is compared with the multiple secondary load profiles. The comparisons of the primary load profile and the multiple secondary load profiles are output via the user interface.
摘要翻译：提供了系统，计算机实现的方法和计算机程序产品，用于使用负载分布优化来估计和优化大规模部署的成本节省。通过用户界面接收到主负载配置文件和多个辅助负载配置文件的选择。从第一个外部源输入主负载曲线，并从第二个外部源输入多个次要负载曲线。将主负载曲线与多个次级负载曲线进行比较。通过用户界面输出主要负载配置文件和多个辅助负载配置文件的比较。

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