专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明申请

US20080237599A1 MEMORY CELL COMPRISING A CARBON NANOTUBE FABRIC ELEMENT AND A STEERING ELEMENT 有权
标题翻译：包含碳纳米管织物元件和转向元件的存储单元
公开(公告)号：US20080237599A1
公开(公告)日：2008-10-02
申请号：US11692148
申请日：2007-03-27
申请人： S. Brad Herner , Roy E. Scheuerlein
发明人： S. Brad Herner , Roy E. Scheuerlein
IPC分类号： H01L27/10 , H01L29/04
CPC分类号： H01L27/101 , B82Y10/00 , G11C13/025 , G11C2213/71 , G11C2213/72 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L27/2454 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/149
摘要： A rewritable nonvolatile memory cell is disclosed comprising a steering element in series with a carbon nanotube fabric. The steering element is preferably a diode, but may also be a transistor. The carbon nanotube fabric reversibly changes resistivity when subjected to an appropriate electrical pulse. The different resistivity states of the carbon nanotube fabric can be sensed, and can correspond to distinct data states of the memory cell. A first memory level of such memory cells can be monolithically formed above a substrate, a second memory level monolithically formed above the first, and so on, forming a highly dense monolithic three dimensional memory array of stacked memory levels.
摘要翻译：公开了一种可重写的非易失性存储单元，其包括与碳纳米管织物串联的转向元件。转向元件优选为二极管，但也可以是晶体管。当经受适当的电脉冲时，碳纳米管织物可逆地改变电阻率。可以感测碳纳米管织物的不同电阻率状态，并且可以对应于存储器单元的不同数据状态。这种存储器单元的第一存储器级别可以单片地形成在衬底上方，第一存储器级单元形成在第一存储器之上，等等，形成堆叠存储器级别的高密度单片三维存储器阵列。

62. 发明授权

US07419701B2 Low-temperature, low-resistivity heavily doped p-type polysilicon deposition 有权
标题翻译：低温，低电阻率重掺杂p型多晶硅沉积
公开(公告)号：US07419701B2
公开(公告)日：2008-09-02
申请号：US10769047
申请日：2004-01-30
申请人： S. Brad Herner , Mark H. Clark
发明人： S. Brad Herner , Mark H. Clark
IPC分类号： C23C16/08
CPC分类号： H01L21/8221 , C23C16/045 , C23C16/24 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L21/28525 , H01L27/1052
摘要： A method to create a low resistivity P+in-situ doped polysilicon film at low temperature from SiH4 and BCl3 with no anneal required. At conventional dopant concentrations using these source gases, as deposition temperature decreases below about 550 degrees C., deposition rate decreases and sheet resistance increases, making production of a high-quality film impossible. By flowing very high amounts of BCl3, however, such that the concentration of boron atoms in the resultant film is about 7×1020 or higher, the deposition rate and sheet resistance are improved, and a high-quality film is produced.
摘要翻译：在低温下从SiH 4和BCl 3 3生成低电阻P +原位掺杂多晶硅膜的方法，无需退火。在使用这些源气体的常规掺杂剂浓度下，随着沉积温度降低到约550℃以下，沉积速率降低并且薄层电阻增加，使得生产高质量膜不可能。然而，通过流动非常高量的BCl 3 3，使得所得膜中硼原子的浓度为约7×10 20或更高，沉积速率和薄层电阻为改进，并且制作出高质量的胶片。

63. 发明授权

US07405465B2 Deposited semiconductor structure to minimize n-type dopant diffusion and method of making 有权
标题翻译：沉积半导体结构以使n型掺杂剂扩散最小化和制备方法
公开(公告)号：US07405465B2
公开(公告)日：2008-07-29
申请号：US11298331
申请日：2005-12-09
申请人： S. Brad Herner
发明人： S. Brad Herner
IPC分类号： H01L31/117
CPC分类号： H01L45/08 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L29/161 , H01L29/165 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146
摘要： In deposited silicon, n-type dopants such as phosphorus and arsenic tend to seek the surface of the silicon, rising as the layer is deposited. When a second undoped or p-doped silicon layer is deposited on n-doped silicon with no n-type dopant provided, a first thickness of this second silicon layer nonetheless tends to include unwanted n-type dopant which has diffused up from lower levels. This surface-seeking behavior diminishes when germanium is alloyed with the silicon. In some devices, it may not be advantageous for the second layer to have significant germanium content. In the present invention, a first heavily n-doped semiconductor layer (preferably at least 10 at % germanium) is deposited, followed by a silicon-germanium capping layer with little or no n-type dopant, followed by a layer with little or no n-type dopant and less than 10 at % germanium. The germanium in the first layer and the capping layer minimizes diffusion of n-type dopant into the germanium-poor layer above.
摘要翻译：在沉积的硅中，诸如磷和砷的n型掺杂剂倾向于寻求硅的表面，随着层的沉积而上升。当在没有提供n型掺杂剂的n掺杂硅上沉积第二未掺杂或p掺杂的硅层时，该第二硅层的第一厚度倾向于包括从较低水平扩散的不期望的n型掺杂剂。当锗与硅合金化时，这种表面寻找行为减弱。在一些设备中，对于第二层可能不是有利的具有显着的锗含量。在本发明中，沉积第一重n掺杂的半导体层（优选至少10原子％的锗），随后是几乎没有或没有n型掺杂剂的硅 - 锗覆盖层，之后是几乎没有或没有 n型掺杂剂和少于10at％的锗。第一层和覆盖层中的锗使n型掺杂剂的扩散最小化到上述的锗贫层中。

64. 发明授权

US07329565B2 Silicide-silicon oxide-semiconductor antifuse device and method of making 有权
标题翻译：硅化硅 - 氧化硅半导体反熔丝装置及其制造方法
公开(公告)号：US07329565B2
公开(公告)日：2008-02-12
申请号：US10986196
申请日：2004-11-12
申请人： S. Brad Herner
发明人： S. Brad Herner
IPC分类号： H01L21/82
CPC分类号： H01L27/101 , H01L23/5252 , H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： An antifuse contains a first silicide layer, a grown silicon oxide antifuse layer on a first surface of the first silicide layer, and a first semiconductor layer having a first surface in contact with the antifuse layer.
摘要翻译：反熔丝包含第一硅化物层，在第一硅化物层的第一表面上生长的氧化硅反熔层，以及具有与反熔丝层接触的第一表面的第一半导体层。

65. 发明申请

US20070164309A1 METHOD OF MAKING A DIODE READ/WRITE MEMORY CELL IN A PROGRAMMED STATE 有权
标题翻译：在编程状态下制作二极管读/写存储单元的方法
公开(公告)号：US20070164309A1
公开(公告)日：2007-07-19
申请号：US11693845
申请日：2007-03-30
申请人： Tanmay Kumar , S. Brad Herner
发明人： Tanmay Kumar , S. Brad Herner
IPC分类号： H01L29/43
CPC分类号： G11C13/0069 , G11C11/5692 , G11C17/14 , G11C17/165 , G11C17/18 , G11C2013/0073 , H01L27/101 , H01L27/1021 , H01L29/868
摘要： A method of making a nonvolatile memory device includes fabricating a diode in a low resistivity, programmed state without an electrical programming step. The memory device includes at least one memory cell. The memory cell is constituted by the diode and electrically conductive electrodes contacting the diode.
摘要翻译：制造非易失性存储器件的方法包括在没有电气编程步骤的情况下制造低电阻率编程状态的二极管。存储器件包括至少一个存储单元。存储单元由二极管和与二极管接触的导电电极构成。

66. 发明授权

US06853049B2 Silicide-silicon oxide-semiconductor antifuse device and method of making 有权
标题翻译：硅化硅 - 氧化硅半导体反熔丝装置及其制造方法
公开(公告)号：US06853049B2
公开(公告)日：2005-02-08
申请号：US10095962
申请日：2002-03-13
申请人： S. Brad Herner
发明人： S. Brad Herner
IPC分类号： H01L23/525 , H01L29/00
CPC分类号： H01L27/101 , H01L23/5252 , H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： An antifuse contains a first silicide layer, a grown silicon oxide antifuse layer on a first surface of the first silicide layer, and a first semiconductor layer having a first surface in contact with the antifuse layer.
摘要翻译：反熔丝包含第一硅化物层，在第一硅化物层的第一表面上生长的氧化硅反熔层，以及具有与反熔丝层接触的第一表面的第一半导体层。

67. 发明授权

US08314477B2 Deposited semiconductor structure to minimize N-type dopant diffusion and method of making 有权
标题翻译：沉积的半导体结构使N型掺杂剂扩散最小化和制备方法
公开(公告)号：US08314477B2
公开(公告)日：2012-11-20
申请号：US13247723
申请日：2011-09-28
申请人： S. Brad Herner
发明人： S. Brad Herner
IPC分类号： H01L21/02
CPC分类号： H01L45/08 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L29/161 , H01L29/165 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146
摘要： A memory cell is provided that includes a semiconductor pillar and a reversible state-change element coupled to the semiconductor pillar. The semiconductor pillar includes a heavily doped bottom region of a first conductivity type, a heavily doped top region of a second conductivity type, and a lightly doped or intrinsic middle region interposed between and contacting the top and bottom regions. The middle region comprises a first proportion of germanium, and either the top region or the bottom region comprises no germanium or comprises a second proportion of germanium less than the first proportion. The reversible state-change element includes a layer of a resistivity-switching metal oxide or nitride compound selected from the group consisting of NiO, Nb2O5, TiO2, HfO2, Al2O3, CoO, MgOx, CrO2, VO, BN, and AlN. Numerous other aspects are provided.
摘要翻译：提供了存储单元，其包括半导体柱和耦合到半导体柱的可逆状态变换元件。半导体柱包括第一导电类型的重掺杂底部区域，第二导电类型的重掺杂顶部区域，以及插入并接触顶部区域和底部区域之间的轻掺杂或固有中间区域。中间区域包括第一比例的锗，并且顶部区域或底部区域不包含锗，或者包括小于第一比例的第二比例的锗。可逆态变化元件包括选自NiO，Nb 2 O 5，TiO 2，HfO 2，Al 2 O 3，CoO，MgO x，CrO 2，VO，BN和AlN的电阻率切换金属氧化物或氮化物层。提供了许多其他方面。

68. 发明授权

US08243509B2 Nonvolatile memory cell operating by increasing order in polycrystalline semiconductor material 有权
标题翻译：非易失性存储单元通过增加多晶半导体材料的顺序来操作
公开(公告)号：US08243509B2
公开(公告)日：2012-08-14
申请号：US13074509
申请日：2011-03-29
申请人： S. Brad Herner , Abhijit Bandyopadhyay
发明人： S. Brad Herner , Abhijit Bandyopadhyay
IPC分类号： G11C11/36 , G11C11/34 , G11C11/00
CPC分类号： G11C11/36 , G11C5/02 , G11C11/39 , G11C17/06 , G11C17/16 , H01L27/1021
摘要： A nonvolatile memory cell is described, the memory cell comprising a semiconductor diode. The semiconductor material making up the diode is formed with significant defect density, and allows very low current flow at a typical read voltage. Application of a programming voltage permanently changes the nature of the semiconductor material, resulting in an improved diode. The programmed diode allows much higher current flow, in some embodiments one, two or three orders of magnitude higher, at the same read voltage. The difference in current allows a programmed memory cell to be distinguished from an unprogrammed memory cell. Fabrication techniques to generate an advantageous unprogrammed defect density are described. The memory cell of the present invention can be formed in a monolithic three dimensional memory array, having multiple stacked memory levels formed above a single substrate.
摘要翻译：描述非易失性存储单元，存储单元包括半导体二极管。构成二极管的半导体材料形成有明显的缺陷密度，并且在典型的读取电压下允许非常低的电流流动。编程电压的应用永久地改变了半导体材料的性质，导致改进的二极管。在相同的读取电压下，编程的二极管允许更高的电流流动，在一些实施例中高一个，两个或三个数量级。电流差异允许将编程的存储器单元与未编程的存储器单元进行区分。描述了产生有利的未编程缺陷密度的制造技术。本发明的存储单元可以形成为在单个衬底上形成多个堆叠存储器级的单片三维存储器阵列。

69. 发明授权

US08163593B2 Method of making a nonvolatile phase change memory cell having a reduced contact area 有权
标题翻译：制造具有减小的接触面积的非挥发性相变存储单元的方法
公开(公告)号：US08163593B2
公开(公告)日：2012-04-24
申请号：US11560792
申请日：2006-11-16
申请人： Usha Raghuram , S. Brad Herner
发明人： Usha Raghuram , S. Brad Herner
IPC分类号： H01L21/00
CPC分类号： H01L45/144 , H01L27/2409 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1683 , H01L45/1691
摘要： A method is described to form a nonvolatile memory cell having a contact area between a phase-change material such as a chalcogenide and a heat source which is smaller than photolithographic limits. A conductive or semiconductor pillar is exposed at a dielectric surface and recessed by selective etch. A thin, conformal layer of a spacer material is deposited on the dielectric top surface, the pillar top surface, and the sidewalls of the recess, then removed from horizontal surfaces by anistropic etch, leaving a spacer on the sidewalls defining a reduced volume within the recess. The phase change material is deposited within the spacer, having a reduced contact area to the underlying conductive or semiconductor pillar.
摘要翻译：描述了一种形成非易失性存储单元的方法，所述非易失性存储单元具有诸如硫族化物的相变材料与小于光刻极限的热源之间的接触面积。导电或半导体柱在电介质表面露出并通过选择性蚀刻凹陷。间隔材料的薄的共形层被沉积在电介质顶表面，柱顶表面和凹槽的侧壁上，然后通过无功蚀刻从水平表面去除，在侧壁上留下间隔，限定内部减小的体积休息。相变材料沉积在间隔物内，具有减小的与下面的导电或半导体柱的接触面积。

70. 发明授权

US08049104B2 Intermetal stack for use in a photovoltaic cell 有权
标题翻译：用于光伏电池的金属间叠层
公开(公告)号：US08049104B2
公开(公告)日：2011-11-01
申请号：US12571415
申请日：2009-09-30
申请人： S. Brad Herner , Mark H. Clark
发明人： S. Brad Herner , Mark H. Clark
IPC分类号： H01L31/00
CPC分类号： H01L31/0747 , H01L21/187 , H01L31/1804 , H01L31/1896 , Y02E10/547 , Y02P70/521
摘要： A donor silicon wafer may be bonded to a substrate and a lamina cleaved from the donor wafer. A photovoltaic cell may be formed from the lamina bonded to the substrate. An intermetal stack is described that is optimized for use in such a cell. The intermetal stack may include a transparent conductive oxide layer serving as a quarter-wave plate, a low resistance layer, an adhesion layer to help adhesion to the receiver element, and may also include a barrier layer to prevent or impede unwanted diffusion within the stack.
摘要翻译：供体硅晶片可以结合到基底和从施主晶片分离的薄片。可以从结合到衬底的薄片形成光伏电池。描述了优化用于这种电池的金属间堆叠。金属间堆叠可以包括用作四分之一波片的透明导电氧化物层，低电阻层，用于帮助粘附到接收器元件的粘合层，并且还可以包括防止或阻碍堆叠内的不期望扩散的阻挡层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式