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61. 发明申请

US20140082630A1 PROVIDING AN ASYMMETRIC MULTICORE PROCESSOR SYSTEM TRANSPARENTLY TO AN OPERATING SYSTEM 有权
标题翻译：向操作系统提供不对称的多重处理器系统
公开(公告)号：US20140082630A1
公开(公告)日：2014-03-20
申请号：US13995994
申请日：2011-12-30
申请人： Boris Ginzburg , Ilya Osadchiy , Ronny Ronen , Eliezer Weissmann , Michael Mishaeli , Alon Naveh , David A. Koufaty , Scott D. Hahn , Tong Li , Avi Mendleson , Eugene Gorbatov , Hisham Abu-Salah , Dheeraj R. Subbareddy , Paolo Narvaez , Aamer Jaleel , Efraim Rotem , Yuval Yosef , Anil Aggarwal , Kenzo Van Craeynest
发明人： Boris Ginzburg , Ilya Osadchiy , Ronny Ronen , Eliezer Weissmann , Michael Mishaeli , Alon Naveh , David A. Koufaty , Scott D. Hahn , Tong Li , Avi Mendleson , Eugene Gorbatov , Hisham Abu-Salah , Dheeraj R. Subbareddy , Paolo Narvaez , Aamer Jaleel , Efraim Rotem , Yuval Yosef , Anil Aggarwal , Kenzo Van Craeynest
IPC分类号： G06F9/48
CPC分类号： G06F9/4881 , G06F9/30101 , G06F9/4856 , G06F15/7807 , Y02D10/12 , Y02D10/13 , Y02D10/24 , Y02D10/32
摘要： In one embodiment, the present invention includes a multicore processor with first and second groups of cores. The second group can be of a different instruction set architecture (ISA) than the first group or of the same ISA set but having different power and performance support level, and is transparent to an operating system (OS). The processor further includes a migration unit that handles migration requests for a number of different scenarios and causes a context switch to dynamically migrate a process from the second core to a first core of the first group. This dynamic hardware-based context switch can be transparent to the OS. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有第一和第二组核心的多核处理器。第二组可以是与第一组或同一ISA组不同的指令集架构（ISA），但具有不同的功率和性能支持级别，并且对于操作系统（OS）是透明的。处理器还包括迁移单元，其处理针对多个不同场景的迁移请求，并使上下文切换将进程从第二核心动态地迁移到第一组的第一核心。这种基于动态硬件的上下文切换对于操作系统可以是透明的。描述和要求保护其他实施例。

62. 发明授权

US08572358B2 Meta predictor restoration upon detecting misprediction 有权
公开(公告)号：US08572358B2
公开(公告)日：2013-10-29
申请号：US13647153
申请日：2012-10-08
申请人： Ronny Ronen , Mattan Erez , Stephan Jourdan , Adi Yoaz
发明人： Ronny Ronen , Mattan Erez , Stephan Jourdan , Adi Yoaz
IPC分类号： G06F9/00 , G06F9/44
CPC分类号： G06F9/3861 , G06F9/3848
摘要： Methods and apparatus for restoring a meta predictor system upon detecting a branch or binary misprediction, are disclosed. An example apparatus may include a base misprediction history register to store a set of misprediction history values each indicating whether a previous branch prediction taken by a previous branch instruction was predicted correctly or incorrectly. The apparatus may comprise a meta predictor to detect a branch misprediction of a current branch prediction based at least in part on an output of the base misprediction history register. The meta predictor may restore the base misprediction history register based on the detecting of the branch misprediction. Additional apparatus, systems, and methods are disclosed.

63. 发明申请

US20130262816A1 TRANSLATION LOOKASIDE BUFFER FOR MULTIPLE CONTEXT COMPUTE ENGINE 有权
标题翻译：多语言计算机引擎的翻译LOOKASIDE缓冲区
公开(公告)号：US20130262816A1
公开(公告)日：2013-10-03
申请号：US13993800
申请日：2011-12-30
申请人： Ronny Ronen , Boris Ginzburg , Eliezer Weissmann , Karthikeyan Vaithianathan
发明人： Ronny Ronen , Boris Ginzburg , Eliezer Weissmann , Karthikeyan Vaithianathan
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F12/0806 , G06F12/0842 , G06F12/1009 , G06F12/1036 , G06F2212/1016 , G06F2212/65 , G06F2212/68 , G06F2212/683 , G06F2212/684
摘要： Some implementations disclosed herein provide techniques and arrangements for an specialized logic engine that includes translation lookaside buffer to support multiple threads executing on multiple cores. The translation lookaside buffer enables the specialized logic engine to directly access a virtual address of a thread executing on one of the plurality of processing cores. For example, an acceleration compute engine may receive one or more instructions from a thread executed by a processing core. The acceleration compute engine may retrieve, based on an address space identifier associated with the one or more instructions, a physical address associated with the one or more instructions from the translation lookaside buffer to execute the one or more instructions using the physical address.
摘要翻译：本文公开的一些实施例提供了专用逻辑引擎的技术和布置，其包括翻译后备缓冲器以支持在多个核上执行的多个线程。翻译后备缓冲器使得专用逻辑引擎能够直接访问在多个处理核之一上执行的线程的虚拟地址。例如，加速计算引擎可以从由处理核心执行的线程接收一个或多个指令。所述加速度计算引擎可以基于与所述一个或多个指令相关联的地址空间标识符，从所述翻译后备缓冲器中检索与所述一个或多个指令相关联的物理地址，以使用所述物理地址来执行所述一个或多个指令。

64. 发明申请

US20130219196A1 POWER MANAGEMENT FOR MULTIPLE PROCESSOR CORES 审中-公开
标题翻译：多处理器电源的电源管理
公开(公告)号：US20130219196A1
公开(公告)日：2013-08-22
申请号：US13847392
申请日：2013-03-19
申请人： Lev Finkelstein , Efraim Rotem , Aviad Cohen , Ronny Ronen , Doron Rajwan
发明人： Lev Finkelstein , Efraim Rotem , Aviad Cohen , Ronny Ronen , Doron Rajwan
IPC分类号： G06F1/26
CPC分类号： G06F1/26 , G06F1/206 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/16 , Y02D10/172
摘要： Methods and apparatus relating to power management for multiple processor cores are described. In one embodiment, one or more techniques may be utilized locally (e.g., on a per core basis) to manage power consumption in a processor. In another embodiment, power may be distributed among different power planes of a processor based on energy-based considerations. Other embodiments are also disclosed and claimed.
摘要翻译：描述与多个处理器核心的电源管理相关的方法和装置。在一个实施例中，本地可以利用一个或多个技术（例如，基于每个核心）来管理处理器中的功率消耗。在另一个实施例中，功率可以基于能量考虑而分布在处理器的不同功率层之间。还公开并要求保护其他实施例。

65. 发明授权

US07934110B2 Dynamically managing thermal levels in a processing system 有权
标题翻译：在处理系统中动态管理热水平
公开(公告)号：US07934110B2
公开(公告)日：2011-04-26
申请号：US11861186
申请日：2007-09-25
申请人： Lev Finkelstein , Aviad Cohen , Ronny Ronen , Efraim Rotem
发明人： Lev Finkelstein , Aviad Cohen , Ronny Ronen , Efraim Rotem
IPC分类号： G06F1/26 , G06F1/22
CPC分类号： G06F1/206 , G05D23/1935
摘要： A technique to dynamically maintain the thermal levels of a plurality of cores of a processing system by interleave core hopping with throttling techniques. The interleaving logic may transfer execution of threads from a hot core to a cold if core hopping is applicable. Core hopping may be applicable if there exist a cold core to which the execution of threads can be assigned to from a hot core and if the rate of occurrence of core hopping is within an allowable rate value. The interleaving logic may apply throttling techniques if core hopping is not applicable. The throttling techniques may throttle the throttling parameters, which may comprise voltage, frequency, and micro-architecture throttling parameters provided to the hot core if the core hopping is not applicable.
摘要翻译：通过采用节流技术的交错核心跳跃来动态地维持处理系统的多个核心的热水平的技术。如果核心跳跃可应用，交错逻辑可以将线程的执行从热核心转移到冷。如果存在可以从热核心分配线程的执行的冷核心以及核心跳跃的发生速率在可允许的速率值内的情况下，可以应用核心跳频。如果核心跳频不适用，交错逻辑可以应用节流技术。节流技术可以节流节流参数，其可以包括提供给热核心的电压，频率和微架构节流参数，如果核心跳频不适用。

66. 发明申请

US20090083551A1 DYNAMICALLY MANAGING THERMAL LEVELS IN A PROCESSING SYSTEM 有权
标题翻译：在处理系统中动态地管理热水平
公开(公告)号：US20090083551A1
公开(公告)日：2009-03-26
申请号：US11861186
申请日：2007-09-25
申请人： Lev Finkelstein , Aviad Cohen , Ronny Ronen , Efraim Rotem
发明人： Lev Finkelstein , Aviad Cohen , Ronny Ronen , Efraim Rotem
IPC分类号： G05D23/00 , G06F1/00
CPC分类号： G06F1/206 , G05D23/1935
摘要： A technique to dynamically maintain the thermal levels of a plurality of cores of a processing system by interleave core hopping with throttling techniques. The interleaving logic may transfer execution of threads from a hot core to a cold if core hopping is applicable. Core hopping may be applicable if there exist a cold core to which the execution of threads can be assigned to from a hot core and if the rate of occurrence of core hopping is within an allowable rate value. The interleaving logic may apply throttling techniques if core hopping is not applicable. The throttling techniques may throttle the throttling parameters, which may comprise voltage, frequency, and micro-architecture throttling parameters provided to the hot core if the core hopping is not applicable.
摘要翻译：通过采用节流技术的交错核心跳跃来动态地维持处理系统的多个核心的热水平的技术。如果核心跳跃可应用，交错逻辑可以将线程的执行从热核心转移到冷。如果存在可以从热核心分配线程的执行的冷核心以及核心跳跃的发生速率在可允许的速率值内的情况下，可以应用核心跳频。如果核心跳频不适用，交错逻辑可以应用节流技术。节流技术可以节流节流参数，其可以包括提供给热核心的电压，频率和微架构节流参数，如果核心跳频不适用。

67. 发明授权

US07284116B2 Method and system for safe data dependency collapsing based on control-flow speculation 有权
标题翻译：基于控制流猜测的安全数据依赖性崩溃的方法和系统
公开(公告)号：US07284116B2
公开(公告)日：2007-10-16
申请号：US10307557
申请日：2002-12-02
申请人： Stephan J. Jourdan , Freddy Gabbay , Ronny Ronen , Adi Yoaz
发明人： Stephan J. Jourdan , Freddy Gabbay , Ronny Ronen , Adi Yoaz
IPC分类号： G06F9/34
CPC分类号： G06F9/30094 , G06F9/383 , G06F9/3832 , G06F9/384 , G06F9/3842 , G06F9/3863
摘要： The present invention is directed to an apparatus and method for data collapsing based on control-flow speculation (conditional branch predictions). Because conditional branch outcomes are resolved based on actual data values, the conditional branch prediction provides potentially valuable insight into data values. Upon encountering a branch if equal instruction and this instruction is predicted as taken or a branch if not equal instruction and this instruction is predicted as not taken, this invention assumes that the two operands used to determine the conditional branch are equal. The data predictions are safe because a data misprediction means a conditional branch misprediction which results in a pipeline flush of the instructions following the conditional branch instruction including the data mispredictions.
摘要翻译：本发明涉及一种基于控制流推测（条件分支预测）的数据压缩的装置和方法。由于条件分支结果基于实际数据值进行解析，条件分支预测提供了对数据值的潜在有价值的洞察。如果相等的指令遇到分支，并且如果不是相等的指令预测该指令或分支，并且该指令被预测为未被使用，则本发明假设用于确定条件分支的两个操作数相等。数据预测是安全的，因为数据错误预测是指条件分支错误预测，导致在包括数据错误预测的条件分支指令之后的指令的流水线刷新。

68. 发明申请

US20060273753A1 METHODS AND APPARATUS FOR OPTIMAL VOLTAGE AND FREQUENCY CONTROL OF THERMALLY LIMITED SYSTEMS 失效
标题翻译：热电有限系统的最佳电压和频率控制方法与装置
公开(公告)号：US20060273753A1
公开(公告)日：2006-12-07
申请号：US11459407
申请日：2006-07-24
申请人： Aviad Cohen , Lev Finkelstein , Avi Mendelson , Ronny Ronen , Dmitry Rudoy
发明人： Aviad Cohen , Lev Finkelstein , Avi Mendelson , Ronny Ronen , Dmitry Rudoy
IPC分类号： H02P21/00
CPC分类号： H02H6/005 , G06F1/206 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/16 , Y02D10/172 , Y10S388/934
摘要： Methods, apparatus, and articles of manufacture control a device or system that has an operational limit related to the rate or frequency of operation. The frequency of operation is controlled at a variable rate calculated to maximize the system or apparatus performance over a calculated period of time short enough that a controlling factor, such as power consumption, does not vary significantly during the period. Known system parameters, such as thermal resistance and capacitance of an integrated circuit (IC) and its package, and measured values, such as current junction temperature in an IC, are used to calculate a time-dependent frequency of operation for the upcoming time period that results in the best overall performance without exceeding the operational limit, such as the junction temperature.
摘要翻译：方法，装置和制品控制具有与操作速率或频率相关的操作限制的装置或系统。操作频率被控制为可变速率，其被计算为在足够长的计算时间段内最大化系统或设备性能，使得诸如功率消耗的控制因素在该时段期间不显着变化。使用已知的系统参数，例如集成电路（IC）及其封装的热阻和电容以及IC中的当前结温等测量值来计算即将到来的时间段的时间依赖性操作频率这导致最佳的整体性能，而不超过操作限制，如结温。

69. 发明授权

US07062638B2 Prediction of issued silent store operations for allowing subsequently issued loads to bypass unexecuted silent stores and confirming the bypass upon execution of the stores 失效
标题翻译：预测发出的无声存储操作，允许随后发出的负载绕过未执行的无声存储，并在执行存储时确认旁路
公开(公告)号：US07062638B2
公开(公告)日：2006-06-13
申请号：US09752796
申请日：2000-12-29
申请人： Adi Yoaz , Ronny Ronen , Rajesh Patel
发明人： Adi Yoaz , Ronny Ronen , Rajesh Patel
IPC分类号： G06F9/312
CPC分类号： G06F9/3834 , G06F9/3832 , G06F9/3838
摘要： An electronic device including a predictor that has a collision history table (CHT) is presented. An extended load buffer is connected to the predictor. Also included is a marking unit, a comparing unit and a recovery unit connected to the extended load buffer. Unexecuted load instructions are advanced over store instructions. Also presented is a method for fetching an instruction and determining if an instruction is a store or a load. If the instruction is a store, then the method performs a silent store prediction. If the instruction is a load, a predicted silent store instruction is bypassed and the load instruction is executed.
摘要翻译：提出了一种包括具有冲突历史表（CHT）的预测器的电子设备。扩展加载缓冲区连接到预测器。还包括标记单元，比较单元和连接到扩展加载缓冲器的恢复单元。未执行的加载指令超过存储指令。还提出了一种用于获取指令并确定指令是存储还是加载的方法。如果指令是存储，则该方法执行静默存储预测。如果指令是负载，则旁路预测的无声存储指令，并执行加载指令。

70. 发明申请

US20060095807A1 Method and apparatus for varying energy per instruction according to the amount of available parallelism 有权
标题翻译：根据可用的并行度量来改变每个指令的能量的方法和装置
公开(公告)号：US20060095807A1
公开(公告)日：2006-05-04
申请号：US10952627
申请日：2004-09-28
申请人： Edward Grochowski , John Shen , Hong Wang , Doron Orenstein , Gad Sheaffer , Ronny Ronen , Murali Annavaram
发明人： Edward Grochowski , John Shen , Hong Wang , Doron Orenstein , Gad Sheaffer , Ronny Ronen , Murali Annavaram
IPC分类号： G06F1/30
CPC分类号： G06F9/3851 , G06F1/206 , G06F1/3203 , G06F1/329 , G06F9/3885 , G06F9/3891 , G06F9/3897 , Y02D10/16 , Y02D10/24 , Y02D50/20
摘要： A method and apparatus for changing the configuration of a multi-core processor is disclosed. In one embodiment, a throttle module (or throttle logic) may determine the amount of parallelism present in the currently-executing program, and change the execution of the threads of that program on the various cores. If the amount of parallelism is high, then the processor may be configured to run a larger amount of threads on cores configured to consume less power. If the amount of parallelism is low, then the processor may be configured to run a smaller amount of threads on cores configured for greater scalar performance.
摘要翻译：公开了一种用于改变多核处理器的配置的方法和装置。在一个实施例中，节气门模块（或节气门逻辑）可以确定当前执行的程序中存在的并行度量，并且改变该程序在各种核心上的线程的执行。如果并行量高，则处理器可以被配置为在被配置为消耗较少功率的核上运行更大量的线程。如果并行量较低，则处理器可能被配置为在配置为更高标量性能的核心上运行较少量的线程。

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