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1. 发明授权

US09720730B2 Providing an asymmetric multicore processor system transparently to an operating system 有权
公开(公告)号：US09720730B2
公开(公告)日：2017-08-01
申请号：US13995994
申请日：2011-12-30
申请人： Boris Ginzburg , Ilya Osadchiy , Ronny Ronen , Eliezer Weissmann , Michael Mishaeli , Alon Naveh , David A. Koufaty , Scott D. Hahn , Tong Li , Avi Mendleson , Eugene Gorbatov , Hisham Abu-Salah , Dheeraj R. Subbareddy , Paolo Narvaez , Aamer Jaleel , Efraim Rotem , Yuval Yosef , Anil Aggarwal , Kenzo Van Craeynest
发明人： Boris Ginzburg , Ilya Osadchiy , Ronny Ronen , Eliezer Weissmann , Michael Mishaeli , Alon Naveh , David A. Koufaty , Scott D. Hahn , Tong Li , Avi Mendleson , Eugene Gorbatov , Hisham Abu-Salah , Dheeraj R. Subbareddy , Paolo Narvaez , Aamer Jaleel , Efraim Rotem , Yuval Yosef , Anil Aggarwal , Kenzo Van Craeynest
IPC分类号： G06F9/46 , G06F9/50 , G06F9/48 , G06F9/30 , G06F15/78
CPC分类号： G06F9/4881 , G06F9/30101 , G06F9/4856 , G06F15/7807 , Y02D10/12 , Y02D10/13 , Y02D10/24 , Y02D10/32
摘要： In one embodiment, the present invention includes a multicore processor with first and second groups of cores. The second group can be of a different instruction set architecture (ISA) than the first group or of the same ISA set but having different power and performance support level, and is transparent to an operating system (OS). The processor further includes a migration unit that handles migration requests for a number of different scenarios and causes a context switch to dynamically migrate a process from the second core to a first core of the first group. This dynamic hardware-based context switch can be transparent to the OS. Other embodiments are described and claimed.

2. 发明申请

US20140082630A1 PROVIDING AN ASYMMETRIC MULTICORE PROCESSOR SYSTEM TRANSPARENTLY TO AN OPERATING SYSTEM 有权
标题翻译：向操作系统提供不对称的多重处理器系统
公开(公告)号：US20140082630A1
公开(公告)日：2014-03-20
申请号：US13995994
申请日：2011-12-30
申请人： Boris Ginzburg , Ilya Osadchiy , Ronny Ronen , Eliezer Weissmann , Michael Mishaeli , Alon Naveh , David A. Koufaty , Scott D. Hahn , Tong Li , Avi Mendleson , Eugene Gorbatov , Hisham Abu-Salah , Dheeraj R. Subbareddy , Paolo Narvaez , Aamer Jaleel , Efraim Rotem , Yuval Yosef , Anil Aggarwal , Kenzo Van Craeynest
发明人： Boris Ginzburg , Ilya Osadchiy , Ronny Ronen , Eliezer Weissmann , Michael Mishaeli , Alon Naveh , David A. Koufaty , Scott D. Hahn , Tong Li , Avi Mendleson , Eugene Gorbatov , Hisham Abu-Salah , Dheeraj R. Subbareddy , Paolo Narvaez , Aamer Jaleel , Efraim Rotem , Yuval Yosef , Anil Aggarwal , Kenzo Van Craeynest
IPC分类号： G06F9/48
CPC分类号： G06F9/4881 , G06F9/30101 , G06F9/4856 , G06F15/7807 , Y02D10/12 , Y02D10/13 , Y02D10/24 , Y02D10/32
摘要： In one embodiment, the present invention includes a multicore processor with first and second groups of cores. The second group can be of a different instruction set architecture (ISA) than the first group or of the same ISA set but having different power and performance support level, and is transparent to an operating system (OS). The processor further includes a migration unit that handles migration requests for a number of different scenarios and causes a context switch to dynamically migrate a process from the second core to a first core of the first group. This dynamic hardware-based context switch can be transparent to the OS. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有第一和第二组核心的多核处理器。第二组可以是与第一组或同一ISA组不同的指令集架构（ISA），但具有不同的功率和性能支持级别，并且对于操作系统（OS）是透明的。处理器还包括迁移单元，其处理针对多个不同场景的迁移请求，并使上下文切换将进程从第二核心动态地迁移到第一组的第一核心。这种基于动态硬件的上下文切换对于操作系统可以是透明的。描述和要求保护其他实施例。

3. 发明申请

US20160182373A1 TECHNOLOGIES FOR NETWORK DEVICE FLOW LOOKUP MANAGEMENT 审中-公开
标题翻译：网络流量查询管理技术
公开(公告)号：US20160182373A1
公开(公告)日：2016-06-23
申请号：US14580801
申请日：2014-12-23
申请人： Ren Wang , Namakkal N. Venkatesan , Aamer Jaleel , Tsung-Yuan C. Tai , Sameh Gobriel , Christian Maciocco
发明人： Ren Wang , Namakkal N. Venkatesan , Aamer Jaleel , Tsung-Yuan C. Tai , Sameh Gobriel , Christian Maciocco
IPC分类号： H04L12/743 , H04L12/747 , H04L29/06
CPC分类号： H04L45/7453 , H04L45/742 , H04L69/22
摘要： Technologies for managing network flow lookups of a network device include a network controller and a target device, each communicatively coupled to the network device. The network device includes a cache for a processor of the network device and a main memory. The network device additionally includes a multi-level hash table having a first-level hash table stored in the cache of the network device and a second-level hash table stored in the main memory of the network device. The network device is configured to determine whether to store a network flow hash corresponding to a network flow indicating the target device in the first-level or second-level hash table based on a priority of the network flow provided to the network device by the network controller.
摘要翻译：用于管理网络设备的网络流查找的技术包括网络控制器和目标设备，每个通信地耦合到网络设备。网络设备包括用于网络设备的处理器的缓存和主存储器。网络设备还包括具有存储在网络设备的高速缓存中的第一级散列表的多级散列表和存储在网络设备的主存储器中的第二级散列表。网络设备被配置为基于由网络提供给网络设备的网络流的优先级来确定是否将与指示目标设备的网络流相对应的网络流哈希存储在第一级或第二级哈希表中控制器。

4. 发明授权

US08769209B2 Method and apparatus for achieving non-inclusive cache performance with inclusive caches 有权
标题翻译：用于通过包含缓存实现非包容性缓存性能的方法和装置
公开(公告)号：US08769209B2
公开(公告)日：2014-07-01
申请号：US12973051
申请日：2010-12-20
申请人： Aamer Jaleel , Simon C. Steely, Jr. , Eric R. Borch , Malini K. Bhandaru , Joel S. Emer
发明人： Aamer Jaleel , Simon C. Steely, Jr. , Eric R. Borch , Malini K. Bhandaru , Joel S. Emer
IPC分类号： G06F12/12
CPC分类号： G06F12/0813 , G06F12/128
摘要： An apparatus and method for improving cache performance in a computer system having a multi-level cache hierarchy. For example, one embodiment of a method comprises: selecting a first line in a cache at level N for potential eviction; querying a cache at level M in the hierarchy to determine whether the first cache line is resident in the cache at level M, wherein M
摘要翻译：一种用于在具有多级高速缓存层级的计算机系统中提高高速缓存性能的装置和方法。例如，方法的一个实施例包括：在级别N的高速缓存中选择潜在驱逐的第一行; 查询层级中的级别M的高速缓存，以确定第一高速缓存行是否驻留在级别M的高速缓存中，其中M

5. 发明申请

US20120084497A1 Instruction Prefetching Using Cache Line History 有权
标题翻译：使用缓存线历史记录进行指令预取
公开(公告)号：US20120084497A1
公开(公告)日：2012-04-05
申请号：US12895387
申请日：2010-09-30
申请人： Samantika Subramaniam , Aamer Jaleel , Simon C. Steely, JR.
发明人： Samantika Subramaniam , Aamer Jaleel , Simon C. Steely, JR.
IPC分类号： G06F12/06 , G06F12/08
CPC分类号： G06F12/0862 , G06F9/3816 , G06F2212/452 , G06F2212/6024 , Y02D10/13
摘要： An apparatus of an aspect includes a prefetch cache line address predictor to receive a cache line address and to predict a next cache line address to be prefetched. The next cache line address may indicate a cache line having at least 64-bytes of instructions. The prefetch cache line address predictor may have a cache line target history storage to store a cache line target history for each of multiple most recent corresponding cache lines. Each cache line target history may indicate whether the corresponding cache line had a sequential cache line target or a non-sequential cache line target. The cache line address predictor may also have a cache line target history predictor. The cache line target history predictor may predict whether the next cache line address is a sequential cache line address or a non-sequential cache line address, based on the cache line target history for the most recent cache lines.
摘要翻译：一方面的装置包括预取高速缓存行地址预测器，用于接收高速缓存行地址并预测要预取的下一个高速缓存行地址。下一个高速缓存行地址可以指示具有至少64字节指令的高速缓存行。预取高速缓存线地址预测器可以具有高速缓存行目标历史存储器，以存储多个最新对应的高速缓存行中的每一个的高速缓存行目标历史。每个高速缓存行目标历史可以指示对应的高速缓存线是否具有顺序高速缓存行目标或非顺序高速缓存行目标。高速缓存行地址预测器也可以具有高速缓存行目标历史预测器。高速缓存行目标历史预测器可以基于最近的高速缓存行的高速缓存行目标历史来预测下一个高速缓存行地址是顺序高速缓存行地址还是非顺序高速缓存行地址。

6. 发明授权

US07725657B2 Dynamic quality of service (QoS) for a shared cache 有权
标题翻译：共享缓存的动态服务质量（QoS）
公开(公告)号：US07725657B2
公开(公告)日：2010-05-25
申请号：US11726238
申请日：2007-03-21
申请人： William C. Hasenplaugh , Li Zhao , Ravishankar Iyer , Ramesh Illikkal , Srihari Makineni , Donald Newell , Aamer Jaleel , Simon C. Steely, Jr.
发明人： William C. Hasenplaugh , Li Zhao , Ravishankar Iyer , Ramesh Illikkal , Srihari Makineni , Donald Newell , Aamer Jaleel , Simon C. Steely, Jr.
IPC分类号： G06F12/06
CPC分类号： G06F12/084 , G06F12/0842
摘要： In one embodiment, the present invention includes a method for associating a first priority indicator with data stored in a first entry of a shared cache memory by a core to indicate a priority level of a first thread, and associating a second priority indicator with data stored in a second entry of the shared cache memory by a graphics engine to indicate a priority level of a second thread. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于将第一优先级指示符与存储在共享高速缓冲存储器的第一条目中的数据相关联以指示第一线程的优先级，并且将第二优先级指示符与存储的数据相关联的方法在图形引擎的共享高速缓冲存储器的第二条目中指示第二线程的优先级。描述和要求保护其他实施例。

7. 发明申请

US20210004328A1 HARDWARE/SOFTWARE CO-OPTIMIZATION TO IMPROVE PERFORMANCE AND ENERGY FOR INTER-VM COMMUNICATION FOR NFVS AND OTHER PRODUCER-CONSUMER WORKLOADS 有权
公开(公告)号：US20210004328A1
公开(公告)日：2021-01-07
申请号：US17027248
申请日：2020-09-21
申请人： Ren Wang , Andrew J. Herdrich , Yen-cheng Liu , Herbert H. Hum , Jong Soo Park , Christopher J. Hughes , Namakkal N. Venkatesan , Adrian C. Moga , Aamer Jaleel , Zeshan A. Chishti , Mesut A. Ergin , Jr-shian Tsai , Alexander W. Min , Tsung-yuan C. Tai , Christian Maciocco , Rajesh Sankaran
发明人： Ren Wang , Andrew J. Herdrich , Yen-cheng Liu , Herbert H. Hum , Jong Soo Park , Christopher J. Hughes , Namakkal N. Venkatesan , Adrian C. Moga , Aamer Jaleel , Zeshan A. Chishti , Mesut A. Ergin , Jr-shian Tsai , Alexander W. Min , Tsung-yuan C. Tai , Christian Maciocco , Rajesh Sankaran
IPC分类号： G06F12/0842 , G06F12/0831 , G06F12/0893 , G06F12/109 , G06F12/0813 , G06F9/455
摘要： Methods and apparatus implementing Hardware/Software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads. The apparatus include multi-core processors with multi-level cache hierarchies including and L1 and L2 cache for each core and a shared last-level cache (LLC). One or more machine-level instructions are provided for proactively demoting cachelines from lower cache levels to higher cache levels, including demoting cachelines from L1/L2 caches to an LLC. Techniques are also provided for implementing hardware/software co-optimization in multi-socket NUMA architecture system, wherein cachelines may be selectively demoted and pushed to an LLC in a remote socket. In addition, techniques are disclosure for implementing early snooping in multi-socket systems to reduce latency when accessing cachelines on remote sockets.

8. 发明申请

US20150234663A1 Instruction and Logic for Run-time Evaluation of Multiple Prefetchers 有权
标题翻译：多个预取器运行时评估的指令和逻辑
公开(公告)号：US20150234663A1
公开(公告)日：2015-08-20
申请号：US14181032
申请日：2014-02-14
申请人： Zeshan A. Chishti , Christopher B. Wilkerson , Seth Pugsley , Peng-Fei Chuang , Robert L. Scott , Aamer Jaleel , Shih-Lien L. Lu , Kingsum Chow
发明人： Zeshan A. Chishti , Christopher B. Wilkerson , Seth Pugsley , Peng-Fei Chuang , Robert L. Scott , Aamer Jaleel , Shih-Lien L. Lu , Kingsum Chow
IPC分类号： G06F9/38 , G06F12/08
CPC分类号： G06F12/0862 , G06F9/3802 , G06F9/3808 , G06F9/383 , G06F2212/6026
摘要： A processor includes a cache, a prefetcher module to select information according to a prefetcher algorithm, and a prefetcher algorithm selection module. The prefetcher algorithm selection module includes logic to select a candidate prefetcher algorithm determine and store memory addresses of predicted memory accesses of the candidate prefetcher algorithm when performed by the prefetcher module, determine cache lines accessed during memory operations, and evaluate whether the determined cache lines match the stored memory addresses. The prefetcher algorithm selection module further includes logic to adjust an accuracy ratio of the candidate prefetcher algorithm, compare the accuracy ratio with a threshold accuracy ratio, and determine whether to apply the first candidate prefetcher algorithm to the prefetcher module.
摘要翻译：处理器包括高速缓存，根据预取器算法选择信息的预取器模块以及预取器算法选择模块。预取器算法选择模块包括选择候选预取器算法的逻辑，当由预取器模块执行时，确定并存储候选预取器算法的预测存储器访问的存储器地址，确定在存储器操作期间访问的高速缓存行，并且评估所确定的高速缓存行是否匹配存储的存储器地址。预取器算法选择模块还包括用于调整候选预取器算法的准确率的逻辑，将精度比与阈值精度比进行比较，并且确定是否将第一候选预取器算法应用于预取器模块。

9. 发明申请

US20150089162A1 DISTRIBUTED MEMORY OPERATIONS 审中-公开
标题翻译：分布式存储器操作
公开(公告)号：US20150089162A1
公开(公告)日：2015-03-26
申请号：US14037468
申请日：2013-09-26
申请人： Bushra Ahsan , Michael C. Adler , Neal C. Crago , Joel S. Emer , Aamer Jaleel , Angshuman Parashar , Michael I. Pellauer
发明人： Bushra Ahsan , Michael C. Adler , Neal C. Crago , Joel S. Emer , Aamer Jaleel , Angshuman Parashar , Michael I. Pellauer
IPC分类号： G06F3/06
CPC分类号： G06F13/1663 , G06F12/0646 , G06F13/1652 , G06F13/1684 , G06F2213/00
摘要： A technology for implementing a method for distributed memory operations. A method of the disclosure includes obtaining distributed channel information for an algorithm to be executed by a plurality of spatially distributed processing elements. For each distributed channel in the distributed channel information, the method further associates one or more of the plurality of spatially distributed processing elements with the distributed channel based on the algorithm.
摘要翻译：一种实现分布式存储器操作方法的技术。本公开的方法包括获得要由多个空间分布的处理元件执行的算法的分布式信道信息。对于分布式信道信息中的每个分布式信道，该方法还基于该算法进一步将多个空间分布处理单元中的一个或多个与分布式信道相关联。

10. 发明授权

US08839259B2 Thread scheduling on multiprocessor systems 有权
标题翻译：多处理器系统上的线程调度
公开(公告)号：US08839259B2
公开(公告)日：2014-09-16
申请号：US13355611
申请日：2012-01-23
申请人： Wenlong Li , Tao Wang , Aamer Jaleel , Yimin Zhang
发明人： Wenlong Li , Tao Wang , Aamer Jaleel , Yimin Zhang
IPC分类号： G06F9/46 , G06F9/38 , G06F9/50
CPC分类号： G06F9/5044 , G06F9/3836 , G06F9/3851 , G06F9/3885 , G06F9/3891
摘要： A thread scheduler may be used in a chip multiprocessor or symmetric multiprocessor system to schedule threads to processors. The scheduler may determine the bandwidth utilization of the two threads in combination and whether that utilization exceeds the threshold value. If so, the threads may be scheduled on different processor clusters that do not have the same paths between the common memory and the processors. If not, then the threads may be allocated on the same processor cluster that shares cache among processors.
摘要翻译：线程调度器可以用在芯片多处理器或对称多处理器系统中以将线程调度到处理器。调度器可以组合确定两个线程的带宽利用率以及该利用率是否超过阈值。如果是这样，线程可能被调度在公共存储器和处理器之间没有相同路径的不同处理器集群上。如果没有，那么线程可能会分配在处理器之间共享高速缓存的同一个处理器集群上。

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