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61. 发明申请

US20080129576A1 Multi-bit pipeline analog-to-digital converter having merged capacitor switching structure 有权
标题翻译：具有并联电容器开关结构的多位流水线模数转换器
公开(公告)号：US20080129576A1
公开(公告)日：2008-06-05
申请号：US11903476
申请日：2007-09-20
申请人： Young Deuk Jeon , Seung Chul Lee , Kwi Dong Kim , Chong Ki Kwon , Jong Dae Kim
发明人： Young Deuk Jeon , Seung Chul Lee , Kwi Dong Kim , Chong Ki Kwon , Jong Dae Kim
IPC分类号： H03M1/14
CPC分类号： H03M1/0682 , H03M1/167 , H03M1/804
摘要： Provided is a multi-bit pipeline analog-to-digital converter (ADC) having a merged capacitor switching structure. In a multiplying digital-to-analog converter (MDAC) used in the multi-bit pipeline ADC, switches are connected between the bottom plates of respective differential capacitors, thereby constantly maintaining a uniform input common mode voltage regardless of an input digital code. Thus, it is possible to improve the operating speed and performance of the MDAC.
摘要翻译：提供了具有合并电容器开关结构的多位流水线模数转换器（ADC）。在多位流水线ADC中使用的乘法数模转换器（MDAC）中，开关连接在各个差分电容器的底板之间，从而不管输入数字代码如何，始终保持均匀的输入共模电压。因此，可以提高MDAC的操作速度和性能。

62. 发明申请

US20080129338A1 HIGH-SPEED ASYNCHRONOUS DIGITAL SIGNAL LEVEL CONVERSION CIRCUIT 失效
标题翻译：高速异步数字信号电平转换电路
公开(公告)号：US20080129338A1
公开(公告)日：2008-06-05
申请号：US11943031
申请日：2007-11-20
申请人： Min Hyung CHO , Kwi Dong KIM , Chong Ki KWON
发明人： Min Hyung CHO , Kwi Dong KIM , Chong Ki KWON
IPC分类号： H03K19/0948 , H03K19/0185
CPC分类号： H03K19/018528 , H03K19/0948
摘要： Provided is a high-speed asynchronous digital signal level conversion circuit converting an input signal of a first voltage level into a signal of a second voltage level. The conversion circuit is able to operate at high speed by connecting first and second nodes, at which the input signal of the first voltage level is converted to the signal of the second voltage level, to a second power source voltage of the second voltage level for fast voltage level conversion when the voltage level of the input signal is changed.
摘要翻译：提供了将第一电压电平的输入信号转换为第二电压电平的信号的高速异步数字信号电平转换电路。转换电路能够通过将第一和第二节点（第一电压电平的输入信号被转换为第二电压电平的信号）连接到第二电压电平的第二电源电压，当输入信号的电压电平改变时，进行快速电压电平转换。

63. 发明申请

US20070268767A1 Circuit and method for controlling self-refresh cycle 有权
标题翻译：控制自刷新周期的电路和方法
公开(公告)号：US20070268767A1
公开(公告)日：2007-11-22
申请号：US11647763
申请日：2006-12-29
申请人： Kwi Dong Kim
发明人： Kwi Dong Kim
IPC分类号： G11C11/406
CPC分类号： G11C11/406 , G11C7/04 , G11C11/40615 , G11C11/40626 , G11C2211/4061 , G11C2211/4068
摘要： The present invention relates to a circuit and a method for controlling a self-refresh cycle of a dynamic random access memory or DRAM. A cell voltage is directly detected so that a self-refresh cycle can be variably controlled. Detectors each detecting whether or not a voltage charged into a capacitor of a detection cell drops to or below a reference voltage and outputs a detection signal. A pulse generator generates a self-refresh pulse while being linked with an enabled detection signal of the plurality of detectors. A self-refresh cycle can be variably controlled and set to be suitable for the charging capacity of a cell. The detection cell is adapted to the change of the charging capacity of the cell in accordance with a change in temperature.
摘要翻译：本发明涉及用于控制动态随机存取存储器或DRAM的自刷新周期的电路和方法。直接检测电池电压，使得可以可变地控制自刷新周期。检测器各自检测充电到检测单元的电容器中的电压是否下降到或低于参考电压，并输出检测信号。脉冲发生器在与多个检测器的使能检测信号链接的同时产生自刷新脉冲。自刷新周期可以被可变地控制并且设置成适合于电池的充电容量。检测单元根据温度的变化适应电池的充电容量的变化。

64. 发明授权

US06608578B2 Current cell driving circuit in digital-to-analog converter 有权
标题翻译：数模转换器中的电流单元驱动电路
公开(公告)号：US06608578B2
公开(公告)日：2003-08-19
申请号：US10032720
申请日：2001-12-27
申请人： Seung Chul Lee , Jong Kee Kwon , Kwi Dong Kim , Kyung Soo Kim
发明人： Seung Chul Lee , Jong Kee Kwon , Kwi Dong Kim , Kyung Soo Kim
IPC分类号： H03M166
CPC分类号： H03K17/102 , H03K17/04106 , H03M1/742
摘要： The present invention relates to a current cell driving circuit in a digital-to-analog converter. The current cell driving circuit limits the potential of differential control signals to a given potential level by means of a voltage limiter using a parasitic capacitance of a transistor. Therefore, the present invention can effectively limit the potential of differential control signals DP and DN without compromising the power consumption and the circuit area and also can minimize the transfer time.
摘要翻译：本发明涉及数模转换器中的电流单元驱动电路。当前单元驱动电路通过使用晶体管的寄生电容的限压器将差分控制信号的电位限制到给定电位电平。因此，本发明可以有效地限制差分控制信号DP和DN的潜力，而不损害功耗和电路面积，并且还可以最小化传送时间。

65. 发明授权

US08737146B2 Semiconductor memory device having redundancy circuit for repairing defective unit cell 有权
标题翻译：具有用于修复缺陷单元的冗余电路的半导体存储器件
公开(公告)号：US08737146B2
公开(公告)日：2014-05-27
申请号：US12649855
申请日：2009-12-30
申请人： Kwi-Dong Kim , Ki-Chang Kwean
发明人： Kwi-Dong Kim , Ki-Chang Kwean
IPC分类号： G11C7/00
CPC分类号： G11C17/16 , G11C17/18
摘要： A semiconductor memory device includes a first bank including a plurality of cell matrices a second bank including a plurality of cell matrices and a shared-fuse set, which is shared by the first and second banks, configured to output a defect indication signal when the first bank or the second bank is enabled and a defective cell matrix is included in the enabled bank.
摘要翻译：一种半导体存储器件，包括：第一存储体，包括多个单元阵列，包括由第一和第二存储体共享的多个单元阵列和共享熔丝组的第二存储体，被配置为当第一和第二存储体中的第一存储单元输出缺陷指示信号时，银行或第二银行被启用，并且有缺陷的单元矩阵被包括在启用银行中。

66. 发明授权

US08477521B2 Fuse circuit and memory device including the same 有权
标题翻译：保险丝电路和包括其的存储器件
公开(公告)号：US08477521B2
公开(公告)日：2013-07-02
申请号：US12981290
申请日：2010-12-29
申请人： Kwi-Dong Kim , Jun-Gi Choi
发明人： Kwi-Dong Kim , Jun-Gi Choi
IPC分类号： G11C17/00 , G11C7/00 , G11C17/18 , G11C8/00
CPC分类号： G11C17/165 , G11C17/18 , G11C29/787
摘要： A fuse circuit includes a plurality of fuse cells, an amplification unit, and a plurality of registers. The amplification unit is configured to sequentially amplify data stored in the fuse cells. The registers are configured to sequentially store data amplified by the amplification unit.
摘要翻译：熔丝电路包括多个熔丝单元，放大单元和多个寄存器。放大单元被配置为顺序放大存储在熔丝单元中的数据。寄存器被配置为顺序地存储由放大单元放大的数据。

67. 发明授权

US08407538B2 Semiconductor package 有权
标题翻译：半导体封装
公开(公告)号：US08407538B2
公开(公告)日：2013-03-26
申请号：US12981628
申请日：2010-12-30
申请人： Tae-Hyoung Huh , Kwi-Dong Kim
发明人： Tae-Hyoung Huh , Kwi-Dong Kim
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C5/025 , G06F11/1008 , G11C2029/0411 , H01L25/18 , H01L2224/16227 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/15192 , H01L2924/15311
摘要： A semiconductor package includes a memory controller chip, a plurality of first memory chips configured to store normal data, a second memory chip configured to store error information for correcting or detecting error of the normal data, and an interface unit configured to interface the memory controller chip, the plurality of first memory chips, and the second memory chip.
摘要翻译：半导体封装包括存储器控制器芯片，被配置为存储正常数据的多个第一存储器芯片，配置为存储用于校正或检测正常数据的错误的错误信息的第二存储器芯片，以及配置为将存储器控制器芯片，多个第一存储器芯片和第二存储器芯片。

68. 发明授权

US08274317B2 Phase-locked loop circuit comprising voltage-controlled oscillator having variable gain 失效
标题翻译：锁相环电路包括具有可变增益的压控振荡器
公开(公告)号：US08274317B2
公开(公告)日：2012-09-25
申请号：US12882132
申请日：2010-09-14
申请人： Sang Hyun Cho , Hui Dong Lee , Kwi Dong Kim , Jong Kee Kwon , Seung Tak Ryu
发明人： Sang Hyun Cho , Hui Dong Lee , Kwi Dong Kim , Jong Kee Kwon , Seung Tak Ryu
IPC分类号： H03L7/06
CPC分类号： H03L7/0995 , H03L7/099 , H03L2207/06
摘要： A phase-locked loop (PLL) circuit including a voltage-controlled oscillator (VCO) with a variable gain is provided. A phase frequency detector (PFD) detects a phase difference between a reference signal and a PLL feedback signal. A charge pump and a loop filter sequentially process an output signal of the PFD. A VCO has different gains according to a mode transition. A control voltage applied to the VCO is selected from an output signal of the loop filter and an additional control signal according to the mode transition.
摘要翻译：提供了包括具有可变增益的压控振荡器（VCO）的锁相环（PLL）电路。相位频率检测器（PFD）检测参考信号和PLL反馈信号之间的相位差。电荷泵和环路滤波器依次处理PFD的输出信号。根据模式转换，VCO具有不同的增益。根据模式转换，从环路滤波器的输出信号和附加控制信号中选择施加到VCO的控制电压。

69. 发明申请

US20120092947A1 FUSE CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME 有权
标题翻译：保险丝电路和包括其的存储器件
公开(公告)号：US20120092947A1
公开(公告)日：2012-04-19
申请号：US12981290
申请日：2010-12-29
申请人： Kwi-Dong KIM , Jun-Gi CHOI
发明人： Kwi-Dong KIM , Jun-Gi CHOI
IPC分类号： G11C17/16
CPC分类号： G11C17/165 , G11C17/18 , G11C29/787
摘要： A fuse circuit includes a plurality of fuse cells, an amplification unit, and a plurality of registers. The amplification unit is configured to sequentially amplify data stored in the fuse cells. The registers are configured to sequentially store data amplified by the amplification unit.
摘要翻译：熔丝电路包括多个熔丝单元，放大单元和多个寄存器。放大单元被配置为顺序放大存储在熔丝单元中的数据。寄存器被配置为顺序地存储由放大单元放大的数据。

70. 发明申请

US20120033511A1 CONTROL CIRCUIT OF READ OPERATION FOR SEMICONDUCTOR MEMORY APPARATUS 有权
标题翻译：半导体存储器的读操作控制电路
公开(公告)号：US20120033511A1
公开(公告)日：2012-02-09
申请号：US13276480
申请日：2011-10-19
申请人： Kwi Dong KIM
发明人： Kwi Dong KIM
IPC分类号： G11C7/22
CPC分类号： G11C7/1039 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C7/22 , G11C7/222
摘要： A control circuit for a read operation of a SERDES (SERializer and DESeriallizer) type semiconductor memory apparatus is disclosed that includes a first line driver configured to output a portion of a output signals from sense amplifier according to a first delay signal; a second line driver configured to output a rest of the output signals from the sense amplifier according to a second delay signal; and a first delay unit configured to output a second delay signal synchronized with a clock to the second line driver.
摘要翻译：公开了一种用于SERDES（串联器和解调器）型半导体存储器件的读取操作的控制电路，其包括：第一线驱动器，被配置为根据第一延迟信号输出来自读出放大器的输出信号的一部分; 第二线驱动器，被配置为根据第二延迟信号从读出放大器输出剩余的输出信号; 以及第一延迟单元，被配置为将与时钟同步的第二延迟信号输出到第二线路驱动器。

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