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61. 发明授权

US06727659B2 Apparatus and method for driving plasma display panels 失效
标题翻译：用于驱动等离子体显示面板的装置和方法
公开(公告)号：US06727659B2
公开(公告)日：2004-04-27
申请号：US10431162
申请日：2003-05-06
申请人： Jae-Yeol Kim , Jin-Sung Kim , Jun-Hyung Kim , Kazuhiro Ito , Myeong-Seob So
发明人： Jae-Yeol Kim , Jin-Sung Kim , Jun-Hyung Kim , Kazuhiro Ito , Myeong-Seob So
IPC分类号： G09G310
CPC分类号： G09G3/2965 , G09G3/293 , G09G2310/066
摘要： An apparatus for driving a plasma display panel that includes first and second signal lines for supplying first and second voltages, respectively, and first and second inductors coupled to one terminal of a panel capacitor. A first current path is formed from the panel capacitor to the second signal line via the second inductor to drop the voltage of the panel capacitor from the first voltage to the second voltage. A second current path is formed to recover the current flowing to the second inductor towards the first signal line, while the voltage of the panel capacitor is sustained at the second voltage. A third current path is formed from the first signal line to the panel capacitor via the first inductor while the current flowing to the second inductor is recovered, to raise the voltage of the panel capacitor from the second voltage to the first voltage. A fourth current is also formed to recover the current flowing to the first inductor towards the first signal line, while the voltage of the panel capacitor is sustained at the first voltage.
摘要翻译：一种用于驱动等离子体显示面板的装置，其包括用于分别提供第一和第二电压的第一和第二信号线以及耦合到面板电容器的一个端子的第一和第二电感器。经由第二电感器从面板电容器到第二信号线形成第一电流路径，以将面板电容器的电压从第一电压降低到第二电压。形成第二电流路径以恢复流向第二电感器的电流朝向第一信号线，同时面板电容器的电压维持在第二电压。第三电流路径由第一信号线经由第一电感器形成到面板电容器，同时流过第二电感器的电流被恢复，以将面板电容器的电压从第二电压升高到第一电压。还形成第四电流以恢复流向第一电感器的电流朝向第一信号线，同时面板电容器的电压维持在第一电压。

62. 发明授权

US06464794B1 Process chamber used in manufacture of semiconductor device, capable of reducing contamination by particulates 失效
标题翻译：用于制造半导体器件的处理室，能够减少微粒污染
公开(公告)号：US06464794B1
公开(公告)日：2002-10-15
申请号：US09404631
申请日：1999-09-23
申请人： Jeong-hyuck Park , Hee-duk Kim , Jung-hun Cho , Jong-wook Choi , Sung-bum Cho , Young-koo Lee , Jin-sung Kim , Jang-eun Lee , Ju-hyuck Chung , Sun-hoo Park , Jae-hyun Lee , Shin-woo Nam
发明人： Jeong-hyuck Park , Hee-duk Kim , Jung-hun Cho , Jong-wook Choi , Sung-bum Cho , Young-koo Lee , Jin-sung Kim , Jang-eun Lee , Ju-hyuck Chung , Sun-hoo Park , Jae-hyun Lee , Shin-woo Nam
IPC分类号： C23C1600
CPC分类号： H01J37/32431 , C23C16/4583 , C23C16/4585 , C23C16/54 , H01J37/32623 , H01J37/32642 , H01L21/32136 , H01L21/6831 , H01L21/68735 , Y10T117/10
摘要： A process chamber used in the manufacture of a semiconductor device for etching a material layer on a semiconductor wafer includes an electrostatic chuck for holding the semiconductor wafer, and an annular edge ring which surrounds the side of the semiconductor wafer on the electrostatic chuck to prevent the semiconductor wafer from departing from its original position. The annular edge ring has a first side which faces the side of the semiconductor wafer and contacts firmly with the side of the semiconductor wafer.
摘要翻译：用于制造用于蚀刻半导体晶片上的材料层的半导体器件的处理室包括用于保持半导体晶片的静电卡盘和围绕静电卡盘上的半导体晶片侧的环形边缘环，以防止半导体晶片从其原始位置脱离。环形边缘环具有面向半导体晶片的侧面并与半导体晶片的侧面牢固接触的第一侧。

63. 发明授权

US06442103B1 Synchronous SRAM device with late write function 有权
标题翻译：具有迟写功能的同步SRAM器件
公开(公告)号：US06442103B1
公开(公告)日：2002-08-27
申请号：US09963962
申请日：2001-09-26
申请人： Jong-Tack Kwak , Jin-Ho Kwack , Sun-Min Lee , Jin-Sung Kim
发明人： Jong-Tack Kwak , Jin-Ho Kwack , Sun-Min Lee , Jin-Sung Kim
IPC分类号： G11C800
CPC分类号： G11C7/1087 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C2207/2218
摘要： A synchronous memory device includes a late write mode of operation, and includes a memory cell array storing data information. The synchronous memory device comprises a write-in command detector, a data input control signal generator, first and second latch circuits, and a multiplexer. The write-in command detector generates a first flag signal indicating that write-in command is applied to the memory device, and generates a second flag signal indicating that the write-in command is received during successive clock cycles. The data input control signal generator, in response to the first flag signal, sequentially generates data input control signals synchronized with a clock signal. The first latch circuit sequentially latches write-in data from external sources in response to the data input control signals, and the second latch circuit latches data latched in the first latch circuit in response to at least one of the data input control signals. The multiplexer selects one of the first and second latch circuits in response to the second flag signal. The selected outputs of the latch circuits are stored to a memory cell array through the write-in circuit within sufficient setup time parameters.
摘要翻译：同步存储器件包括后期写操作模式，并且包括存储数据信息的存储单元阵列。同步存储装置包括写入命令检测器，数据输入控制信号发生器，第一和第二锁存电路以及多路复用器。写入命令检测器产生指示写入命令被施加到存储器件的第一标志信号，并产生指示在连续时钟周期期间接收写入命令的第二标志信号。数据输入控制信号发生器响应于第一标志信号顺序地产生与时钟信号同步的数据输入控制信号。第一锁存电路响应于数据输入控制信号顺序地锁存来自外部源的写入数据，并且第二锁存电路响应于数据输入控制信号中的至少一个锁存锁存在第一锁存电路中的数据。复用器响应于第二标志信号选择第一和第二锁存电路中的一个。所选择的锁存电路的输出通过写入电路在足够的建立时间参数内存储到存储单元阵列。

64. 发明授权

US06380916B1 Color adjustment circuit for liquid crystal display 有权
标题翻译：液晶显示器色调电路
公开(公告)号：US06380916B1
公开(公告)日：2002-04-30
申请号：US09294849
申请日：1999-04-20
申请人： Jin Sung Kim
发明人： Jin Sung Kim
IPC分类号： G09G336
CPC分类号： G09G3/3607 , G09G3/3611 , G09G2320/0606 , G09G2320/0666
摘要： A color adjustment circuit in LCDs, comprising: an R data adjusting portion for externally receiving an R data of selected bits, which has a predetermined color level, for adjusting the color level of the received R data to a desirable color level and for generating the color level adjusted-R data; a G data adjusting portion for externally receiving a G data of selected bits, which has a predetermined color level, for adjusting the color level of the received G data to a desirable color level and for generating the color level adjusted-G data; and a B data adjusting portion for externally receiving a B data of selected bits, which has a predetermined color level, for adjusting the color level of the received B data to a desirable color level and for generating the color level adjusted-B data.
摘要翻译：一种LCD中的颜色调整电路，包括：R数据调整部分，用于外部接收具有预定色彩级别的所选位的R数据，用于将接收到的R数据的色彩水平调整到期望的色彩水平，并产生色彩调整R数据; G数据调整部分，用于外部接收具有预定颜色级别的所选位的G数据，用于将接收到的G数据的色彩水平调整到期望的色彩水平，并用于产生色度调整的G数据; 以及B数据调整部分，用于从外部接收具有预定色彩级别的所选位的B数据，用于将接收到的B数据的色彩水平调整到期望的色彩水平，并产生色度调整后的B数据。

65. 发明授权

US06279503B1 Chemical vapor deposition apparatus for manufacturing semiconductor devices 有权
标题翻译：用于制造半导体器件的化学气相沉积设备
公开(公告)号：US06279503B1
公开(公告)日：2001-08-28
申请号：US09183599
申请日：1998-10-29
申请人： Baik-soon Choi , Jung-il An , Jin-sung Kim , Jung-ki Kim
发明人： Baik-soon Choi , Jung-il An , Jin-sung Kim , Jung-ki Kim
IPC分类号： C23C1600
CPC分类号： C23C16/4405
摘要： There is provided a method of optimizing recipe of in-situ cleaning process for process chamber after a specific process on semiconductor wafers by using Residual Gas Analyzer Quadrupole Mass Spectrometer (RGA-QMS). According to the present invention, a Chemical Vapor Deposition (CVD) apparatus for manufacturing semiconductor devices comprises: a process chamber; process gas supply line for supplying process gas into the process chamber; a waste-gas exhaust line for removing the waste-gas from the process chamber after process; a supply line for supplying a CiF3 gas into the process chamber; a sampling manifold for sampling the gas inside process chamber by using pressure difference; and RGA-QMS for analyzing the sampling gas, and the optimization of the end points according to gas flow, pressure, and temperature of the cleaning process for the process chamber is achieved through the analysis by above RGA-QMS.
摘要翻译：提供了一种通过使用残留气体分析仪四极质谱仪（RGA-QMS）在半导体晶片上的特定工艺之后优化处理室的原位清洗工艺的方法。根据本发明，用于制造半导体器件的化学气相沉积（CVD）装置包括：处理室; 工艺气体供应管线，用于将处理气体供应到处理室中; 用于从处理室中除去废气的废气排放管线; 用于将CiF3气体供应到处理室中的供应管线; 采样歧管，用于通过使用压力差来对处理室内的气体进行采样; 和用于分析采样气体的RGA-QMS，并通过上述RGA-QMS的分析实现了根据工艺室清洁过程的气体流量，压力和温度对端点进行优化。

66. 发明授权

US6162664A Method for fabricating a surface mounting type semiconductor chip package 有权
标题翻译：制造表面安装型半导体芯片封装的方法
公开(公告)号：US6162664A
公开(公告)日：2000-12-19
申请号：US168886
申请日：1998-10-09
申请人： Jin-Sung Kim
发明人： Jin-Sung Kim
IPC分类号： H01L23/12 , H01L23/13 , H01L23/24 , H01L23/28 , H01L23/31 , H01L23/498 , H05K3/34 , H01L21/50 , H01L21/44
CPC分类号： H01L23/49866 , H01L23/13 , H01L23/24 , H01L23/3121 , H01L23/49816 , H01L24/45 , H01L24/48 , H01L2224/451 , H01L2224/48227 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15174 , H01L2924/15311 , H01L2924/16195 , H01L2924/181 , H05K3/3436 , H05K3/3484 , H05K2201/035 , H05K2201/0367 , H05K2201/09745 , H05K2203/043 , Y02P70/613 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2924/00 , H01L2224/05599 , H01L2224/85399
摘要： A solder structure for a surface mounting type semiconductor chip package, and a method of fabricating the same are disclosed. The surface mounting type semiconductor chip package includes a package body having an interconnection formed therein and a semiconductor chip accommodated therein, and a plurality of double layer bumps each attached to the bottom of the package body as an external connection terminal.
摘要翻译：公开了一种用于表面安装型半导体芯片封装的焊料结构及其制造方法。表面安装型半导体芯片封装包括具有形成在其中的互连的封装主体和容纳在其中的半导体芯片，以及多个双层凸块，每个双层凸块均附接到封装主体的底部作为外部连接端子。

67. 发明授权

US6137163A Semiconductor substrate and stackable semiconductor package and fabrication method thereof 失效
标题翻译：半导体衬底和可堆叠半导体封装及其制造方法
公开(公告)号：US6137163A
公开(公告)日：2000-10-24
申请号：US060707
申请日：1998-04-16
申请人： Jo-Han Kim , Jin-Sung Kim
发明人： Jo-Han Kim , Jin-Sung Kim
IPC分类号： H01L23/12 , H01L23/055 , H01L23/24 , H01L23/52 , H01L25/10 , H01L25/11 , H01L25/18 , H01L23/02
CPC分类号： H01L23/055 , H01L23/24 , H01L25/105 , H01L2224/32225 , H01L2224/451 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/1058 , H01L24/45 , H01L24/48 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/1627 , H01L2924/181
摘要： A semiconductor substrate and a stackable semiconductor package and a fabrication method thereof which make it possible to form a highly-integrated semiconductor module within a limited area. The semiconductor substrate includes a non-conductive substrate main body having a plurality of patterned conductive wires formed therein, a cavity formed in an upper center portion of the substrate main body, and a plurality of via holes which perpendicularly pass through edge portions of the substrate main body. A stackable semiconductor package includes the above-described semiconductor substrate, having a semiconductor device positioned in its cavity with a molding compound, the semiconductor device being electrically connected to the conductive wires formed in the semiconductor substrate. Plural stackable semiconductor packages may be stacked such that the via holes are aligned, and a conductive material such as solder can be placed in the via holes to ensure electrical connection. Additionally, conductive external terminals may be positioned on upper and lower surfaces of the substrate main body of the upper and lower stackable semiconductor packages.
摘要翻译：一种半导体衬底和可堆叠半导体封装及其制造方法，其可以在有限的区域内形成高度集成的半导体模块。半导体衬底包括：非导电衬底主体，其具有形成在其中的多个图案化导电线，形成在衬底主体的上中心部分中的空腔;以及多个通孔，其垂直地穿过衬底的边缘部分主体。可堆叠的半导体封装包括上述半导体衬底，半导体器件具有模制化合物位于其腔中的半导体器件，该半导体器件与形成在半导体衬底中的导线电连接。可以堆叠多个可堆叠的半导体封装，使得通孔对准，并且诸如焊料的导电材料可以放置在通孔中以确保电连接。此外，导电外部端子可以位于上部和下部可堆叠半导体封装的基板主体的上表面和下表面上。

68. 发明授权

US5877549A UFBGA package equipped with interface assembly including a photosoluble layer 失效
标题翻译： UFBGA封装配有包含光敏层的接口组件
公开(公告)号：US5877549A
公开(公告)日：1999-03-02
申请号：US581956
申请日：1996-01-02
申请人： Jin Sung Kim
发明人： Jin Sung Kim
IPC分类号： H01L23/12 , H01L21/60 , H01L23/04 , H01L23/31 , H01L23/498 , H05K3/32 , H01L23/48
CPC分类号： H01L23/3128 , H01L23/49816 , H05K3/323 , H01L2224/451 , H01L2224/48091 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/07811 , H01L2924/15311 , H01L2924/181 , H01L2924/3011 , H05K2201/10719 , H05K2203/095
摘要： An improved UFBGA package equipped with an interface assembly having external electrode protrusions, an anisotropic conductive film, and a photosoluble film, which includes an interface assembly provided at the lower portion of the substrate.
摘要翻译：一种改进的UFBGA封装，其配备有具有外部电极突起的接口组件，各向异性导电膜和可光敏膜，其包括设置在基板的下部的界面组件。

69. 发明授权

US5815253A Method and apparatus for estimating performance of gas tube 失效
标题翻译：用于估计气管性能的方法和装置
公开(公告)号：US5815253A
公开(公告)日：1998-09-29
申请号：US760511
申请日：1996-12-05
申请人： Jin-Sung Kim , Taek-Jin Lim , Gui-Jin Kim
发明人： Jin-Sung Kim , Taek-Jin Lim , Gui-Jin Kim
IPC分类号： G01N23/225 , F16L55/00 , F17D5/00 , G01N21/88 , G01N21/93 , G01N21/954 , G01N23/227 , G01N37/00 , G01Q60/24
CPC分类号： G01N21/88
摘要： Method and apparatus for estimating the performance of a gas tube. The method comprising the steps of: (a) preparing a sample tube to be analyzed and cutting the sample tube in a desired size and shape; (b) examining distribution of defects and surface condition of the cut sample tube with an optical microscope; (c) analyzing structure and composition of surface defects which can not be measured in the step (b), to determine type and composition of the surface defects and shape of a surface grain; (d) analyzing structure of an inner surface-treated layer of the sample tube along the thickness thereof; and (e) synthetically analyzing data for defect density and surface roughness, which are numerically expressed through the steps (a) to (d), to define a reference data which can be used in a semiconductor manufacturing process.
摘要翻译：用于估计气体管的性能的方法和装置。该方法包括以下步骤：（a）准备要分析的样品管并以期望的尺寸和形状切割样品管; （b）用光学显微镜检查切割的样品管的缺陷和表面状况的分布; （c）分析在步骤（b）中不能测量的表面缺陷的结构和组成，以确定表面缺陷的形式和组成以及表面颗粒的形状; （d）沿其厚度分析样品管的内表面处理层的结构; 和（e）综合分析通过步骤（a）至（d）数值表示的缺陷密度和表面粗糙度的数据，以定义可用于半导体制造工艺的参考数据。

70. 发明授权

US5729050A Semiconductor package substrate and ball grid array (BGA) semiconductor package using same 失效
标题翻译：半导体封装衬底和球栅阵列（BGA）半导体封装使用相同
公开(公告)号：US5729050A
公开(公告)日：1998-03-17
申请号：US751672
申请日：1996-11-18
申请人： Jin Sung Kim
发明人： Jin Sung Kim
IPC分类号： H01L23/28 , H01L23/12 , H01L23/31 , H01L23/50 , H01L23/52
CPC分类号： H01L23/3128 , H01L2224/32225 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/8592 , H01L2224/92247 , H01L24/45 , H01L24/48 , H01L24/73 , H01L2924/01077 , H01L2924/01078 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/181
摘要： A semiconductor package substrate and a ball grid array (BGA) semiconductor package using the same include a cavity formed in the substrate, anti-cracking bumpers on the inner substrate surface adjacent to the cavity and a plurality of holes and recesses in the substrate, whereby delamination and cracking which may occur during the credibility checkup can be prevented, thereby improving the package reliability.
摘要翻译：半导体封装基板和使用该半导体封装基板的球栅阵列（BGA）半导体封装包括形成在基板中的空腔，与该空腔相邻的内基板表面上的抗裂纹缓冲器和基板中的多个孔和凹部，由此可以防止在可信度检查期间发生的分层和破裂，从而提高包装可靠性。

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