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61. 发明申请

US20090309099A1 DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：显示装置及其制造方法
公开(公告)号：US20090309099A1
公开(公告)日：2009-12-17
申请号：US12268725
申请日：2008-11-11
申请人： Jong-In Kim , Jang-Soo Kim , Young-Wook Lee
发明人： Jong-In Kim , Jang-Soo Kim , Young-Wook Lee
IPC分类号： H01L27/08 , H01L21/77
CPC分类号： H01L27/12 , G02F1/136213 , G02F1/136227 , G02F1/136286 , G02F1/1368 , H01L27/124 , H01L27/1248 , H01L27/1288
摘要： The present invention relates to a display device and a manufacturing method thereof. The display device includes a substrate, a first conductor disposed on the substrate, a first insulating layer disposed on the first conductor, a second insulating layer disposed on the first insulating layer, a semiconductor disposed on the second insulating layer, and a second conductor disposed on the semiconductor. A thickness of the first insulating layer is greater than a thickness of the first conductor, and the first insulating layer includes a first opening exposing the first conductor.
摘要翻译：显示装置及其制造方法技术领域本发明涉及显示装置及其制造方法。显示装置包括基板，设置在基板上的第一导体，设置在第一导体上的第一绝缘层，设置在第一绝缘层上的第二绝缘层，设置在第二绝缘层上的半导体和设置在第二绝缘层上的第二导体在半导体上。第一绝缘层的厚度大于第一导体的厚度，第一绝缘层包括暴露第一导体的第一开口。

62. 发明授权

US07599015B2 Thin film transistor array panel and a method for manufacturing the same 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US07599015B2
公开(公告)日：2009-10-06
申请号：US11487837
申请日：2006-07-17
申请人： Young-Wook Lee , Jang-Soo Kim
发明人： Young-Wook Lee , Jang-Soo Kim
IPC分类号： G02F1/136
CPC分类号： H01L27/124 , G02F1/136209 , G02F1/136286 , G02F1/1365 , G02F1/1368 , G02F2001/134372 , G02F2001/136222 , G02F2001/13629 , H01L27/1248
摘要： A thin film transistor array panel includes a substrate; a plurality of gate lines that are formed on the substrate; a plurality of data lines that intersect the gate lines; a plurality of thin film transistors that are connected to the gate lines and the data lines; a plurality of color filters that are formed on upper parts of the gate lines, the data lines, and the thin film transistors; a common electrode that is formed on the color filters and that includes a transparent conductor; a passivation layer that is formed on an upper part of the common electrode; and a plurality of pixel electrodes that are formed on an upper part of the passivation layer and that are connected to a drain electrode of each of the thin film transistors.
摘要翻译：薄膜晶体管阵列面板包括基板; 形成在所述基板上的多条栅极线; 与栅极线相交的多条数据线; 连接到栅极线和数据线的多个薄膜晶体管; 形成在栅极线，数据线和薄膜晶体管的上部的多个滤色器; 形成在滤色器上并且包括透明导体的公共电极; 钝化层，其形成在所述公共电极的上部; 以及形成在钝化层的上部并且连接到每个薄膜晶体管的漏电极的多个像素电极。

63. 外观设计

USD594723S1 Scissors 有权
公开(公告)号：USD594723S1
公开(公告)日：2009-06-23
申请号：US29326408
申请日：2008-10-17
申请人： Jang Soo Kim
设计人： Jang Soo Kim

64. 发明申请

US20090121228A1 ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：阵列基板及其制造方法
公开(公告)号：US20090121228A1
公开(公告)日：2009-05-14
申请号：US12269748
申请日：2008-11-12
申请人： Jang-Soo Kim , Hong-Long Ning , Bong-Kyun Kim , Hong-Sick Park , Shi-Yul Kim , Chang-Oh Jeong , Sang-Gab Kim , Jae-Hyoung Youn , Woo-Geun Lee , Yang-Ho Bae , Pil-Sang Yun , Jong-Hyun Choung , Sun-Young Hong , Ki-Won Kim , Byeong-Jin Lee , Yopung-Wook Lee , Jong-In Kim , Byeong-Beom Kim , Nam-Seok Suh
发明人： Jang-Soo Kim , Hong-Long Ning , Bong-Kyun Kim , Hong-Sick Park , Shi-Yul Kim , Chang-Oh Jeong , Sang-Gab Kim , Jae-Hyoung Youn , Woo-Geun Lee , Yang-Ho Bae , Pil-Sang Yun , Jong-Hyun Choung , Sun-Young Hong , Ki-Won Kim , Byeong-Jin Lee , Yopung-Wook Lee , Jong-In Kim , Byeong-Beom Kim , Nam-Seok Suh
IPC分类号： H01L29/04 , H01L21/336
CPC分类号： G02F1/13458 , G02F1/136286 , G02F2001/136295 , H01L27/1218 , H01L27/124 , H01L27/1288
摘要： A gate line includes a first seed layer formed on a base substrate and a first metal layer formed on the first seed layer. A first insulation layer is formed on the base substrate. A second insulation layer is formed on the base substrate. Here, a line trench is formed through the second insulation layer in a direction crossing the gate line. A data line includes a second seed layer formed below the line trench and a second metal layer formed in the line trench. A pixel electrode is formed in a pixel area of the base substrate. Therefore, a trench of a predetermined depth is formed using an insulation layer and a metal layer is formed through a plating method, so that a metal line having a sufficient thickness may be formed.
摘要翻译：栅极线包括形成在基底基板上的第一籽晶层和形成在第一籽晶层上的第一金属层。在基底基板上形成第一绝缘层。在基底基板上形成第二绝缘层。这里，在与栅极线交叉的方向上通过第二绝缘层形成线沟槽。数据线包括形成在线沟槽下方的第二晶种层和形成在线沟槽中的第二金属层。像素电极形成在基底基板的像素区域中。因此，使用绝缘层形成预定深度的沟槽，并且通过电镀方法形成金属层，从而可以形成具有足够厚度的金属线。

65. 发明申请

US20080299712A1 MANUFACTURING METHOD OF A THIN FILM TRANSISTOR ARRAY PANEL 审中-公开
标题翻译：薄膜晶体管阵列的制造方法
公开(公告)号：US20080299712A1
公开(公告)日：2008-12-04
申请号：US12192531
申请日：2008-08-15
申请人： Woo-Geun LEE , Hye-Young RYU , Sang-Gab KIM , Jang-Soo KIM
发明人： Woo-Geun LEE , Hye-Young RYU , Sang-Gab KIM , Jang-Soo KIM
IPC分类号： H01L21/336
CPC分类号： H01L27/1288 , H01L21/32134 , H01L21/76838 , H01L27/1214 , H01L29/66765
摘要： A method of manufacturing a thin film transistor array panel includes forming a gate line including a gate electrode, forming a gate insulating layer on the gate line, forming a semiconductor stripe on the gate insulating layer; forming ohmic contacts on the semiconductor stripe, forming a data line including a source electrode and a drain electrode on the ohmic contacts, depositing a passivation layer on the data line and the drain electrode, and forming a pixel electrode connected to the drain electrode. The formation of the data line and the drain electrode, the ohmic contacts, and the semiconductor stripe includes depositing an intrinsic silicon layer, an extrinsic silicon layer, and a conductor layer on the gate insulating layer, forming a photoresist including a second portion corresponding to a channel area between the source electrode and the drain electrode, and a first portion corresponding to a wire area on the data line and the drain electrode, wherein the first portion is thicker than the second portion, etching the conductor layer corresponding to a remaining area except for the wire and the channel area using the photoresist as an etch mask, removing the second portion to expose the conductor layer on the channel areas, etching the intrinsic silicon layer and the extrinsic silicon layer on the remaining area, etching the conductor layer and the extrinsic silicon layer on the channel areas, and removing the first portion.
摘要翻译：制造薄膜晶体管阵列面板的方法包括：形成包括栅电极的栅极线，在栅极线上形成栅绝缘层，在栅绝缘层上形成半导体条; 在半导体条上形成欧姆接触，在欧姆接触上形成包括源电极和漏电极的数据线，在数据线和漏电极上沉积钝化层，并形成连接到漏电极的像素电极。数据线和漏电极，欧姆接触和半导体条纹的形成包括在栅绝缘层上沉积本征硅层，非本征硅层和导体层，形成光致抗蚀剂，其包括对应于源极电极和漏极电极之间的沟道区域，以及对应于数据线和漏极电极的导线区域的第一部分，其中第一部分比第二部分厚，蚀刻对应于剩余区域的导体层除了使用光致抗蚀剂作为蚀刻掩模的导线和沟道区域之外，去除第二部分以暴露沟道区域上的导体层，蚀刻剩余区域上的本征硅层和非本征硅层，蚀刻导体层和在通道区域上的非本征硅层，以及去除第一部分。

66. 发明申请

US20080185589A1 DISPLAY SUBSTRATE HAVING THE SAME AND METHOD OF MANUFACTURING THE DISPLAY SUBSTRATE 有权
标题翻译：具有该显示基板的显示基板和制造显示基板的方法
公开(公告)号：US20080185589A1
公开(公告)日：2008-08-07
申请号：US12027102
申请日：2008-02-06
申请人： Kyoung-Ju Shin , Jang-Soo Kim , Chong-Chul Chai
发明人： Kyoung-Ju Shin , Jang-Soo Kim , Chong-Chul Chai
IPC分类号： H01L29/04 , H01L21/02 , G02F1/136
CPC分类号： G02F1/136213 , G02F2001/136222
摘要： A display substrate includes a thin-film transistor (TFT) layer, a color filter layer and a pixel electrode formed on a substrate. The TFT layer includes a gate line, a data line electrically insulated from the gate line and extending in a direction different from the gate line, a TFT electrically connected to the gate line and the data line, and a storage electrode formed from the same layer as the gate line in each pixel. The color filter layer includes a storage hole extending to a portion of the TFT layer corresponding to the storage electrode. The storage hole has a horizontal cross-sectional area greater than the storage electrode, wherein the horizontal cross-sectional area is measured in a plane parallel to the substrate. The pixel electrode is formed on the color filter layer and in the storage hole to form a storage capacitor with the storage electrode.
摘要翻译：显示基板包括薄膜晶体管（TFT）层，滤色器层和形成在基板上的像素电极。 TFT层包括栅极线，与栅极线电绝缘并沿与栅极线不同的方向延伸的数据线，与栅极线和数据线电连接的TFT，以及由同一层形成的存储电极作为每个像素中的栅极线。滤色器层包括延伸到对应于存储电极的TFT层的一部分的存储孔。存储孔具有大于存储电极的水平横截面积，其中在平行于衬底的平面中测量水平横截面面积。像素电极形成在滤色器层和存储孔中，以与存储电极形成存储电容器。

67. 发明授权

US07371621B2 Thin film transistor array panel and fabrication 有权
标题翻译：薄膜晶体管阵列和制造
公开(公告)号：US07371621B2
公开(公告)日：2008-05-13
申请号：US11486330
申请日：2006-07-12
申请人： Sang-Gab Kim , Woo-Geun Lee , Shi-Yul Kim , Jin-Ho Ju , Jang-Soo Kim , Sang-Woo Whangbo , Min-Seok Oh , Hye-Young Ryu , Hong-Kee Chin
发明人： Sang-Gab Kim , Woo-Geun Lee , Shi-Yul Kim , Jin-Ho Ju , Jang-Soo Kim , Sang-Woo Whangbo , Min-Seok Oh , Hye-Young Ryu , Hong-Kee Chin
IPC分类号： H01L21/00
CPC分类号： H01L27/124 , G02F2001/13629 , H01L29/458
摘要： The present invention provides a manufacturing method of a thin film transistor array panel, which includes forming a gate line on a substrate; forming a gate insulating layer, a semiconductor layer, and an ohmic contact on the gate line; forming a first conducting film including Mo, a second conducting film including Al, and a third conducting film including Mo on the ohmic contact; forming a first photoresist pattern on the third conducting film; etching the first, second, and third conducting films, the ohmic contact, and the semiconductor layer using the first photoresist pattern as a mask; removing the first photoresist pattern by a predetermined thickness to form a second photoresist pattern; etching the first, second, and third conducting films using the second photoresist pattern as a mask to expose a portion of the ohmic contact; and etching the exposed ohmic contact using a Cl-containing gas and a F-containing gas.
摘要翻译：本发明提供一种薄膜晶体管阵列面板的制造方法，其包括在基板上形成栅极线; 在栅极线上形成栅极绝缘层，半导体层和欧姆接触; 形成包括Mo的第一导电膜，包括Al的第二导电膜和在欧姆接触上包含Mo的第三导电膜; 在所述第三导电膜上形成第一光致抗蚀剂图案; 使用第一光致抗蚀剂图案作为掩模蚀刻第一，第二和第三导电膜，欧姆接触和半导体层; 将第一光致抗蚀剂图案去除预定厚度以形成第二光致抗蚀剂图案; 使用第二光致抗蚀剂图案作为掩模蚀刻第一，第二和第三导电膜以暴露欧姆接触的一部分; 并使用含Cl气体和含F气体蚀刻暴露的欧姆接触。

68. 发明申请

US20080042135A1 THIN-FILM TRANSISTOR SUBSTRATE, METHOD OF MANUFACTURING THE SAME AND DISPLAY APPARATUS HAVING THE SAME 有权
标题翻译：薄膜晶体管基板，其制造方法和具有该薄膜晶体管基板的显示装置
公开(公告)号：US20080042135A1
公开(公告)日：2008-02-21
申请号：US11840161
申请日：2007-08-16
申请人： Hye-Young RYU , Jang-Soo Kim , Su-Hyoung Kang
发明人： Hye-Young RYU , Jang-Soo Kim , Su-Hyoung Kang
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： G02F1/136227 , G02F2001/136222 , H01L27/3258
摘要： In a thin-film transistor (TFT) substrate, a gate insulating layer is disposed on a gate electrode electrically connected to a gate line. A semiconductor layer is disposed on the gate insulating layer. A source electrode is electrically connected to a data line that intersects the gate line. A drain electrode faces the source electrode and defines a channel area of a semiconductor layer. An organic layer is disposed on the data line and has a first opening exposing the channel area. An inorganic insulating layer is disposed on the organic layer. A pixel electrode is disposed on the inorganic insulating layer and electrically connected to the drain electrode. The inorganic insulating layer covers the first opening, and thickness of the inorganic insulating layer is substantially uniform.
摘要翻译：在薄膜晶体管（TFT）基板中，栅极绝缘层设置在与栅极线电连接的栅电极上。半导体层设置在栅极绝缘层上。源极电极与与栅极线相交的数据线电连接。漏电极面对源电极并限定半导体层的沟道面积。有机层设置在数据线上，并且具有暴露通道区域的第一开口。无机绝缘层设置在有机层上。像素电极设置在无机绝缘层上并与漏电极电连接。无机绝缘层覆盖第一开口，无机绝缘层的厚度基本均匀。

69. 发明授权

US07289171B2 Thin film transistor array panel for liquid crystal display having pixel electrode 有权
标题翻译：具有像素电极的液晶显示器的薄膜晶体管阵列面板
公开(公告)号：US07289171B2
公开(公告)日：2007-10-30
申请号：US11551450
申请日：2006-10-20
申请人： Dong-Gyu Kim , Hyang-Shik Kong , Jang-Soo Kim
发明人： Dong-Gyu Kim , Hyang-Shik Kong , Jang-Soo Kim
IPC分类号： G02F1/136 , G02F1/1343
CPC分类号： G02F1/136213 , G02F1/1337 , G02F1/133784 , G02F1/134336 , G02F1/136227 , G02F2201/123
摘要： A TFT array panel includes an insulating substrate, a gate line and a storage electrode line formed thereon. The gate line and the storage electrode line are covered with a gate insulating layer, and a semiconductor island is formed on the gate insulating layer. A pair of ohmic contacts are formed on the semiconductor island, and a data line and a drain electrode are formed thereon. The data line and the drain electrode are covered with a passivation layer having a contact hole exposing the drain electrode. A pixel electrode is formed on the passivation layer and connected to the drain electrode through the contact hole. The TFT array panel is covered with an alignment layer rubbed approximately in a direction from the upper left corner to the lower right corner of the TFT array panel or the pixel electrodes. The pixel electrode has approximately a rectangular shape and overlaps the gate line and the data line. The pixel electrode has an expansion located near the upper left corner of the pixel electrode to increase the width of the corresponding overlapping area between the pixel electrode and the gate line and/or the data line.
摘要翻译： TFT阵列面板包括绝缘基板，栅极线和形成在其上的存储电极线。栅极线和存储电极线被栅极绝缘层覆盖，并且在栅极绝缘层上形成半导体岛。在半导体岛上形成一对欧姆接触，在其上形成数据线和漏电极。数据线和漏电极被具有暴露漏电极的接触孔的钝化层覆盖。像素电极形成在钝化层上，并通过接触孔与漏电极连接。 TFT阵列面板被大致沿着从TFT阵列板的左上角到右下角或像素电极的方向摩擦的取向膜覆盖。像素电极具有大致矩形形状并且与栅极线和数据线重叠。像素电极具有位于像素电极的左上角附近的扩展部，以增加像素电极与栅极线和/或数据线之间的对应重叠区域的宽度。

70. 发明申请

US20070249150A1 Method of Forming a Metal Line and Method of Manufacturing a Display Substrate by Using the Same 审中-公开
公开(公告)号：US20070249150A1
公开(公告)日：2007-10-25
申请号：US11669639
申请日：2007-01-31
申请人： Jang-Soo Kim , Sang-Gab Kim
发明人： Jang-Soo Kim , Sang-Gab Kim
IPC分类号： H01L21/44
CPC分类号： H01L27/1288 , H01L27/1214
摘要： In a method of forming a metal line and a method of manufacturing a display substrate, a channel layer and a metal layer are successively formed on a base substrate. A photoresist pattern is formed in a wiring area. The metal layer is etched by using the photoresist pattern to form a metal line. The photoresist pattern is removed by a predetermined thickness to form a residual photoresist pattern on the metal line. The channel layer is etched by using the metal line to form an undercut under the metal line. The protruding portion of the metal line is removed by using the residual photoresist pattern. The protruding portion relatively protrudes by formation of the undercut. Thus, an aperture ratio is increased, an afterimage is prevented, and the display quality is improved.

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