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61. 发明申请

WO2006068984A1 HIGH SPEED DIFFERENTIAL RESISTIVE VOLTAGE DIGITAL-TO-ANALOG CONVERTER 审中-公开
标题翻译：高速差分电阻式数字到模拟转换器
公开(公告)号：WO2006068984A1
公开(公告)日：2006-06-29
申请号：PCT/US2005/045832
申请日：2005-12-16
申请人： EXAR CORPORATION , FOTOUHI, Bahram
发明人： FOTOUHI, Bahram
IPC分类号： H03M1/78
CPC分类号： H03M1/68 , H03M1/76 , H03M1/765
摘要： A differential digital-to-analog voltage converter (VDAC) includes, in part, a resistor, and at least two decoding stages. The resistor is divided into N equal segments each disposed in a different one of N decoders forming a first decoding stage. The resistor segment in each decoder is further divided into M equal segments to provide M tapped nodes. Each decoder of the first decoding stage delivers two of the M tapped voltages to a pair of associated output nodes, and that are complementary with respect to a voltage present at the center of the resistor segment disposed in that decoder. A second decoding stage receives the first and second voltages delivered by each of the N decoders and delivers two of these voltages, that are complementary with respect to a voltage present at the center of the resistor, to a pair of third and fourth output nodes.
摘要翻译：差分数模转换器（VDAC）部分包括电阻器和至少两个解码级。电阻器被分成N个相等的片段，每个N个等分片段分别设置在形成第一解码级的N个解码器的不同的一个中。每个解码器中的电阻器段进一步分成M个相等的段以提供M个抽头节点。第一解码级的每个解码器将两个M抽头电压传送到一对相关联的输出节点，并且相对于存在于设置在该解码器中的电阻器段的中心处的电压互补。第二解码级接收由N个解码器中的每一个传送的第一和第二电压，并且将相对于存在于电阻器中心的电压互补的这些电压中的两个输出到一对第三和第四输出节点。

62. 发明申请

WO2006068915A3 COMMUNICATIONS SYSTEM WITH SCAN TABLE IDENTIFICATION 审中-公开
公开(公告)号：WO2006068915A3
公开(公告)日：2006-06-29
申请号：PCT/US2005/045422
申请日：2005-12-16
申请人： EXAR CORPORATION , HOMER, Russell , DUONG, Khai, Hoan
发明人： HOMER, Russell , DUONG, Khai, Hoan
IPC分类号： H04L12/56 , H04B10/20
摘要： A communications system, comprising a first device including a first scan table and a second device including a second scan table. The first device is configured to select the first scan table and transmit scan table identification. The second device is configured to receive the scan table identification from the first device and select the second scan table based on the received scan table identification.

63. 发明申请

WO2018182638A1 ADAPTIVE BODY BIASING IN CMOS CIRCUITS TO EXTEND THE INPUT COMMON MODE OPERATING RANGE 审中-公开
公开(公告)号：WO2018182638A1
公开(公告)日：2018-10-04
申请号：PCT/US2017/025128
申请日：2017-03-30
申请人： EXAR CORPORATION
发明人： JAYARAJ, Vinit , OJALA, Pekka , TABLER, John
IPC分类号： G05F3/02 , H03F3/45
CPC分类号： H03F3/45206 , G05F3/02 , G05F3/205 , H03F3/45708 , H03F2200/453 , H03F2203/45341 , H03F2203/45418
摘要： In order to get the best of both high and low common mode ranges, an adaptive body biasing method using a pair of replica devices is implemented, Each replica device corresponds to a NMOS (or PMOS) device that constitutes the input pair used in a logic circuit or other type of integrated circuits, This configuration helps to increase the threshold voltage of the device, utilizing body effect, at high input common mode voltage, as desired for NMOS, and at low input common mode voltage, as desired for PMOS. At the same time, this configuration scales the threshold back to normal at low input common mode voltages, thereby countering the negative impact of body effect. In short, the body bias applied to the NMOS (or PMOS) device helps in adapting the threshold voltage to the operating condition.

64. 发明申请

WO2012178192A1 METHOD FOR REMOTE DEVICE PROVISIONING AND INSERTION/EXTRACTION OF OVERHEAD/EOAM DATA FOR VARIOUS PROTOCOLS 审中-公开
标题翻译：用于各种协议的远程设备提供和插入/提取OVERHEAD / EOAM数据的方法
公开(公告)号：WO2012178192A1
公开(公告)日：2012-12-27
申请号：PCT/US2012/044066
申请日：2012-06-25
申请人： EXAR CORPORATION , TZVETANOV, Ilian Sevdalinov , RIDA, Nizar
发明人： TZVETANOV, Ilian Sevdalinov , RIDA, Nizar
IPC分类号： H04L12/24 , H04L12/40 , H04L12/56
CPC分类号： H04L12/4641 , H04J3/047 , H04J2203/0073
摘要： A device demultiplexes an optical signal to produce a number of client streams for client devices. The device produces overhead packets for the client devices. The overhead packets are sent using a packet interface on the device. The overhead packets are sent to the client devices with a Virtual Local Area Network Identification (VLAN ID) portion of the overhead packets identify a client device of the client devices.
摘要翻译：设备对光信号进行多路分解以产生用于客户端设备的多个客户端流。该设备为客户端设备生成开销数据包。使用设备上的数据包接口发送开销数据包。开销数据包被发送到客户端设备，其中开销包的虚拟局域网标识（VLAN ID）部分标识客户端设备的客户端设备。

65. 发明申请

WO2012030483A3 DEJITTER (DESYNCHRONIZE) TECHNIQUE TO SMOOTH GAPPED CLOCK WITH JITTER/WANDER ATTENUATION USING ALL DIGITAL LOGIC 审中-公开
公开(公告)号：WO2012030483A3
公开(公告)日：2012-03-08
申请号：PCT/US2011/046962
申请日：2011-08-08
申请人： EXAR CORPORATION , LAWANGE, Omeshwar Suryakant
发明人： LAWANGE, Omeshwar Suryakant
IPC分类号： H04L7/00
摘要： Digital logic receives a gapped and jittery clock signal with specified frequency and frequency offset allowed by specification and a reference clock signal with same specified frequency and different frequency offset allowed by specification having low jitter. The digital logic adds and/or removes cycles from the reference clock signal over an extended period of time to produce a produced clock signal with low jitter that has a frequency that approaches the frequency of the gapped and jittery clock signal. The produced clock signal being provided as feedback to the digital frequency comparator and also acts as final dejitter smooth clock output with 50% duty cycle.

66. 发明申请

WO2011103353A1 EXTENDABLE N-CHANNEL DIGITAL PULSE-WIDTH/PULSE-FREQUENCY MODULATOR 审中-公开
标题翻译：可扩展的N沟道数字脉冲宽度/脉冲频率调制器
公开(公告)号：WO2011103353A1
公开(公告)日：2011-08-25
申请号：PCT/US2011/025327
申请日：2011-02-17
申请人： Exar Corporation , LUKIC, Zdravko , IOZSEF, Eric , ZHAO, Zhenyu , CHEN, Jingquan
发明人： LUKIC, Zdravko , IOZSEF, Eric , ZHAO, Zhenyu , CHEN, Jingquan
IPC分类号： H03K7/08
CPC分类号： H03K7/08 , H03K7/06
摘要： A multichannel digital pulse width modulator/digital pulse frequency modulator uses a single ring oscillator that is shared by multiple channels. The ring oscillator has taps that can be used for least significant bit (LSB) precision of the generated PWM signal. The ring oscillator also produces a ring clock that is used to synchronize logic in the channels. Since the logic in the channels are synchronized by the ring clock, the channels can each independently produce different frequency PWM (or PFM) signals and still share the same ring oscillator.
摘要翻译：多通道数字脉宽调制器/数字脉冲频率调制器使用由多个通道共享的单个环形振荡器。环形振荡器具有可用于产生的PWM信号的最低有效位（LSB）精度的抽头。环形振荡器还产生一个环形时钟，用于同步通道中的逻辑。由于通道中的逻辑通过环形时钟同步，通道可以各自独立地产生不同频率的PWM（或PFM）信号，并且仍然共享相同的环形振荡器。

67. 发明申请

WO2011103352A1 DIGITAL CONTROL METHOD FOR IMPROVING HEAVY-TO-LIGHT (STEP DOWN) LOAD TRANSIENT RESPONSE OF SWITCH MODE POWER SUPPLIES 审中-公开
标题翻译：用于改善开关模式电源的负载过渡响应的数字控制方法
公开(公告)号：WO2011103352A1
公开(公告)日：2011-08-25
申请号：PCT/US2011/025326
申请日：2011-02-17
申请人： EXAR CORPORATION , PRODIC, Aleksandar , ZHAO, Zhenyu
发明人： PRODIC, Aleksandar , ZHAO, Zhenyu
IPC分类号： G05F1/00
CPC分类号： H02M3/158
摘要： A method for improving heavy-to-light load transient response in low-power switch-mode power supplies is described. It uses a negative voltage input power rail and a digital controller with an extended duty ratio control value to provide faster discharging current slew rate in the switched mode power supplies (SMPS) inductor.
摘要翻译：描述了一种在低功率开关模式电源中改善重轻负载瞬态响应的方法。它使用负电压输入电源轨和具有扩展占空比控制值的数字控制器，以在开关模式电源（SMPS）电感器中提供更快的放电电流转换速率。

68. 发明申请

WO2010033391A1 GRAY CODE CURRENT MODE ANALOG-TO-DIGITAL CONVERTER 审中-公开
标题翻译：灰色代码电流模式模拟到数字转换器
公开(公告)号：WO2010033391A1
公开(公告)日：2010-03-25
申请号：PCT/US2009/055929
申请日：2009-09-03
申请人： EXAR CORPORATION , RANDLETT, Richard W. , HU, Zonggi
发明人： RANDLETT, Richard W. , HU, Zonggi
IPC分类号： H03M1/12
CPC分类号： H03M1/447 , H03M1/0682 , H03M7/16
摘要： One embodiment of the present invention is a Gray code current-mode analog to digital (ADC) converter using a Gray code current-mode ADC building block. The Gray code current-mode ADC building block can produce a Gray code bit and a current output that is sent to a next Gray code ADC building block. In one embodiment, the Gray code current-mode ADC building block does not use a voltage comparator in a signal path of the current output. In one embodiment, an 8 bit analog-to-digital converter can have a 65ns conversion time and consume only 10mW of power with a single +5.0V supply.
摘要翻译：本发明的一个实施例是使用格雷码电流模式ADC构建块的格雷码电流模式模数（ADC）转换器。格雷码电流模式ADC构建块可以产生一个格雷码位和一个电流输出，发送到下一个格雷码ADC构建块。在一个实施例中，格雷码电流模式ADC构建块在电流输出的信号路径中不使用电压比较器。在一个实施例中，8位模数转换器可以具有65ns的转换时间，并且在单个+ 5.0V电源下仅消耗10mW的功率。

69. 发明申请

WO2009006601A1 PROGRAMMABLE ANALOG-TO-DIGITAL CONVERTER FOR LOW-POWER DC-DC SMPS 审中-公开
标题翻译：用于低功率DC-DC SMPS的可编程模数转换器
公开(公告)号：WO2009006601A1
公开(公告)日：2009-01-08
申请号：PCT/US2008/069216
申请日：2008-07-03
申请人： EXAR CORPORATION , PARAYANDEH, Amir , PRODIC, Aleksandar
发明人： PARAYANDEH, Amir , PRODIC, Aleksandar
IPC分类号： H03M1/66
CPC分类号： H03K7/08 , H02M3/157 , H03M1/502
摘要： A voltage-to-time based windowed analog-to-digital converter (ADC) can have programmable reference voltage, conversion time, and accuracy of voltage regulation. The ADC can be fully implemented on a small silicon area and is suitable for implementation in various integrated digital controllers for high frequency low-power switch mode power supplies (SMPS). The programmable characteristics can be achieved through the utilization of the inherent averaging effect of the delay line or of the other voltage-to-time conversion structures and through the adjustments of delay cells' propagation times or the effective voltage-to-time conversion ratio in alternative structures.
摘要翻译：基于电压 - 时间的窗口模数转换器（ADC）可以具有可编程参考电压，转换时间和电压调节精度。 ADC可以在小型硅片上完全实现，适用于高频低功耗开关电源（SMPS）的各种集成数字控制器。可编程特性可以通过利用延迟线或其他电压 - 时间转换结构的固有平均效应，并通过调整延迟单元的传播时间或有效的电压 - 时间转换比来实现替代结构。

70. 发明申请

WO2006068913A2 COMMUNICATIONS SYSTEM WITH SEGMENTING AND FRAMING OF SEGMENTS 审中-公开
标题翻译：具有分段和框架的通信系统
公开(公告)号：WO2006068913A2
公开(公告)日：2006-06-29
申请号：PCT/US2005/045413
申请日：2005-12-16
申请人： EXAR CORPORATION , HOMER, Russell , DUONG, Khai, Hoan
发明人： HOMER, Russell , DUONG, Khai, Hoan
IPC分类号： H04J3/24
CPC分类号： H04L47/36 , H04L12/427 , H04L47/10 , H04L47/13
摘要： A communications system comprising a segmenting mechanism configured to receive a plurality of payloads and divide each of the received payloads into segments, a framing mechanism configured to insert at least one of the segments from each of the plurality of payloads into a packet, a first interface configured to transmit the packet, and a second interface configured to transmit segment information about the segments in the packet.
摘要翻译：一种通信系统，包括分段机制，其被配置为接收多个有效负载并将所接收的有效载荷分成多个段;帧机制，被配置为将来自所述多个有效载荷中的每一个的所述段中的至少一个插入到分组中;第一接口被配置为发送分组，以及第二接口，被配置为发送关于分组中的分段的分段信息。

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