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51. 发明专利

JP2009071608A Offset cancellation circuit and differential amplifier circuit 审中-公开
标题翻译：偏移消除电路和差分放大器电路
公开(公告)号：JP2009071608A
公开(公告)日：2009-04-02
申请号：JP2007238215
申请日：2007-09-13
申请人： Sumitomo Electric Ind Ltd , 住友電気工業株式会社
发明人： TANAKA KEIJI
IPC分类号： H03F3/34 , H03F1/34 , H03F3/45
CPC分类号： H03F3/45475 , H03F3/45183 , H03F3/45748 , H03F3/45973 , H03F2203/45138 , H03F2203/45212 , H03F2203/45441 , H03F2203/45521 , H03F2203/45588 , H03F2203/45682
摘要： PROBLEM TO BE SOLVED: To provide an offset cancellation circuit reducing the variation of the cutoff frequency by reducing the variation of a mirror capacitance caused by a varied input voltage.
SOLUTION: An offset cancellation circuit 20 includes a feedback differential amplifier 30 and a filter circuit 40. The filter circuit 40 includes: first and second resistors 41, 42 respectively connected between the output terminal of a main differential amplifier 10 and the input terminal of the feedback differential amplifier 30; an operation amplifier 51; third and fourth resistors 52, 53 respectively connected between the input terminal of the feedback differential amplifier 30 and the input terminal of the operation amplifier 51; fifth and sixth resistors 54, 55 connected between the input terminal and the output terminal of the operation amplifier 51; and first and second capacitor elements 56, 57 respectively connected to the input terminal of the feedback differential amplifier 30 and the output terminal of the operation amplifier 51.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种通过减小由变化的输入电压引起的反射镜电容的变化来减小截止频率的变化的偏移消除电路。偏移消除电路20包括反馈差分放大器30和滤波电路40.滤波器电路40包括：分别连接在主差分放大器10的输出端和输入端之间的第一和第二电阻器41,42 反馈差分放大器30的端子; 运算放大器51; 分别连接在反馈差分放大器30的输入端和运算放大器51的输入端之间的第三和第四电阻52,53; 连接在运算放大器51的输入端子和输出端子之间的第五和第六电阻器54,55; 以及分别连接到反馈差分放大器30的输入端子和运算放大器51的输出端子的第一和第二电容器元件56,57。版权所有（C）2009，JPO＆INPIT

52. 发明专利

JP2006238403A Circuit and method for compensating for offset voltage 审中-公开
标题翻译：用于补偿偏置电压的电路和方法
公开(公告)号：JP2006238403A
公开(公告)日：2006-09-07
申请号：JP2005145713
申请日：2005-05-18
申请人： Samsung Electro Mech Co Ltd , 三星電機株式会社
发明人： GONG JUNG CHUL , KWON KYOUNG SOO , HWANG HYEON-SEOK , KIM SANG SUK
IPC分类号： H03F3/34 , H03F1/30 , H03F3/08
CPC分类号： H03F3/45748 , H03F3/087 , H03F3/45291 , H03F3/45896 , H03F3/45973 , H03F2200/447
摘要： PROBLEM TO BE SOLVED: To provide a circuit and method for compensating for a variation in an offset voltage caused by a temperature variation of a circuit (PDIC) for converting light to be used for high-speed and high-capacitance storage technologies equivalent to a magnetic disk into an electric signal.
SOLUTION: In an offset voltage compensation circuit, characteristics of a BJT (bipolar junction transistor) used for an output circuit of a PDIC are varied with variation in surrounding temperature. A second BJT having the same temperature characteristics as the above BJT is prepared to configure a bypass circuit of a current flowing through a current mirror to an output BJT element, thereby compensating for the variation in the offset voltage caused by the temperature variation.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于补偿由用于转换用于高速和高电容存储技术的光的电路（PDIC）的温度变化引起的偏移电压变化的电路和方法相当于将磁盘变成电信号。解决方案：在偏移电压补偿电路中，用于PDIC的输出电路的BJT（双极结型晶体管）的特性随周围温度的变化而变化。准备具有与上述BJT相同的温度特性的第二BJT，以将流过电流镜的电流的旁路电路配置到输出BJT元件，从而补偿由温度变化引起的偏移电压的变化。版权所有（C）2006，JPO＆NCIPI

53. 发明专利

JP2015144427A DCオフセットキャンセル回路有权
标题翻译：直流断开断开电路
公开(公告)号：JP2015144427A
公开(公告)日：2015-08-06
申请号：JP2014241080
申请日：2014-11-28
申请人：パナソニック株式会社
发明人：阿部敬之 , 今村幸司 , 佐藤多俊 , 中村重紀
IPC分类号： H03F3/34
CPC分类号： H03F3/45071 , H03F1/0233 , H03F3/45179 , H03F3/45475 , H03F3/45748 , H03F3/45973 , H03F2200/513 , H03F2203/45101 , H03F2203/45112 , H03F2203/45212
摘要：【課題】差動増幅回路の大信号特性を劣化させることがなく、またカレントリユース型差動増幅回路に用いた場合に当該増幅回路の特性の劣化を生じさせることがないDCオフセットキャンセル回路を提供する。【解決手段】LPF102,103を、それぞれ、差動増幅回路101の出力側に配置して、差動増幅回路101の第1出力端からの出力信号Voutnに含まれる交流成分を除去し、第2出力端からの出力信号Voutpに含まれる交流成分を除去し、交流成分を除去した出力信号Voutnのローパスフィルタ電圧VLPFoutnを比較器104の1つの入力端に出力し、また交流成分を除去した出力信号Voutpのローパスフィルタ電圧VLPFoutpを比較器105の1つの入力端に出力する。【選択図】図1
摘要翻译：要解决的问题：提供一种能够确保差分放大器电路的大信号特性的DC偏移消除电路，并且即使当被施加到电流再使用型差分放大器电路时，能够确保放大器的特性电路。解决方案：LPF102和LPF103分别设置在差分放大器电路101的输出侧，以去除包括在差分放大器电路101的第一输出端的输出信号Voutn中的AC分量，并且去除 AC分量，其包括在来自第二输出端子的输出信号Voutp中。将去除了AC分量的输出信号Voutn的低通滤波器电压VLPFoutn输出到比较器104的一个输入端子; 并且将去除了AC分量的输出信号Voutp的低通滤波器电压VLPFoutp输出到比较器105的一个输入端。

54. 发明专利

JP2012191436A Received signal processing device 有权
标题翻译：接收信号处理装置
公开(公告)号：JP2012191436A
公开(公告)日：2012-10-04
申请号：JP2011053202
申请日：2011-03-10
申请人： Panasonic Corp , パナソニック株式会社
发明人： KOBAYASHI MASASHI , FUJITA TAKU , AKIZUKI TAIJI
IPC分类号： H03F3/34 , H03G3/20 , H04B1/30
CPC分类号： H04L25/06 , H03F1/0277 , H03F3/189 , H03F3/45183 , H03F3/45748 , H03F3/72 , H03F2200/294 , H03F2200/336 , H03F2200/405 , H03F2200/411 , H03F2200/507 , H03F2203/45212 , H03F2203/45352 , H03F2203/45702 , H03F2203/7215 , H03F2203/7221 , H03F2203/7227 , H03F2203/7231 , H03F2203/7236 , H03G3/3068 , H04B1/30
摘要： PROBLEM TO BE SOLVED: To provide a received signal processing device that has a small circuit scale and a low power consumption.SOLUTION: The received signal processing device includes: a mixer section for combining a local oscillation signal with a high frequency received signal to effect frequency conversion; an amplification section including a plurality of variable gain amplifiers in a multistage configuration; a conversion section for converting an analog signal amplified by the amplification section to a digital signal; a switch disposed at the back of each variable gain amplifier; a bypass switch section for setting open/closed a path along which an output of one variable gain amplifier bypasses the later variable gain amplifiers to enter the conversion section; a switch control section for controlling the switch and the bypass switch section such that the output of each variable gain amplifier bypasses the later variable gain amplifiers to enter the conversion section; and a DC offset control section for setting a DC offset compensation value in accordance with a gain set in a variable gain amplifier to be corrected when the received signal bypasses the variable gain amplifier to be corrected and the output of the variable gain amplifier to be corrected bypasses the later variable gain amplifiers to enter the conversion section.
摘要翻译：要解决的问题：提供具有小电路规模和低功耗的接收信号处理装置。解决方案：接收信号处理装置包括：混合器部分，用于将本地振荡信号与高频接收信号组合以实现频率转换; 放大部分，包括多级配置的多个可变增益放大器; 转换部分，用于将由放大部分放大的模拟信号转换为数字信号; 设置在每个可变增益放大器背面的开关; 旁路开关部分，用于设置开路/闭合一个可变增益放大器的输出沿着该路径绕过稍后的可变增益放大器以进入转换部分的路径; 用于控制开关和旁路开关部分的开关控制部分，使得每个可变增益放大器的输出绕过稍后的可变增益放大器进入转换部分; 以及DC偏移控制部分，用于根据在可变增益放大器中设置的增益设置DC偏移补偿值，以在接收到的信号绕过要校正的可变增益放大器时被校正，并且可变增益放大器的输出被校正绕过后面的可变增益放大器进入转换部分。版权所有（C）2013，JPO＆INPIT

55. 发明专利

JP4416728B2 Drive circuit and a control method of the low-voltage differential signal 有权
公开(公告)号：JP4416728B2
公开(公告)日：2010-02-17
申请号：JP2005358124
申请日：2005-12-12
申请人：韓國電子通信研究院Electronics and Telecommunications Research Institute
发明人：クィドンキム , ジョンテキム , チョンキクウォン
IPC分类号： H03F3/45
CPC分类号： H03F3/45748 , H03F2200/513 , H03F2203/45082 , H03F2203/45644

56. 发明专利

JP2004242319A Continuous erasure of low frequency errors in high-speed differential amplifier 审中-公开
公开(公告)号：JP2004242319A
公开(公告)日：2004-08-26
申请号：JP2004028278
申请日：2004-02-04
申请人： Fujitsu Ltd , 富士通株式会社
发明人： JIANG JIAN HONG
IPC分类号： H03F3/45 , H03F3/68
CPC分类号： H03F3/45973 , H03F3/45183 , H03F3/45748 , H03F2203/45652
摘要： PROBLEM TO BE SOLVED: To provide a technology with which low frequency errors can be continuously erased in a high-speed differential amplifier. SOLUTION: A signal processing module 18 provides high-gain amplification to a received signal while partially or wholly erasing low frequency errors in the received signal. The signal processing module 18 includes multi-stage amplification systems 30A-30E and feedback loops (32, 30F) for erasing low frequency errors. COPYRIGHT: (C)2004,JPO&NCIPI

57. 发明申请

US20180091107A1 VARIABLE GAIN AMPLIFIER, CORRECTION METHOD AND RECEIVING DEVICE 审中-公开
公开(公告)号：US20180091107A1
公开(公告)日：2018-03-29
申请号：US15672637
申请日：2017-08-09
申请人： Renesas Electronics Corporation
发明人： Noriaki MATSUNO , Satoru TOMISAWA
IPC分类号： H03G3/30 , H04B1/62
CPC分类号： H03G3/3063 , H03F3/45076 , H03F3/45179 , H03F3/45475 , H03F3/45748 , H03F3/45973 , H03F2203/45051 , H03F2203/45138 , H03F2203/45528 , H03F2203/45588 , H03F2203/45591 , H03G1/0088 , H03M1/0612 , H03M1/183 , H04B1/62
摘要： To provide a variable gain amplifier capable of correcting a DC offset voltage through simpler control even when a gain thereof is changed. A differential output type variable gain amplifier is equipped with a first voltage correction unit coupled to a preceding stage of a variable gain amplifier circuit and for outputting a first correction voltage to correct a potential difference generated between a first conductor provided with a first input resistor and a second conductor provided with a second input resistor, and a second voltage correction unit coupled to a subsequent stage of the variable gain amplifier circuit and for correcting a differential output. A control unit is configured to control the first correction voltage and a correction amount of a potential difference by the second voltage correction unit and thereby attenuate a DC offset voltage included in the differential output.

58. 发明授权

US09503039B2 Trimming method for current sense amplifiers 有权
标题翻译：电流检测放大器的微调方法
公开(公告)号：US09503039B2
公开(公告)日：2016-11-22
申请号：US14967529
申请日：2015-12-14
申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
发明人： Razvan Puscasu , Cornel D. Stanescu , Laurentiu O. Creosteanu , Pavel Brinzoi
IPC分类号： H03F3/45 , H03F3/21 , H03F1/52 , H03F1/02
CPC分类号： H03F3/45748 , G01R1/203 , G01R19/0092 , H03F1/0205 , H03F1/523 , H03F3/211 , H03F3/45 , H03F3/45179 , H03F3/45273 , H03F3/45381 , H03F3/45479 , H03F2200/261 , H03F2200/444 , H03F2200/462 , H03F2203/45116 , H03F2203/45118 , H03F2203/45528 , H03F2203/45571 , H03F2203/45594 , H03F2203/45674
摘要： A method for adjusting common mode rejection ratio (CMRR) and gain error of a current sense (CS) amplifier, comprising: measuring a first referred to input (RTI) offset voltage while presenting a given common mode (CM) input voltage; adding a first trim resistor of a plurality of selectable trim resistors within an adjustable feedback resistor chain to a feedback electrical path; measuring a second RTI offset voltage while presenting the given CM input voltage; estimating, based upon the first and second RTI offset voltages, a third RTI offset voltage value that would result by adding a second trim resistor of the plurality of selectable trim resistors to the feedback electrical path; using the first, second and third RTI offset voltage values to identify the combination of selectable trim resistors that achieves an RTI offset voltage closest to zero volts; and adding the identified selectable trim resistors to the feedback electrical path.
摘要翻译：一种用于调节电流检测（CS）放大器的共模抑制比（CMRR）和增益误差的方法，包括：在呈现给定共模（CM）输入电压的同时测量第一参考输入（RTI）偏移电压; 将多个可选修整电阻器的第一微调电阻器添加到可调反馈电阻器链中到反馈电路径; 在呈现给定CM输入电压的同时测量第二RTI偏移电压; 基于所述第一和第二RTI偏移电压估计将通过将所述多个可选修整电阻器的第二调整电阻器添加到所述反馈电路径而产生的第三RTI偏移电压值; 使用第一，第二和第三RTI偏移电压值来识别实现最接近零伏的RTI偏移电压的可选择的微调电阻器的组合; 并将所识别的可选修整电阻器添加到反馈电路径。

59. 发明授权

US09496835B2 Current sense amplifer with extended common mode input voltage range 有权
标题翻译：具有扩展共模输入电压范围的电流检测放大器
公开(公告)号：US09496835B2
公开(公告)日：2016-11-15
申请号：US14668809
申请日：2015-03-25
申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
发明人： Laurentiu O. Creosteanu , Razvan Puscasu , Pavel Brinzoi , Nicusor Bortun
IPC分类号： H03F3/45 , H03F3/21 , H03F1/52 , H03F1/02
CPC分类号： H03F3/45748 , G01R1/203 , G01R19/0092 , H03F1/0205 , H03F1/523 , H03F3/211 , H03F3/45 , H03F3/45179 , H03F3/45273 , H03F3/45381 , H03F3/45479 , H03F2200/261 , H03F2200/444 , H03F2200/462 , H03F2203/45116 , H03F2203/45118 , H03F2203/45528 , H03F2203/45571 , H03F2203/45594 , H03F2203/45674
摘要： Current sense amplifiers with extended input common mode (CM) voltage range, including an extended CM input voltage amplifier that includes a low voltage (LV) p-type metal oxide semiconductor (PMOS) input module coupled to a positive supply rail, wherein said supply rail provides a voltage that is the maximum between a positive input signal (IN+) applied to the amplifier and an internal power supply voltage. The amplifier further includes a voltage regulator coupled to the supply rail that generates a decreased voltage level relative to the supply rail voltage that is provided to the LV PMOS input module via a high voltage ground (HV_GND) line. At least part of the LV PMOS input module is powered by a voltage difference between the positive supply rail and the HV_GND line. The voltage regulator maintains said voltage difference within an operating range of LV devices within the LV PMOS input module.
摘要翻译：具有扩展输入共模（CM）电压范围的电流检测放大器，包括扩展CM输入电压放大器，其包括耦合到正电源轨的低电压（LV）p型金属氧化物半导体（PMOS）输入模块，其中所述电源轨道提供在施加到放大器的正输入信号（IN +）和内部电源电压之间的最大值的电压。放大器还包括耦合到电源轨的电压调节器，其相对于经由高压地（HV_GND）线提供给LVPOS输入模块的电源轨电压产生降低的电压电平。至少部分LV PMOS输入模块由正电源轨和HV_GND线之间的电压差供电。电压调节器将所述电压差保持在LV PMOS输入模块内的LV器件的工作范围内。

60. 发明申请

US20160173037A1 TRIMMING METHOD FOR CURRENT SENSE AMPLIFIERS 有权
标题翻译：电流检测放大器的测量方法
公开(公告)号：US20160173037A1
公开(公告)日：2016-06-16
申请号：US14967529
申请日：2015-12-14
申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
发明人： Razvan PUSCASU , Cornel D. STANESCU , Laurentiu O. CREOSTEANU , Pavel BRINZOI
IPC分类号： H03F1/02 , H03F3/45
CPC分类号： H03F3/45748 , G01R1/203 , G01R19/0092 , H03F1/0205 , H03F1/523 , H03F3/211 , H03F3/45 , H03F3/45179 , H03F3/45273 , H03F3/45381 , H03F3/45479 , H03F2200/261 , H03F2200/444 , H03F2200/462 , H03F2203/45116 , H03F2203/45118 , H03F2203/45528 , H03F2203/45571 , H03F2203/45594 , H03F2203/45674
摘要： A method for adjusting common mode rejection ratio (CMRR) and gain error of a current sense (CS) amplifier, comprising: measuring a first referred to input (RTI) offset voltage while presenting a given common mode (CM) input voltage; adding a first trim resistor of a plurality of selectable trim resistors within an adjustable feedback resistor chain to a feedback electrical path; measuring a second RTI offset voltage while presenting the given CM input voltage; estimating, based upon the first and second RTI offset voltages, a third RTI offset voltage value that would result by adding a second trim resistor of the plurality of selectable trim resistors to the feedback electrical path; using the first, second and third RTI offset voltage values to identify the combination of selectable trim resistors that achieves an RTI offset voltage closest to zero volts; and adding the identified selectable trim resistors to the feedback electrical path.
摘要翻译：一种用于调节电流检测（CS）放大器的共模抑制比（CMRR）和增益误差的方法，包括：在呈现给定共模（CM）输入电压的同时测量第一参考输入（RTI）偏移电压; 将多个可选修整电阻器的第一微调电阻器添加到可调反馈电阻器链中到反馈电路径; 在呈现给定CM输入电压的同时测量第二RTI偏移电压; 基于所述第一和第二RTI偏移电压估计将通过将所述多个可选修整电阻器的第二调整电阻器添加到所述反馈电路径而产生的第三RTI偏移电压值; 使用第一，第二和第三RTI偏移电压值来识别实现最接近零伏的RTI偏移电压的可选择的微调电阻器的组合; 并将所识别的可选修整电阻器添加到反馈电路径。

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