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51. 发明申请

WO2002065536A2 RAPID-TEMPERATURE PULSING ANNEAL METHOD AT LOW TEMPERATURE FOR FABRICATING LAYERED SUPERLATTICE MATERIALS AND MAKING ELECTRONIC DEVICES INCLUDING SAME 审中-公开
标题翻译：用于制备层状超薄材料的低温快速压制方法和制造包括其的电子器件
公开(公告)号：WO2002065536A2
公开(公告)日：2002-08-22
申请号：PCT/US2001/045240
申请日：2001-11-29
申请人： SYMETRIX CORPORATION , MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： UCHIYAMA, Kiyoshi , PAZ DE ARAUJO, Carlos, A. , TANAKA, Keisuke
IPC分类号： H01L21/316
CPC分类号： C23C18/1216 , C23C18/1225 , C23C18/1279 , C23C18/1283 , C30B29/68 , C30B33/00 , H01L21/02197 , H01L21/02282 , H01L21/28291 , H01L21/31691 , H01L29/78391
摘要： A liquid precursor for forming a layered superlattice material (124, 226, 610) is applied (324) to an integrated circuit substrate. The precursor coating is annealed in oxygen using a rapid-temperature pulsing anneal ("RPA") technique with a ramp rate of 30°C/second at a hold temperature of 650°C for a holding time of 30 minutes. The RPA technique includes applying a plurality (330, 340) of rapid-temperature heat pulses in sequence.
摘要翻译：用于形成层状超晶格材料（124,226,610）的液体前体（324）施加到集成电路基板上。使用快速温度脉冲退火（“RPA”）技术在650℃的保持温度下以30℃/秒的升温速率在氧气中退火前体涂层，保持时间为30分钟。 RPA技术包括依次应用多个（330,340）的快速热脉冲。

52. 发明申请

WO1998028784A1 INTEGRATED CIRCUIT ELECTRODE STRUCTURE AND PROCESS FOR FABRICATING SAME 审中-公开
标题翻译：集成电路电极结构及其制造方法
公开(公告)号：WO1998028784A1
公开(公告)日：1998-07-02
申请号：PCT/US1997023697
申请日：1997-12-19
申请人： SYMETRIX CORPORATION
发明人： SYMETRIX CORPORATION , CUCHIARO, Joseph, D. , MCMILLAN, Larry, D. , PAZ DE ARAUJO, Carlos, A.
IPC分类号： H01L21/3205
CPC分类号： H01L27/11502 , C23C16/4412 , C23C16/448 , C23C16/45561 , C23C16/4558 , C23C16/46 , C23C16/482 , C23C16/52 , C23C18/1216 , C23C18/1245 , C23C18/1295 , C23C18/14 , H01L21/31691 , H01L28/55 , H01L28/56 , H01L28/60 , H01L28/65
摘要： An electrode (79, 329) for a ferroelectric electronic device (80, 317C) is formed on an SiO2 isolation layer (77, 324) by depositing an adhesion layer (98, 326), such as titanium, between about 25 ANGSTROM and 500 ANGSTROM thick, then a layer (81, 328) of a nobel metal, such as platinum, that is at least 10 times thicker than the adhesion layer. The electrode is then annealed at a temperature higher than the minimum oxide eutectic temperature of the adhesion layer. The electrode is moved into the annealing furnace at a ramp rate such that it reaches its anneal temperature in five minutes or less. The relative thinness of the adhesion layer and the quick ramp up of the anneal causes all the titanium to be tied up in the oxide before it can diffuse through the platinum, and prevents the formation of rutile phases of the titanium and defects such as voids and hillocks in the platinum, which can destabilize the electrode.
摘要翻译：用于铁电电子器件（80,317C）的电极（79,329）通过在约25至500之间沉积诸如钛的粘附层（98,326）而在SiO 2隔离层（77,324）上形成 ANGSTROM厚，然后是比粘合层厚至少10倍的诺贝尔金属（例如铂）的层（81,328）。然后在高于粘附层的最小氧化物共晶温度的温度下退火电极。电极以升高速度移动到退火炉中，使其在5分钟或更短时间内达到其退火温度。粘合层的相对薄度和退火的快速上升使得所有的钛在氧化物中扩散通过铂之前被束缚在其中，并且防止了钛的金红石相的形成和诸如空隙和缺陷的缺陷白金中的小丘，可能会使电极不稳定。

53. 发明申请

WO1998005071A1 METHOD OF FABRICATING AN INTEGRATED CIRCUIT USING SELF-PATTERNED THIN FILMS 审中-公开
标题翻译：使用自制薄膜制作集成电路的方法
公开(公告)号：WO1998005071A1
公开(公告)日：1998-02-05
申请号：PCT/US1997013483
申请日：1997-07-25
申请人： SYMETRIX CORPORATION
发明人： SYMETRIX CORPORATION , UCHIDA, Hiroto , SOYAMA, Nobuyuki , OGI, Katsumi , SCOTT, Michael, C. , CUCHIARO, Joseph, D. , MCMILLAN, Larry, D. , PAZ DE ARAUJO, Carlos, A.
IPC分类号： H01L27/115
CPC分类号： H01L27/11502 , H01L28/55
摘要： A first photosensitive liquid solution is applied to a substrate (21, 105, 125, 155, 188, 255), patterned through exposure to radiation and development, and annealed to form a layered superlattice material (34, 34A, 34B, 34D, 106, 126, 157, 176, 256, 286, 434) that is incorporated into a component (30, 30A, 30B, 30D, 101, 121, 330) of an integrated circuit (50, 60, 64, 70). Fabrication processes are designed to protect the self-patterned material from conventional IC processing and to protect the conventional materials, such as silicon, from elements in the self-patterned layered superlattice material. In one embodiment, a layer of bismuth oxide (158) is formed on SrBi2Ta2O9 (156) and a silicon oxide hole (162) is etched to the bismuth oxide. The bismuth oxide protects the SrBi2Ta2O9 from the etchant, and is reduced by the etchant to bismuth. Any remaining bismuth oxide and much of the bismuth are vaporized in the anneal, and the remaining bismuth is incorporated into the SrBi2Ta2O9. In another embodiment, a transitor (22) on a silicon substrate is covered by an insulating layer (31). A conducting plug (38) passes through the insulating layer to the transistor drain (24). The bottom electrode (32) of a layered superlattice material capacitor (30) directly overlies the plug and contacts the plug. The layered superlattice material completely overlies the transistor. A self-patterned sacrificial layer (40) completely overlies the layered superlattice material. The bottom electrode of the capacitor is completely enclosed by the layered superlattice material, the insulting layer, and the conducting plug.
摘要翻译：将第一感光性液体溶液施加到通过暴露于辐射和显影而图案化的基板（21,105,125,155,188,255），并且退火以形成分层超晶格材料（34,34A，34B，34D，106 ，126，157，176，256，286，434），其被集成到集成电路（50,60,64,70）的组件（30,30A，30B，30D，101,121,330）中。设计制造工艺以保护自组装图案材料免于常规IC处理，并且保护常规材料（例如硅）免受自图形分层超晶格材料中的元素的影响。在一个实施例中，在SrBi 2 Ta 2 O 9（156）上形成氧化铋层（158），氧化铋蚀刻氧化硅孔（162）。氧化铋保护SrBi2Ta2O9与蚀刻剂的相互作用，并被腐蚀剂还原成铋。任何剩余的氧化铋和大部分铋在退火过程中被蒸发，剩余的铋掺入到SrBi2Ta2O9中。在另一个实施例中，硅衬底上的过渡器（22）被绝缘层（31）覆盖。导电插头（38）穿过绝缘层到晶体管漏极（24）。分层超晶格材料电容器（30）的底部电极（32）直接覆盖在插头上并接触插头。分层超晶格材料完全覆盖晶体管。自图案化牺牲层（40）完全覆盖层状超晶格材料。电容器的底部电极被层状超晶格材料，绝缘层和导电插塞完全封闭。

54. 发明申请

WO1997044818A1 METHOD AND APPARATUS FOR MISTED LIQUID SOURCE DEPOSITION OF THIN FILMS WITH INCREASED YIELD 审中-公开
标题翻译：薄膜失效液体沉积的方法与装置
公开(公告)号：WO1997044818A1
公开(公告)日：1997-11-27
申请号：PCT/US1997008248
申请日：1997-05-15
申请人： SYMETRIX CORPORATION
发明人： SYMETRIX CORPORATION , MCMILLAN, Larry, D. , PAZ DE ARAUJO, Carlos, A.
IPC分类号： H01L21/316
CPC分类号： C23C18/14 , B05D1/007 , B05D1/04 , C23C16/45561 , C23C18/1216 , H01L21/31691
摘要： A mist generator (12) produces a mist from a liquid precursor. Energy is added to the mist particles without carbonizing or otherwise breaking down the bonds in the metal compounds and solvent, preferably by charging the mist particles and then electrically accelerating them. The mist is deposited on a substrate (605) having the opposite polarity to the particles. Infrared lamps (38, 40) may also heat the mist particles to a temperature below the temperature at which the compounds and solvent in the liquid precursor decompose.
摘要翻译：雾发生器（12）从液体前体产生雾。能量被添加到雾状颗粒中，而不会碳化或以其他方式分解金属化合物和溶剂中的键，优选通过充电雾颗粒然后电加速它们。雾沉积在具有与颗粒相反的极性的基底（605）上。红外灯（38,40）也可以将雾粒加热到低于液体前体中的化合物和溶剂分解的温度的温度。

55. 发明申请

WO1996034407A1 BOTTOM ELECTRODE STRUCTURE FOR DIELECTRIC CAPACITORS AND METHOD OF MAKING THE SAME 审中-公开
标题翻译：用于介电电容器的底部电极结构及其制造方法
公开(公告)号：WO1996034407A1
公开(公告)日：1996-10-31
申请号：PCT/US1996005867
申请日：1996-04-25
申请人： SYMETRIX CORPORATION , MATSUSHITA ELECTRONICS CORPORATION
发明人： SYMETRIX CORPORATION , MATSUSHITA ELECTRONICS CORPORATION , AZUMA, Masamichi , PAZ DE ARAUJO, Carlos , CUCHIARO, Joseph
IPC分类号： H01L21/3205
CPC分类号： H01L28/60
摘要： An integrated circuit capacitor (20) includes a bottom electrode structure (24) having an adhesion metal portion (34), a noble metal portion (36), and a second noble metal layer (40). A process of manufacture includes annealing the adhesion metal portion (34) and the noble metal portion (36) prior to the deposition of second noble metal layer (40) for purposes of forming barrier region (38). The electrode (24) preferably contacts metal oxide layer (26), which is made of a perovskite or perovskite-like layered superlattice material. A temporary capping layer (59) is formed and removed in manufacture, which serves to increase polarization potential from the device by at least 40 %.
摘要翻译：集成电路电容器（20）包括具有粘附金属部分（34），贵金属部分（36）和第二贵金属层（40）的底部电极结构（24）。制造方法包括为了形成阻挡区域（38）而在沉积第二贵金属层（40）之前退火附着金属部分（34）和贵金属部分（36）。电极（24）优选接触由钙钛矿或类钙钛矿层状超晶格材料制成的金属氧化物层（26）。在制造中形成和移除临时封盖层（59），其用于将器件的极化电位增加至少40％。

56. 发明申请

WO1996029728A1 INTEGRATED CIRCUITS HAVING MIXED LAYERED SUPERLATTICE MATERIALS AND PRECURSOR SOLUTIONS FOR USE IN A PROCESS OF MAKING THE SAME 审中-公开
标题翻译：具有混合层状超导材料的集成电路及其制造方法中使用的前驱体解决方案
公开(公告)号：WO1996029728A1
公开(公告)日：1996-09-26
申请号：PCT/US1996003523
申请日：1996-03-14
申请人： MATSUSHITA ELECTRONICS CORPORATION , SYMETRIX CORPORATION
发明人： MATSUSHITA ELECTRONICS CORPORATION , SYMETRIX CORPORATION , AZUMA, Masamichi , PAZ DE ARAUJO, Carlos, A. , MCMILLAN, Larry, D.
IPC分类号： H01L21/3205
CPC分类号： C23C16/448 , C04B35/62227 , C23C16/45561 , C23C18/1216 , C23C18/1225 , C23C18/1279 , C30B7/00 , C30B7/005 , C30B29/68 , H01L21/314 , H01L21/31691 , H01L27/10805 , H01L27/11502 , H01L28/40 , H01L28/55 , H01L28/56 , H01L28/60
摘要： Metal alkoxycarboxylate-based liquid precursor solutions are used to form electronic devices (100) that include mixed layered superlattice materials (112) of a type having discrete oxygen octahedral layers (124 and 128) collated with a superlattice-generator layer (116). The precursor solutions include a plurality of metal moieties in effective amounts for yielding the layered superlattice materials. These metal moieties are mixed to include an A/B portion capable of forming an A/B layer (124), a perovskite-like AB layer portion capable of forming a perovskite-like AB octahedral layer (128), and a superlattice-generator portion capable of forming the superlattice-generator layer (116). The precursors are deposited in liquid form upon a substrate and annealed to provide the layered superlattice materials.
摘要翻译：使用基于金属烷氧基羧酸盐的液体前体溶液形成电子器件（100），其包括具有与超晶格 - 发生器层（116）对照的离散氧八面体层（124和128）的混合层状超晶格材料（112）。前体溶液包括有效量的用于产生层状超晶格材料的多个金属部分。这些金属部分被混合以包括能够形成A / B层（124）的A / B部分，能形成钙钛矿型AB八面体层（128）的钙钛矿型AB层部分，以及超晶格发生器部分能够形成超晶格 - 发生器层（116）。前体以液体形式沉积在基底上并退火以提供层状超晶格材料。

57. 发明申请

WO1996029726A1 UV RADIATION PROCESS FOR MAKING ELECTRONIC DEVICES HAVING LOW-LEAKAGE-CURRENT AND LOW-POLARIZATION FATIGUE 审中-公开
标题翻译：用于制造具有低漏电流和低极化疲劳的电子器件的紫外线辐射方法
公开(公告)号：WO1996029726A1
公开(公告)日：1996-09-26
申请号：PCT/US1996003521
申请日：1996-03-14
申请人： SYMETRIX CORPORATION , MATSUSHITA ELECTRONICS CORPORATION
发明人： SYMETRIX CORPORATION , MATSUSHITA ELECTRONICS CORPORATION , AZUMA, Masamichi , MCMILLAN, Larry, D. , PAZ DE ARAUJO, Carlos, A. , SCOTT, Michael, C.
IPC分类号： H01L21/3205
CPC分类号： H01L21/31691 , C23C16/4412 , C23C16/448 , C23C16/4486 , C23C16/45561 , C23C16/4558 , C23C16/46 , C23C16/482 , C23C16/52 , C23C18/1216 , C23C18/1225 , C23C18/1279 , C23C18/1283 , C23C18/1295 , C23C18/14 , C30B7/00 , C30B29/68 , H01L27/10805 , H01L27/11502 , H01L28/55 , H01L28/56 , H01L28/60
摘要： A precursor solution (P22) formed of a liquid polyoxyalkylated metal complex in a solvent is applied to a substrate in the formation of a metal oxide thin film (P26). The liquid thin film is baked (P28) in air to a temperature up to 500 DEG C while UV radiation having a wavelength ranging from 180 nm to 300 nm is applied. The thin film can be twice-baked at increasing temperatures while UV radiation is applied at one or both bakings. The film is then annealed (P32) at temperature ranging from about 700 DEG C to 850 DEG C to produce a thin-film solid metal oxide product. Alternatively, the UV radiation may be applied to the liquid precursor, the thin film may be annealed with UV radiation, or combinations of such applications of UV radiation to the precursor, to the thin film before or after baking, and/or UV annealing may be used.
摘要翻译：在溶剂中由液态聚氧化烷基化金属络合物形成的前体溶液（P22）在金属氧化物薄膜（P26）的形成中被施加到基板上。将液体薄膜在空气中烘烤（P28）到高达500℃的温度，同时施加波长范围为180nm至300nm的UV辐射。薄膜可以在增加的温度下进行两次烘烤，同时在一个或两个烘烤处施加UV辐射。然后将膜在约700℃至850℃的温度范围内退火（P32）以产生薄膜固体金属氧化物产物。或者，UV辐射可以施加到液体前体，薄膜可以在紫外线辐射之前或UV辐射的这种应用的组合与前体一起退火到烘烤之前或之后的薄膜，和/或UV退火使用。

58. 发明申请

WO1996027192A1 METHOD AND APPARATUS FOR REDUCED FATIGUE IN FERROELECTRIC MEMORY ELEMENTS 审中-公开
标题翻译：在电磁记忆元件中减少疲劳的方法和装置
公开(公告)号：WO1996027192A1
公开(公告)日：1996-09-06
申请号：PCT/US1996002288
申请日：1996-02-27
申请人： SYMETRIX CORPORATION , OLYMPUS OPTICAL CO., LTD.
发明人： SYMETRIX CORPORATION , OLYMPUS OPTICAL CO., LTD. , MIHARA, Takashi , WATANABE, Hitoshi , YOSHIMORI, Hiroyuki , PAZ DE ARAUJO, Carlos, A. , MCMILLAN, Larry, D.
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G11C11/223 , G11C11/2293
摘要： A method and apparatus for programming ferroelectric memory cells (200, 600) which reduces polarizability fatigue effects of switching polarization of the ferroelectric devices (202) associated with the memory cells such as ferroelectric capacitors (202) and transistors (602). Alteration of the pulse width duty cycle associated with signals used to switch ferroelectric device polarization is shown to reduce polarizability fatigue of the ferroelectric material (608) thereby increasing the useful life of ferroelectric memory cells (200, 600). Methods and apparatus for producing a signal pulse duty cycle in the range 2-30 % is disclosed and shown to improve the useful life of the ferroelectric material (608).
摘要翻译：一种用于编程铁电存储器单元（200,600）的方法和装置，其减小与诸如铁电电容器（202）和晶体管（602）的存储单元相关联的铁电元件（202）的开关极化的极化率疲劳效应。显示与用于切换铁电体器件极化的信号相关联的脉冲宽度占空比的改变，以降低铁电材料（608）的极化率疲劳，从而增加铁电存储器单元（200,600）的使用寿命。公开并示出了用于产生2-30％范围内的信号脉冲占空比的方法和装置，以改善铁电材料（608）的使用寿命。

59. 发明申请

WO1996015537A1 METHOD AND APPARATUS FOR REDUCED FATIGUE IN FERROELECTRIC MEMORY ELEMENTS 审中-公开
标题翻译：在电磁记忆元件中减少疲劳的方法和装置
公开(公告)号：WO1996015537A1
公开(公告)日：1996-05-23
申请号：PCT/US1995014611
申请日：1995-11-07
申请人： SYMETRIX CORPORATION , OLYMPUS OPTICAL CO., LTD.
发明人： SYMETRIX CORPORATION , OLYMPUS OPTICAL CO., LTD. , MIHARA, Takashi , WATANABE, Hitoshi , YOSHIMORI, Hiroyuki , PAZ DE ARAUJO, Carlos, A. , MCMILLAN, Larry, D.
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A method and apparatus for programming ferroelectric memory cells (100, 200) which reduce fatigue effects of switching polarization of the ferroelectric devices associated with the memory cells such as ferroelectric capacitors (102, 202) and transistors (1002). Alteration of the rise and fall times associated with signals used to switch ferroelectric device polarization reduces fatigue of the ferroelectric material thereby increasing the useful life of ferroelectric memory cells. Slowing the rise and fall times as well as the rate of signal level rise and fall, (signal shape), reduces fatigue effects of switching polarization of ferroelectric devices. Methods and apparatus for producing a triangular ("sawtooth") signal waveform (322), a Gaussian signal waveform (422), and a waveform (522) having exponential rise anf fall times are disclosed.
摘要翻译：一种用于编程铁电存储器单元（100,200）的方法和装置，其减少与诸如铁电电容器（102,202）和晶体管（1002）之类的存储单元相关联的铁电元件的开关极化的疲劳效应。与用于切换铁电体器件极化的信号相关联的上升和下降时间的改变降低了铁电材料的疲劳，从而增加了铁电存储器单元的使用寿命。降低上升和下降时间以及信号电平上升和下降的速率（信号形状）可以降低铁电元件开关极化的疲劳效应。公开了用于产生具有指数上升和下降时间的三角形（“锯齿”）信号波形（322），高斯信号波形（422）和波形（522）的方法和装置。

60. 发明申请

WO1995027982A1 NON-VOLATILE MEMORY 审中-公开
标题翻译：非易失性存储器
公开(公告)号：WO1995027982A1
公开(公告)日：1995-10-19
申请号：PCT/US1995003758
申请日：1995-03-30
申请人： SYMETRIX CORPORATION , OLYMPUS OPTICAL CO., LTD
发明人： SYMETRIX CORPORATION , OLYMPUS OPTICAL CO., LTD , MCMILLAN, Larry, D. , MIHARA, Takashi , YOSHIMORI, Hiroyuki , GREGORY, John, W. , PAZ DE ARAUJO, Carlos, A.
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G11C11/223
摘要： An integrated memory unit (12, 600) includes a capacitor (30, 30A), a transistor (32, 32A), and saturation means (29, 25, 14, 62, 43, 15, 61; 71A, 72A) for polarizing the ferroelectric material (50, 74) to saturation with a voltage of less than 10 volts. One electrode (47, 49A) of the capacitor and the transistor gate (33, 33A) are the same conductive member. The other electrode may be formed by extensions (71A, 72A) of the transistor source (71) and drain (77) underlying the gate (33A). The capacitor (230, 30A) has a capacitance Cf, and an area Af, and the transistor (232, 32A) forms a gate capacitor (233, 255, 266) having an area Ag and a gate capacitance Cg, a gate overlap b, and a channel depth a. The ferroelectric material (250, 74) has a dielectric constant ELEMENT f and the gate insulator (268, 86) has a dielectric constant ELEMENT g. The memory unit has the parametric relationships: Cf /= 2a, and ELEMENT g >/= ELEMENT f/8.
摘要翻译：集成存储器单元（12,600）包括电容器（30,30A），晶体管（32,32A）和用于偏振的饱和装置（29,25,14,62,43,15,61,71A，72A）铁电材料（50,74）以小于10伏特的电压饱和。电容器和晶体管栅极（33,33A）的一个电极（47,49A）是相同的导电构件。另一个电极可以由晶体管源极（71）的延伸部（71A，72A）和栅极（33A）下方的漏极（77）形成。电容器（230,30A）具有电容Cf和区域Af，并且晶体管（232,32A）形成具有面积Ag和栅极电容Cg的栅极电容器（233,255,266），栅极重叠b ，以及频道深度a。铁电材料（250,74）具有介电常数ELEMENT f，并且栅极绝缘体（268,86）具有介电常数ELEMENT g。存储单元具有参数关系：Cf <5×Cg，Af / = 2a和ELEMENT g> / = ELEMENT f / 8。

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