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1. 发明申请

WO1994010704A1 INTEGRATED CIRCUIT WITH LAYERED SUPERLATTICE MATERIAL AND METHOD OF FABRICATING SAME 审中-公开
标题翻译：具有层状超导材料的集成电路及其制造方法
公开(公告)号：WO1994010704A1
公开(公告)日：1994-05-11
申请号：PCT/US1993010127
申请日：1993-10-21
申请人： SYMETRIX CORPORATION , OLYMPUS OPTICAL CO., LTD.
发明人： SYMETRIX CORPORATION , OLYMPUS OPTICAL CO., LTD. , YOSHIMORI, Hiroyuki , WATANABE, Hitoshi , PAZ DE ARUAJO, Carlos, A. , HIRAIDE, Shuzo , McMILLAN, Larry, D. , MIHARA, Takashi
IPC分类号： H01L27/115
CPC分类号： H01L27/11502 , C23C16/45561 , C30B7/00 , C30B7/005 , C30B29/68 , H01L21/31691 , H01L27/10805 , H01L28/55 , H01L28/56 , H01L28/60
摘要： A method of fabricating a layered superlattice DRAM (100) compatible with conventional silicon CMOS technology. A MOSFET (72) is formed on a silicon substrate (71). A thick layer (77D) of BPSG followed by a thin SOG layer (77E) overlies the MOSFET (72). A capacitor (80) is formed by depositing a layer (81) of platinum, annealing, depositing an intermediate layer (84) comprising a layered superlattice material, annealing, depositing a second layer (84) of platinum, then patterning the capacitor (80). Another SOG layer (86) is deposited, contact holes (106, 107) to the MOSFET (72) and capacitor (80) are partially opened, the SOG (86) is annealed, the contact holes (106, 107) are completely opened, and a Pt/Ti/PtSi wiring layer (88, 288) is deposited.
摘要翻译：一种制造与常规硅CMOS技术兼容的分层超晶格DRAM（100）的方法。在硅衬底（71）上形成MOSFET（72）。 BPSG的厚层（77D）之后是薄的SOG层（77E）覆盖在MOSFET（72）上。通过沉积铂的层（81），退火，沉积包括层状超晶格材料的中间层（84），退火，沉积铂的第二层（84），然后对电容器（80）进行构图，形成电容器（80））。沉积另一个SOG层（86），接触孔（106,107）到MOSFET（72）和电容器（80）被部分打开，SOG（86）退火，接触孔（106,107）被完全打开，并沉积Pt / Ti / PtSi布线层（88,288）。

2. 发明申请

WO1996030938A2 PROCESS FOR FABRICATING LAYERED SUPERLATTICE MATERIALS AND MAKING ELECTRONIC DEVICES INCLUDING SAME 审中-公开
标题翻译：制造层状超导材料和制造包括其的电子器件的方法
公开(公告)号：WO1996030938A2
公开(公告)日：1996-10-03
申请号：PCT/US1996003367
申请日：1996-03-12
申请人： SYMETRIX CORPORATION , OLYMPUS OPTICAL CO., LTD.
发明人： SYMETRIX CORPORATION , OLYMPUS OPTICAL CO., LTD. , YOSHIMORI, Hiroyuki , PAZ DE ARAUJO, Carlos, A. , ITO, Takeshi , SCOTT, Michael, C. , MCMILLAN, Larry, D.
IPC分类号： H01L21/3205
CPC分类号： C23C18/1216 , B05D1/00 , B05D1/60 , B05D3/0493 , C23C16/4412 , C23C16/4486 , C23C16/45561 , C23C16/4558 , C23C16/46 , C23C16/482 , C23C16/52 , C23C18/1279 , C23C18/1283 , C23C18/1295 , C23C26/02 , C30B7/00 , C30B7/005 , C30B29/68 , H01C7/1013 , H01L21/314 , H01L21/31691 , H01L27/10805 , H01L27/11502 , H01L28/55 , H01L28/56 , H01L28/60 , H01L41/257 , H01L41/318 , H05K3/105
摘要： A liquid precursor containing a metal is applied to a substrate, RTP baked, and annealed to form a layered superlattice material. Special polyoxyalkylated precursor solutions are designed to optimize polarizability of the corresponding metal oxide materials by adding dopants including stoichiometric excess amounts of bismuth and tantalum. The RTP baking process is especially beneficial in optimizing the polarizability of the resultant metal oxide.
摘要翻译：将含有金属的液体前体施加到基底上，进行RTP烘烤并退火以形成层状超晶格材料。设计特殊的聚氧化烷基化前体溶液通过添加包括化学计量过量的铋和钽的掺杂剂来优化相应的金属氧化物材料的极化率。 RTP烘焙过程对于优化所得金属氧化物的极化率是特别有利的。

3. 发明申请

WO1996013860A1 FERROELECTRIC MEMORY 审中-公开
标题翻译：电磁记忆
公开(公告)号：WO1996013860A1
公开(公告)日：1996-05-09
申请号：PCT/US1995013379
申请日：1995-10-26
申请人： SYMETRIX CORPORATION , OLYMPUS OPTICAL CO., LTD.
发明人： SYMETRIX CORPORATION , OLYMPUS OPTICAL CO., LTD. , MIHARA, Takashi , WATANABE, Hitoshi , YOSHIMORI, Hiroyuki , PAZ DE ARAUJO, Carlos, A. , McMILLAN, Larry, D.
IPC分类号： H01L27/115
CPC分类号： H01L27/11502 , G11C11/22
摘要： A non-volatile integrated circuit memory (10, 11, 100, 200) in which the memory cell (10, 11) includes a first transistor gate (19, 36) overlying a first channel region (44A), a ferroelectric material (48) overlying a second channel region (44B), and a second transistor gate (23, 37) overlying a third channel region (44C). The channel regions (44A, 44B, 44C) are connected in series, and preferably are contiguous portions of a single semiconducting channel (44). The first channel (44A) is connected to a plate voltage that is 20 % to 50 % of the coercive voltage of the ferroelectric material. A sense amplifier (110) is connected to the third channel region (44C) via a bit line (108). The rise of the bit line after reading a logic "1" state of the cell is prevented from disturbing the ferroelectric material by shutting off the third channel before the sense amplifier rises.
摘要翻译：一种非易失性集成电路存储器（10,11,100,200），其中存储单元（10,11）包括覆盖第一沟道区（44A）的第一晶体管栅极（19,36），铁电材料（48））覆盖第二沟道区（44B），以及覆盖第三沟道区（44C）的第二晶体管栅极（23,37）。沟道区域（44A，44B，44C）串联连接，优选地是单个半导体沟道（44）的邻接部分。第一通道（44A）与铁电体的矫顽电压的20％〜50％的板电压连接。读出放大器（110）经由位线（108）连接到第三通道区域（44C）。在读出逻辑“1”状态之后，位线的上升通过在读出放大器上升之前关闭第三通道来防止铁电材料的干扰。

4. 发明申请

WO1994010702A1 PROCESS FOR FABRICATING LAYERED SUPERLATTICE MATERIALS AND MAKING ELECTRONIC DEVICES INCLUDING SAME 审中-公开
标题翻译：制造层状超导材料和制造包括其的电子器件的方法
公开(公告)号：WO1994010702A1
公开(公告)日：1994-05-11
申请号：PCT/US1993010021
申请日：1993-10-21
申请人： SYMETRIX CORPORATION , OLYMPUS OPTICAL CO., LTD.
发明人： SYMETRIX CORPORATION , OLYMPUS OPTICAL CO., LTD. , YOSHIMORI, Hiroyuki , WATANABE, Hitoshi , PAZ DE ARAUJO, Carlos, A. , McMILLAN, Larry, D. , CUCHIARO, Joseph, D. , SCOTT, Michael, C.
IPC分类号： H01L21/316
CPC分类号： H01L27/11502 , C23C16/45561 , C30B7/00 , C30B7/005 , C30B29/68 , H01L21/31691 , H01L27/10805 , H01L28/55 , H01L28/56 , H01L28/60
摘要： A liquid precursor containing a metal is applied to a substrate (18), RTP baked, and annealed to form a layered superlattice material (30). To obtain good electrical properties, prebaking the substrate (18) in oxygen in the RTP and anneal are essential, except for high bismuth content precursors. Excess bismuth between 110 % and 140 % of stoichiometry and RTP temperature of 750 DEG C is optimum. The film is formed in two layers (30A, 30B), the first of which uses a stoichiometric precursor and the second of which uses an excess bismuth precursor.
摘要翻译：将含有金属的液体前体施加到基材（18）上，进行RTP烘焙并退火以形成层状超晶格材料（30）。为了获得良好的电学性能，将基材（18）在RTP中进行氧预处理和退火是重要的，除了高铋含量前体。化学计量的110％至140％之间的过量铋和750℃的RTP温度是最佳的。膜形成为两层（30A，30B），其中第一层使用化学计量的前体，其中第二层使用过量的铋前体。

5. 发明申请

WO1996027192A1 METHOD AND APPARATUS FOR REDUCED FATIGUE IN FERROELECTRIC MEMORY ELEMENTS 审中-公开
标题翻译：在电磁记忆元件中减少疲劳的方法和装置
公开(公告)号：WO1996027192A1
公开(公告)日：1996-09-06
申请号：PCT/US1996002288
申请日：1996-02-27
申请人： SYMETRIX CORPORATION , OLYMPUS OPTICAL CO., LTD.
发明人： SYMETRIX CORPORATION , OLYMPUS OPTICAL CO., LTD. , MIHARA, Takashi , WATANABE, Hitoshi , YOSHIMORI, Hiroyuki , PAZ DE ARAUJO, Carlos, A. , MCMILLAN, Larry, D.
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G11C11/223 , G11C11/2293
摘要： A method and apparatus for programming ferroelectric memory cells (200, 600) which reduces polarizability fatigue effects of switching polarization of the ferroelectric devices (202) associated with the memory cells such as ferroelectric capacitors (202) and transistors (602). Alteration of the pulse width duty cycle associated with signals used to switch ferroelectric device polarization is shown to reduce polarizability fatigue of the ferroelectric material (608) thereby increasing the useful life of ferroelectric memory cells (200, 600). Methods and apparatus for producing a signal pulse duty cycle in the range 2-30 % is disclosed and shown to improve the useful life of the ferroelectric material (608).
摘要翻译：一种用于编程铁电存储器单元（200,600）的方法和装置，其减小与诸如铁电电容器（202）和晶体管（602）的存储单元相关联的铁电元件（202）的开关极化的极化率疲劳效应。显示与用于切换铁电体器件极化的信号相关联的脉冲宽度占空比的改变，以降低铁电材料（608）的极化率疲劳，从而增加铁电存储器单元（200,600）的使用寿命。公开并示出了用于产生2-30％范围内的信号脉冲占空比的方法和装置，以改善铁电材料（608）的使用寿命。

6. 发明申请

WO1996015537A1 METHOD AND APPARATUS FOR REDUCED FATIGUE IN FERROELECTRIC MEMORY ELEMENTS 审中-公开
标题翻译：在电磁记忆元件中减少疲劳的方法和装置
公开(公告)号：WO1996015537A1
公开(公告)日：1996-05-23
申请号：PCT/US1995014611
申请日：1995-11-07
申请人： SYMETRIX CORPORATION , OLYMPUS OPTICAL CO., LTD.
发明人： SYMETRIX CORPORATION , OLYMPUS OPTICAL CO., LTD. , MIHARA, Takashi , WATANABE, Hitoshi , YOSHIMORI, Hiroyuki , PAZ DE ARAUJO, Carlos, A. , MCMILLAN, Larry, D.
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A method and apparatus for programming ferroelectric memory cells (100, 200) which reduce fatigue effects of switching polarization of the ferroelectric devices associated with the memory cells such as ferroelectric capacitors (102, 202) and transistors (1002). Alteration of the rise and fall times associated with signals used to switch ferroelectric device polarization reduces fatigue of the ferroelectric material thereby increasing the useful life of ferroelectric memory cells. Slowing the rise and fall times as well as the rate of signal level rise and fall, (signal shape), reduces fatigue effects of switching polarization of ferroelectric devices. Methods and apparatus for producing a triangular ("sawtooth") signal waveform (322), a Gaussian signal waveform (422), and a waveform (522) having exponential rise anf fall times are disclosed.
摘要翻译：一种用于编程铁电存储器单元（100,200）的方法和装置，其减少与诸如铁电电容器（102,202）和晶体管（1002）之类的存储单元相关联的铁电元件的开关极化的疲劳效应。与用于切换铁电体器件极化的信号相关联的上升和下降时间的改变降低了铁电材料的疲劳，从而增加了铁电存储器单元的使用寿命。降低上升和下降时间以及信号电平上升和下降的速率（信号形状）可以降低铁电元件开关极化的疲劳效应。公开了用于产生具有指数上升和下降时间的三角形（“锯齿”）信号波形（322），高斯信号波形（422）和波形（522）的方法和装置。

7. 发明申请

WO1995027982A1 NON-VOLATILE MEMORY 审中-公开
标题翻译：非易失性存储器
公开(公告)号：WO1995027982A1
公开(公告)日：1995-10-19
申请号：PCT/US1995003758
申请日：1995-03-30
申请人： SYMETRIX CORPORATION , OLYMPUS OPTICAL CO., LTD
发明人： SYMETRIX CORPORATION , OLYMPUS OPTICAL CO., LTD , MCMILLAN, Larry, D. , MIHARA, Takashi , YOSHIMORI, Hiroyuki , GREGORY, John, W. , PAZ DE ARAUJO, Carlos, A.
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G11C11/223
摘要： An integrated memory unit (12, 600) includes a capacitor (30, 30A), a transistor (32, 32A), and saturation means (29, 25, 14, 62, 43, 15, 61; 71A, 72A) for polarizing the ferroelectric material (50, 74) to saturation with a voltage of less than 10 volts. One electrode (47, 49A) of the capacitor and the transistor gate (33, 33A) are the same conductive member. The other electrode may be formed by extensions (71A, 72A) of the transistor source (71) and drain (77) underlying the gate (33A). The capacitor (230, 30A) has a capacitance Cf, and an area Af, and the transistor (232, 32A) forms a gate capacitor (233, 255, 266) having an area Ag and a gate capacitance Cg, a gate overlap b, and a channel depth a. The ferroelectric material (250, 74) has a dielectric constant ELEMENT f and the gate insulator (268, 86) has a dielectric constant ELEMENT g. The memory unit has the parametric relationships: Cf /= 2a, and ELEMENT g >/= ELEMENT f/8.
摘要翻译：集成存储器单元（12,600）包括电容器（30,30A），晶体管（32,32A）和用于偏振的饱和装置（29,25,14,62,43,15,61,71A，72A）铁电材料（50,74）以小于10伏特的电压饱和。电容器和晶体管栅极（33,33A）的一个电极（47,49A）是相同的导电构件。另一个电极可以由晶体管源极（71）的延伸部（71A，72A）和栅极（33A）下方的漏极（77）形成。电容器（230,30A）具有电容Cf和区域Af，并且晶体管（232,32A）形成具有面积Ag和栅极电容Cg的栅极电容器（233,255,266），栅极重叠b ，以及频道深度a。铁电材料（250,74）具有介电常数ELEMENT f，并且栅极绝缘体（268,86）具有介电常数ELEMENT g。存储单元具有参数关系：Cf <5×Cg，Af / = 2a和ELEMENT g> / = ELEMENT f / 8。

8. 发明公开

EP0665981A1 PROCESS FOR FABRICATING LAYERED SUPERLATTICE MATERIALS AND MAKING ELECTRONIC DEVICES INCLUDING SAME 失效
标题翻译：分层的超晶格材料的方法和包含的电子设备。
公开(公告)号：EP0665981A1
公开(公告)日：1995-08-09
申请号：EP94901174.0
申请日：1993-10-21
申请人： SYMETRIX CORPORATION , OLYMPUS OPTICAL CO., LTD.
发明人： YOSHIMORI, Hiroyuki , WATANABE, Hitoshi , PAZ DE ARAUJO, Carlos, A. , McMILLAN, Larry, D. , CUCHIARO, Joseph, D. , SCOTT, Michael, C.
IPC分类号： C01B13 , C23C18 , C30B7 , C30B29 , H01L21 , H01L27 , H01L29
CPC分类号： H01L27/11502 , C23C16/45561 , C30B7/00 , C30B7/005 , C30B29/68 , H01L21/31691 , H01L27/10805 , H01L28/55 , H01L28/56 , H01L28/60
摘要： A method of fabricating a layered superlattice DRAM (100) compatible with conventional silicon CMOS technology. A MOSFET (72) is formed on a silicon substrate (71). A thick layer (77D) of BPSG followed by a thin SOG layer (77E) overlies the MOSFET (72). A capacitor (80) is formed by depositing a layer (81) of platinum, annealing, depositing an intermediate layer (84) comprising a layered superlattice material, annealing, depositing a second layer (84) of platinum, then patterning the capacitor (80). Another SOG layer (86) is deposited, contact holes (106, 107) to the MOSFET (72) and capacitor (80) are partially opened, the SOG (86) is annealed, the contact holes (106, 107) are completely opened, and a Pt/Ti/PtSi wiring layer (88, 288) is deposited.

9. 发明公开

EP0815589A2 PROCESS FOR FABRICATING LAYERED SUPERLATTICE MATERIALS AND MAKING ELECTRONIC DEVICES INCLUDING SAME 失效
标题翻译：分层超级电网材料的方法和含有电子电路
公开(公告)号：EP0815589A2
公开(公告)日：1998-01-07
申请号：EP96912411.0
申请日：1996-03-12
申请人： SYMETRIX CORPORATION , OLYMPUS OPTICAL CO., LTD.
发明人： YOSHIMORI, Hiroyuki , PAZ DE ARAUJO, Carlos, A. , ITO, Takeshi , SCOTT, Michael, C. , MCMILLAN, Larry, D.
IPC分类号： H01L21 , B05D1 , B05D3 , B05D7 , C23C16 , C23C18 , C23C26 , C30B7 , H01C7 , H01L27 , H01L29 , H01L41 , H05K3
CPC分类号： C23C18/1216 , B05D1/00 , B05D1/60 , B05D3/0493 , C23C16/4412 , C23C16/4486 , C23C16/45561 , C23C16/4558 , C23C16/46 , C23C16/482 , C23C16/52 , C23C18/1279 , C23C18/1283 , C23C18/1295 , C23C26/02 , C30B7/00 , C30B7/005 , C30B29/68 , H01C7/1013 , H01L21/314 , H01L21/31691 , H01L27/10805 , H01L27/11502 , H01L28/55 , H01L28/56 , H01L28/60 , H01L41/257 , H01L41/318 , H05K3/105
摘要： A liquid precursor containing a metal is applied to a substrate, RTP baked, and annealed to form a layered superlattice material. Special polyoxyalkylated precursor solutions are designed to optimize polarizability of the corresponding metal oxide materials by adding dopants including stoichiometric excess amounts of bismuth and tantalum. The RTP baking process is especially beneficial in optimizing the polarizability of the resultant metal oxide.

10. 发明授权

EP0665981B1 PROCESS FOR FABRICATING LAYERED SUPERLATTICE MATERIALS AND ELECTRONIC DEVICES INCLUDING SAME 失效
标题翻译：分层的超晶格材料的方法和包含电子器件
公开(公告)号：EP0665981B1
公开(公告)日：2002-03-20
申请号：EP94901174.6
申请日：1993-10-21
申请人： SYMETRIX CORPORATION , Olympus Optical Co., Ltd.
发明人： YOSHIMORI, Hiroyuki , WATANABE, Hitoshi , PAZ DE ARAUJO, Carlos, A. , McMILLAN, Larry, D. , CUCHIARO, Joseph, D. , SCOTT, Michael, C.
IPC分类号： H01L21/316 , H01L21/3205 , C30B7/00 , C23C18/12
CPC分类号： H01L27/11502 , C23C16/45561 , C30B7/00 , C30B7/005 , C30B29/68 , H01L21/31691 , H01L27/10805 , H01L28/55 , H01L28/56 , H01L28/60
摘要： A method of fabricating a layered superlattice DRAM (100) compatible with conventional silicon CMOS technology. A MOSFET (72) is formed on a silicon substrate (71). A thick layer (77D) of BPSG followed by a thin SOG layer (77E) overlies the MOSFET (72). A capacitor (80) is formed by depositing a layer (81) of platinum, annealing, depositing an intermediate layer (84) comprising a layered superlattice material, annealing, depositing a second layer (84) of platinum, then patterning the capacitor (80). Another SOG layer (86) is deposited, contact holes (106, 107) to the MOSFET (72) and capacitor (80) are partially opened, the SOG (86) is annealed, the contact holes (106, 107) are completely opened, and a Pt/Ti/PtSi wiring layer (88, 288) is deposited.

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