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51. 发明授权

US07902064B1 Method of forming a layer to enhance ALD nucleation on a substrate 有权
标题翻译：形成层以增强基底上的ALD成核的方法
公开(公告)号：US07902064B1
公开(公告)日：2011-03-08
申请号：US12121661
申请日：2008-05-15
申请人： Tony Chiang , Chi-I Lang , Zachary Fresco
发明人： Tony Chiang , Chi-I Lang , Zachary Fresco
IPC分类号： H01L21/4763
CPC分类号： H01L21/28562 , C23C16/0272 , C23C16/45525 , H01L21/76807 , H01L21/76814 , H01L21/76843 , H01L21/76876
摘要： A layer to enhance nucleation of a substrate is described, including a method to form the layer, the method including obtaining a substrate comprising a patterned feature comprising a dielectric region and a conductive region, selectively forming a self-aligned monolayer (SAM) on the dielectric region of the substrate to enhance nucleation process of a first precursor, and depositing the first precursor on the substrate, the precursor to adsorb on the SAM.
摘要翻译：描述了一种用于增强基底的成核的层，包括形成该层的方法，该方法包括获得包括具有电介质区域和导电区域的图案化特征的基底，在该基底上选择性地形成自对准单层（SAM）电介质区域以增强第一前体的成核过程，以及将第一前体沉积在基底上，所述前体吸附在SAM上。

52. 发明申请

US20100141571A1 Image Sensor with Integrated Light Meter for Controlling Display Brightness 审中-公开
标题翻译：带集成光度计的图像传感器，用于控制显示亮度
公开(公告)号：US20100141571A1
公开(公告)日：2010-06-10
申请号：US12331426
申请日：2008-12-09
申请人： Tony Chiang , Amit Mittra
发明人： Tony Chiang , Amit Mittra
IPC分类号： G09G3/36
CPC分类号： G09G3/20 , G09G3/3406 , G09G2320/064 , G09G2330/021 , G09G2360/144
摘要： The present invention is directed to an image sensor with an integrated light meter that can be used to automatically adjust the display brightness based on ambient light in the environment. According to one embodiment, an automatic exposure (AE) control loop estimates the ambient light when the image sensor is imaging, and the image sensor measures the ambient light when the image sensor is not imaging.
摘要翻译：本发明涉及一种具有集成光度计的图像传感器，其可用于基于环境中的环境光自动调节显示器亮度。根据一个实施例，当图像传感器成像时，自动曝光（AE）控制环路估计环境光，并且当图像传感器不成像时，图像传感器测量环境光。

53. 发明申请

US20090273087A1 CLOSED-LOOP SPUTTERING CONTROLLED TO ENHANCE ELECTRICAL CHARACTERISTICS IN DEPOSITED LAYER 有权
标题翻译：控制加密环境中的电气特性的隐蔽环
公开(公告)号：US20090273087A1
公开(公告)日：2009-11-05
申请号：US12243322
申请日：2008-10-01
申请人： Wayne French , Pragati Kumar , Prashant Phatak , Tony Chiang
发明人： Wayne French , Pragati Kumar , Prashant Phatak , Tony Chiang
IPC分类号： H01L23/48 , C23C14/34
CPC分类号： C23C14/083 , C23C14/0042 , C23C14/54 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1625 , H01L45/1641 , H01L45/165
摘要： This disclosure provides a method of fabricating a semiconductor device layer and an associated memory cell. Empirical data may be used to generate a hysteresis curve associated with metal oxide deposition for a metal-insulator-metal structure, with curve measurements reflecting variance of a desired electrical property as a function of cathode voltage used during a sputtering process that uses a biased target. By generating at least one voltage level to be used during the sputtering process, where the voltage reflects a suitable value for the electrical property from among the values obtainable in mixed-mode deposition, a semiconductor device layer may be produced with improved characteristics and durability. A multistable memory cell or array of such cells manufactured according to this process can, for a set of given materials (e.g., metals and oxygen source), be fabricated to have minimal leakage or “off” current characteristics (Ileak or Ioff, respectively) or a maximum ratio of “on” current to “off” current (Ion/Ioff).
摘要翻译：本公开提供了制造半导体器件层和相关联的存储单元的方法。经验数据可用于产生与金属 - 绝缘体 - 金属结构的金属氧化物沉积相关联的滞后曲线，曲线测量反映了在使用偏置目标的溅射过程期间所使用的阴极电压的期望电特性的变化。通过在溅射过程中产生要使用的至少一个电压电平，其中电压从混合模式沉积中可获得的值中反映适合的电特性值，可以制造具有改进的特性和耐久性的半导体器件层。对于一组给定的材料（例如金属和氧源），可以制造这样的电池的多电平存储器单元或阵列，以便具有最小的泄漏或“截止”电流特性（分别为Ileak或Ioff）或“关”电流与“关”电流（Ion / Ioff）的最大比例。

54. 发明申请

US20090272961A1 SURFACE TREATMENT TO IMPROVE RESISTIVE-SWITCHING CHARACTERISTICS 有权
标题翻译：表面处理提高电阻开关特性
公开(公告)号：US20090272961A1
公开(公告)日：2009-11-05
申请号：US12345576
申请日：2008-12-29
申请人： Michael Miller , Prashant Phatak , Tony Chiang , Xiying Chen , April Schricker , Tanmay Kumar
发明人： Michael Miller , Prashant Phatak , Tony Chiang , Xiying Chen , April Schricker , Tanmay Kumar
IPC分类号： H01L45/00 , H01L21/283
CPC分类号： H01L45/16 , H01L21/265 , H01L21/31155 , H01L27/2463 , H01L29/8615 , H01L45/08 , H01L45/10 , H01L45/12 , H01L45/1233 , H01L45/146 , H01L45/1608 , H01L45/1616 , H01L45/1625 , H01L45/1641 , H01L45/165
摘要： This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.
摘要翻译：本公开提供了制造半导体器件层和相关联的存储单元结构的方法。通过进行半导体器件层的表面处理（例如离子轰击）以产生具有有意深度分布的缺陷，可以创建具有更一致的电参数的多层存储单元。例如，在电阻式开关存储单元中，可以获得设定和复位电压的更紧密的分配和较低的成形电压，从而提高器件的产量和可靠性。在至少一个实施例中，选择深度轮廓以调制缺陷的类型及其对被轰击的金属氧化物层的电性能的影响并增强均匀的缺陷分布。

55. 发明申请

US20090269922A1 Method of depositing a metal seed layer over recessed feature surfaces in a semiconductor substrate 有权
标题翻译：在半导体衬底中的凹陷特征表面上沉积金属种子层的方法
公开(公告)号：US20090269922A1
公开(公告)日：2009-10-29
申请号：US12459091
申请日：2009-06-25
申请人： Tony Chiang , Gongda Yao , Peijun Ding , Fusen E. Chen , Barry L. Chin , Gene Y. Kohara , Zheng Xu , Hong Zhang
发明人： Tony Chiang , Gongda Yao , Peijun Ding , Fusen E. Chen , Barry L. Chin , Gene Y. Kohara , Zheng Xu , Hong Zhang
IPC分类号： H01L21/768
CPC分类号： H01L21/76843 , C23C14/046 , C23C14/165 , H01L21/2855 , H01L21/76805 , H01L21/76844 , H01L21/76846 , H01L21/76862 , H01L21/76865 , H01L21/76871 , H01L21/76877 , H01L21/76879 , H01L21/76883
摘要： We disclose a method of depositing a metal seed layer on a wafer substrate comprising a plurality of recessed device features. The method comprises depositing a first portion of the metal seed layer on the wafer via plasma deposition at a sufficient ratio of wafer substrate bias to DC source power that bottom coverage is achieved while resputtering of surfaces of the recessed device features is inhibited. The method also comprises depositing a second portion of the metal seed layer at a ration of substrate RF bias to DC source power such that resputtering is not inhibited.
摘要翻译：我们公开了在包括多个凹入的装置特征的晶片衬底上沉积金属种子层的方法。该方法包括通过等离子体沉积将金属种子层的第一部分以足够的晶片衬底偏压比与DC源功率沉积在晶片上，达到底部覆盖范围，同时抑制凹陷器件特征的表面的再溅射。该方法还包括以基板RF偏压的比例将金属种子层的第二部分沉积到DC源功率，使得不会抑制再溅射。

56. 发明申请

US20050272254A1 Method of depositing low resistivity barrier layers for copper interconnects 审中-公开
标题翻译：沉积用于铜互连的低电阻阻挡层的方法
公开(公告)号：US20050272254A1
公开(公告)日：2005-12-08
申请号：US11184404
申请日：2005-07-18
申请人： Peijun Ding , Zheng Xu , Hong Zhang , Xianmin Tang , Praburam Gopalraja , Suraj Rengarajan , John Forster , Jianming Fu , Tony Chiang , Gongda Yao , Fusen Chen , Barry Chin , Gene Kohara
发明人： Peijun Ding , Zheng Xu , Hong Zhang , Xianmin Tang , Praburam Gopalraja , Suraj Rengarajan , John Forster , Jianming Fu , Tony Chiang , Gongda Yao , Fusen Chen , Barry Chin , Gene Kohara
IPC分类号： C23C14/06 , C23C14/16 , C23C14/32 , H01L21/285 , H01L21/44 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/02183 , C23C14/0641 , C23C14/165 , C23C14/541 , C23C14/5806 , H01L21/02266 , H01L21/2855 , H01L21/318 , H01L21/76846 , H01L21/76856 , H01L21/76862 , H01L21/76876
摘要： We have discovered a method of providing a thin approximately from about 2 Å to about 100 Å thick TaN seed layer, which can be used to induce the formation of alpha tantalum when tantalum is deposited over the TaN seed layer. Further, the TaN seed layer exhibits low resistivity, in the range of 30 μΩ cm and can be used as a low resistivity barrier layer in the absence of an alpha tantalum layer. In one embodiment of the method, a TaN film is altered on its surface form the TaN seed layer. In another embodiment of the method, a Ta film is altered on its surface to form the TaN seed layer.
摘要翻译：我们已经发现了一种提供大约约2埃至大约100埃的Ta N种子层的薄膜的方法，当钽沉积在Ta上时可用于诱导形成α钽， SUB> N 种子层。此外，Ta N N种子层在30μΩ·cm的范围内显示低电阻率，并且可以在不存在α钽层的情况下用作低电阻率阻挡层。在该方法的一个实施方案中，TaN膜在其表面上形成Ta N N种子层。在该方法的另一个实施方案中，在其表面上改变Ta膜以形成Ta N N种子层。

57. 发明申请

US20050031784A1 Barrier layer for electroplating processes 审中-公开
标题翻译：电镀工艺的屏障层
公开(公告)号：US20050031784A1
公开(公告)日：2005-02-10
申请号：US10931865
申请日：2004-09-01
申请人： Peijun Ding , Tony Chiang , Tse-Yong Yao , Barry Chin
发明人： Peijun Ding , Tony Chiang , Tse-Yong Yao , Barry Chin
IPC分类号： C25D5/34 , C25D3/00 , C25D7/12 , H01L21/28 , H01L21/288 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522 , C23C14/00 , H05H1/24
CPC分类号： H01L21/76846 , H01L21/2885 , H01L21/76843 , H01L21/76864 , H01L21/76873 , H01L21/76877
摘要： The invention generally provides a method for preparing a surface for electrochemical deposition comprising forming a high conductance barrier layer on the surface and depositing a seed layer over the high conductance barrier layer. Another aspect of the invention provides a method for filling a structure on a substrate, comprising depositing a high conductance barrier layer on one or more surfaces of the structure, depositing a seed layer over the barrier layer, and electrochemically depositing a metal to fill the structure.
摘要翻译：本发明通常提供了一种用于制备用于电化学沉积的表面的方法，其包括在表面上形成高导电阻挡层并在高导电阻挡层上沉积种子层。本发明的另一方面提供了一种用于在基板上填充结构的方法，包括在所述结构的一个或多个表面上沉积高电导阻挡层，在所述阻挡层上沉积晶种层，以及电化学沉积金属以填充所述结构。

58. 发明授权

US06559061B2 Method and apparatus for forming improved metal interconnects 失效
公开(公告)号：US06559061B2
公开(公告)日：2003-05-06
申请号：US09928891
申请日：2001-08-13
申请人： Imran Hashim , Tony Chiang , Barry Chin
发明人： Imran Hashim , Tony Chiang , Barry Chin
IPC分类号： H01L21302
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76814 , H01L21/76831 , H01L21/76834 , H01L21/76838 , H01L21/76877 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming copper interconnects free from via-to-via leakage currents and having low resistances are disclosed. In a first aspect, a barrier layer is deposited on the first metal layer prior to copper oxide sputter-etching to prevent copper atoms from reaching the interlayer dielectric and forming via-to-via leakage current paths therein. In a second aspect, a capping dielectric barrier layer is deposited over the first metal layer prior to sputter etching. During sputter-etching, the capping dielectric barrier layer redistributes on the sidewalls of the interlayer dielectric, preventing sputter-etched copper atoms from reaching the interlayer dielectric and forming via-to-via leakage paths therein. In a third aspect, both a capping dielectric barrier layer and a barrier layer are deposited over the first metal layer prior to sputter-etching to prevent copper atoms produced during sputter-etching from reaching the interlayer dielectric and forming via-to-via leakage paths therein.

59. 发明授权

US6160315A Copper alloy via structure 有权
标题翻译：铜合金通孔结构
公开(公告)号：US6160315A
公开(公告)日：2000-12-12
申请号：US478721
申请日：2000-01-06
申请人： Tony Chiang , Peijun Ding , Barry Chin , Imran Hashim , Bingxi Sun
发明人： Tony Chiang , Peijun Ding , Barry Chin , Imran Hashim , Bingxi Sun
IPC分类号： C23C14/02 , C23C14/16 , C23C16/02 , C23C16/06 , H01L21/285 , H01L21/768 , H01L23/532 , H01L23/48
CPC分类号： H01L21/76834 , C23C14/024 , C23C14/025 , C23C14/16 , C23C14/165 , C23C16/0281 , C23C16/06 , H01L21/2855 , H01L21/76831 , H01L21/76843 , H01L21/76871 , H01L21/76877 , H01L21/76888 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A copper via structure formed when copper and a small amount of an alloying metal such as magnesium or aluminum are cosputtered onto a substrate having oxide on at least a portion of its surface. Either the wafer is held at an elevated temperature during deposition or the sputtered film is annealed without the wafer being exposed to ambient. Due to the high temperature, the alloying metal diffuses to the surface. If a surface is exposed to a low partial pressure of oxygen or contacts silicon dioxide, the magnesium or aluminum forms a thin stable oxide but also extends into the oxide a distance of about 100 nm. The alloying metal oxide having a thickness of about 6 nm on the oxide sidewalls encapsulates the copper layer to provide a barrier against copper migration, to form an adhesion layer over silicon dioxide, and to act as a seed layer for the later growth of copper, for example, by electroplating.
摘要翻译：当铜和少量的合金金属如镁或铝形成的铜通孔结构在其表面的至少一部分上被分散在具有氧化物的基底上。在沉积期间晶片保持在升高的温度下，或者溅射膜被退火而晶片不暴露于环境中。由于高温，合金金属扩散到表面。如果表面暴露于低的氧分压或接触二氧化硅，则镁或铝形成薄的稳定氧化物，但也延伸到氧化物中约100nm的距离。在氧化物侧壁上具有约6nm厚度的合金化金属氧化物封装铜层以提供阻挡铜迁移的屏障，以形成二氧化硅以上的粘合层，并且用作后续生长铜的种子层，例如，通过电镀。

60. 发明授权

US09129894B2 Embedded nonvolatile memory elements having resistive switching characteristics 有权
标题翻译：具有电阻开关特性的嵌入式非易失性存储元件
公开(公告)号：US09129894B2
公开(公告)日：2015-09-08
申请号：US13621371
申请日：2012-09-17
申请人： Imran Hashim , Tony Chiang , Vidyut Gopal , Yun Wang
发明人： Imran Hashim , Tony Chiang , Vidyut Gopal , Yun Wang
IPC分类号： G11C11/21 , H01L27/24 , G11C13/00 , H01L45/00
CPC分类号： H01L45/1608 , G11C13/0007 , G11C13/0069 , G11C2213/32 , G11C2213/51 , G11C2213/52 , G11C2213/74 , G11C2213/79 , H01L27/2436 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/146
摘要： Provided are nonvolatile memory assemblies each including a resistive switching layer and current steering element. The steering element may be a transistor connected in series with the switching layer. Resistance control provided by the steering element allows using switching layers requiring low switching voltages and currents. Memory assemblies including such switching layers are easier to embed into integrated circuit chips having other low voltage components, such as logic and digital signal processing components, than, for example, flash memory requiring much higher switching voltages. In some embodiments, provided nonvolatile memory assemblies operate at switching voltages less than about 3.0V and corresponding currents less than 50 microamperes. A memory element may include a metal rich hafnium oxide disposed between a titanium nitride electrode and doped polysilicon electrode. One electrode may be connected to a drain or source of the transistor, while another electrode is connected to a signal line.
摘要翻译：提供了各自包括电阻式开关层和电流控制元件的非易失性存储器组件。转向元件可以是与开关层串联连接的晶体管。由转向元件提供的电阻控制允许使用需要低开关电压和电流的开关层。包括这种开关层的存储器组件比例如需要高得多的开关电压的闪速存储器更容易嵌入到具有其它低电压组件（例如逻辑和数字信号处理组件）的集成电路芯片中。在一些实施例中，所提供的非易失性存储器组件在小于约3.0V的开关电压和小于50微安的相应电流下工作。存储元件可以包括设置在氮化钛电极和掺杂多晶硅电极之间的富含金属的氧化铪。一个电极可以连接到晶体管的漏极或源极，而另一个电极连接到信号线。

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