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1. 发明申请

US20090272961A1 SURFACE TREATMENT TO IMPROVE RESISTIVE-SWITCHING CHARACTERISTICS 有权
标题翻译：表面处理提高电阻开关特性
公开(公告)号：US20090272961A1
公开(公告)日：2009-11-05
申请号：US12345576
申请日：2008-12-29
申请人： Michael Miller , Prashant Phatak , Tony Chiang , Xiying Chen , April Schricker , Tanmay Kumar
发明人： Michael Miller , Prashant Phatak , Tony Chiang , Xiying Chen , April Schricker , Tanmay Kumar
IPC分类号： H01L45/00 , H01L21/283
CPC分类号： H01L45/16 , H01L21/265 , H01L21/31155 , H01L27/2463 , H01L29/8615 , H01L45/08 , H01L45/10 , H01L45/12 , H01L45/1233 , H01L45/146 , H01L45/1608 , H01L45/1616 , H01L45/1625 , H01L45/1641 , H01L45/165
摘要： This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.
摘要翻译：本公开提供了制造半导体器件层和相关联的存储单元结构的方法。通过进行半导体器件层的表面处理（例如离子轰击）以产生具有有意深度分布的缺陷，可以创建具有更一致的电参数的多层存储单元。例如，在电阻式开关存储单元中，可以获得设定和复位电压的更紧密的分配和较低的成形电压，从而提高器件的产量和可靠性。在至少一个实施例中，选择深度轮廓以调制缺陷的类型及其对被轰击的金属氧化物层的电性能的影响并增强均匀的缺陷分布。

2. 发明授权

US08062918B2 Surface treatment to improve resistive-switching characteristics 有权
标题翻译：表面处理提高电阻开关特性
公开(公告)号：US08062918B2
公开(公告)日：2011-11-22
申请号：US12345576
申请日：2008-12-29
申请人： Michael Miller , Prashant Phatak , Tony Chiang , Xiying Chen , April Schricker , Tanmay Kumar
发明人： Michael Miller , Prashant Phatak , Tony Chiang , Xiying Chen , April Schricker , Tanmay Kumar
IPC分类号： H01L21/00
CPC分类号： H01L45/16 , H01L21/265 , H01L21/31155 , H01L27/2463 , H01L29/8615 , H01L45/08 , H01L45/10 , H01L45/12 , H01L45/1233 , H01L45/146 , H01L45/1608 , H01L45/1616 , H01L45/1625 , H01L45/1641 , H01L45/165
摘要： This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.
摘要翻译：本公开提供了制造半导体器件层和相关联的存储单元结构的方法。通过进行半导体器件层的表面处理（例如离子轰击）以产生具有有意深度分布的缺陷，可以创建具有更一致的电参数的多层存储单元。例如，在电阻式开关存储单元中，可以获得设定和复位电压的更紧密的分配和较低的成形电压，从而提高器件的产量和可靠性。在至少一个实施例中，选择深度轮廓以调制缺陷的类型及其对被轰击的金属氧化物层的电性能的影响并增强均匀的缺陷分布。

3. 发明申请

US20120032133A1 SURFACE TREATMENT TO IMPROVE RESISTIVE-SWITCHING CHARACTERISTICS 有权
标题翻译：表面处理提高电阻开关特性
公开(公告)号：US20120032133A1
公开(公告)日：2012-02-09
申请号：US13252360
申请日：2011-10-04
申请人： Michael Miller , Prashant Phatak , Tony Chiang , Xiying Chen , April Schricker , Tanmay Kumar
发明人： Michael Miller , Prashant Phatak , Tony Chiang , Xiying Chen , April Schricker , Tanmay Kumar
IPC分类号： H01L45/00
CPC分类号： H01L45/16 , H01L21/265 , H01L21/31155 , H01L27/2463 , H01L29/8615 , H01L45/08 , H01L45/10 , H01L45/12 , H01L45/1233 , H01L45/146 , H01L45/1608 , H01L45/1616 , H01L45/1625 , H01L45/1641 , H01L45/165
摘要： This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.
摘要翻译：本公开提供了制造半导体器件层和相关联的存储单元结构的方法。通过进行半导体器件层的表面处理（例如离子轰击）以产生具有有意深度分布的缺陷，可以创建具有更一致的电参数的多层存储单元。例如，在电阻式开关存储单元中，可以获得设定和复位电压的更紧密的分配和较低的成形电压，从而提高器件的产量和可靠性。在至少一个实施例中，选择深度轮廓以调制缺陷的类型及其对被轰击的金属氧化物层的电性能的影响并增强均匀的缺陷分布。

4. 发明授权

US08465996B2 Surface treatment to improve resistive-switching characteristics 有权
公开(公告)号：US08465996B2
公开(公告)日：2013-06-18
申请号：US13593116
申请日：2012-08-23
申请人： Michael Miller , Prashant Phatak , Tony Chiang , Xiyang Chen , April Schricker , Tanmay Kumar
发明人： Michael Miller , Prashant Phatak , Tony Chiang , Xiyang Chen , April Schricker , Tanmay Kumar
IPC分类号： H01L21/00
CPC分类号： H01L45/16 , H01L21/265 , H01L21/31155 , H01L27/2463 , H01L29/8615 , H01L45/08 , H01L45/10 , H01L45/12 , H01L45/1233 , H01L45/146 , H01L45/1608 , H01L45/1616 , H01L45/1625 , H01L45/1641 , H01L45/165
摘要： This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.

5. 发明申请

US20120315725A1 SURFACE TREATMENT TO IMPROVE RESISTIVE-SWITCHING CHARACTERISTICS 有权
公开(公告)号：US20120315725A1
公开(公告)日：2012-12-13
申请号：US13593116
申请日：2012-08-23
申请人： Michael Miller , Prashant Phatak , Tony Chiang , Xiyang Chen , April Schricker , Tanmay Kumar
发明人： Michael Miller , Prashant Phatak , Tony Chiang , Xiyang Chen , April Schricker , Tanmay Kumar
IPC分类号： H01L21/8239
CPC分类号： H01L45/16 , H01L21/265 , H01L21/31155 , H01L27/2463 , H01L29/8615 , H01L45/08 , H01L45/10 , H01L45/12 , H01L45/1233 , H01L45/146 , H01L45/1608 , H01L45/1616 , H01L45/1625 , H01L45/1641 , H01L45/165
摘要： This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.

6. 发明授权

US08274066B2 Surface treatment to improve resistive-switching characteristics 有权
标题翻译：表面处理提高电阻开关特性
公开(公告)号：US08274066B2
公开(公告)日：2012-09-25
申请号：US13252360
申请日：2011-10-04
申请人： Michael Miller , Prashant Phatak , Tony Chiang , Xiyang Chen , April Schricker , Tanmay Kumar
发明人： Michael Miller , Prashant Phatak , Tony Chiang , Xiyang Chen , April Schricker , Tanmay Kumar
IPC分类号： H01L47/00
CPC分类号： H01L45/16 , H01L21/265 , H01L21/31155 , H01L27/2463 , H01L29/8615 , H01L45/08 , H01L45/10 , H01L45/12 , H01L45/1233 , H01L45/146 , H01L45/1608 , H01L45/1616 , H01L45/1625 , H01L45/1641 , H01L45/165
摘要： This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.
摘要翻译：本公开提供了制造半导体器件层和相关联的存储单元结构的方法。通过进行半导体器件层的表面处理（例如离子轰击）以产生具有有意深度分布的缺陷，可以创建具有更一致的电参数的多层存储单元。例如，在电阻式开关存储单元中，可以获得设定和复位电压的更紧密的分配和较低的成形电压，从而提高器件的产量和可靠性。在至少一个实施例中，选择深度轮廓以调制缺陷的类型及其对被轰击的金属氧化物层的电性能的影响并增强均匀的缺陷分布。

7. 发明授权

US08975613B1 Resistive-switching memory elements having improved switching characteristics 有权
公开(公告)号：US08975613B1
公开(公告)日：2015-03-10
申请号：US12610236
申请日：2009-10-30
申请人： Ronald John Kuse , Tony Chiang , Michael Miller , Prashant Phatak , Jinhong Tong
发明人： Ronald John Kuse , Tony Chiang , Michael Miller , Prashant Phatak , Jinhong Tong
IPC分类号： H01L21/16 , G11C11/00
CPC分类号： H01L45/146 , G11C13/0007 , G11C13/003 , G11C2213/32 , G11C2213/51 , G11C2213/52 , G11C2213/56 , G11C2213/71 , G11C2213/72 , G11C2213/74 , G11C2213/76 , G11C2213/79 , H01L27/2409 , H01L27/2463 , H01L29/861 , H01L45/10 , H01L45/12 , H01L45/1233 , H01L45/1616 , H01L45/1641
摘要： Resistive-switching memory elements having improved switching characteristics are described, including a memory element having a first electrode and a second electrode, a switching layer between the first electrode and the second electrode, the switching layer comprising a first metal oxide having a first bandgap greater than 4 electron volts (eV), the switching layer having a first thickness, and a coupling layer between the switching layer and the second electrode, the coupling layer comprising a second metal oxide having a second bandgap greater the first bandgap, the coupling layer having a second thickness that is less than 25 percent of the first thickness.

8. 发明申请

US20120205610A1 RESISTIVE SWITCHING MEMORY ELEMENT INCLUDING DOPED SILICON ELECTRODE 有权
标题翻译：电阻式开关元件包括掺杂的硅电极
公开(公告)号：US20120205610A1
公开(公告)日：2012-08-16
申请号：US13454392
申请日：2012-04-24
申请人： Prashant Phatak , Tony Chiang , Michael Miller , Wen Wu
发明人： Prashant Phatak , Tony Chiang , Michael Miller , Wen Wu
IPC分类号： H01L45/00
CPC分类号： H01L45/1616 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/10 , H01L45/1233 , H01L45/1253 , H01L45/146
摘要： A resistive switching memory element including a doped silicon electrode is described, including a first electrode comprising doped silicon having a first work function, a second electrode having a second work function that is different from the first work function by between 0.1 and 1.0 electron volts (eV), a metal oxide layer between the first electrode and the second electrode, the metal oxide layer switches using bulk-mediated switching and has a bandgap of greater than 4 eV, and the memory element switches from a low resistance state to a high resistance state and vice versa.
摘要翻译：描述了包括掺杂硅电极的电阻式开关存储元件，其包括包括具有第一功函数的掺杂硅的第一电极，具有与第一功函数不同的第二功函数的第二电极在0.1和1.0电子伏特之间 eV），第一电极和第二电极之间的金属氧化物层，金属氧化物层使用体积介导的开关进行开关，并且具有大于4eV的带隙，并且存储元件从低电阻状态切换到高电阻状态，反之亦然。

9. 发明申请

US20120088328A1 NON-VOLATILE RESISTIVE-SWITCHING MEMORIES 有权
标题翻译：非易失性电阻开关存储器
公开(公告)号：US20120088328A1
公开(公告)日：2012-04-12
申请号：US13329253
申请日：2011-12-17
申请人： Prashant Phatak , Tony Chiang , Pragati Kumar , Michael Miller
发明人： Prashant Phatak , Tony Chiang , Pragati Kumar , Michael Miller
IPC分类号： H01L21/8239
CPC分类号： H01L45/146 , G11C13/0007 , G11C2213/32 , G11C2213/55 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L29/8615 , H01L45/08 , H01L45/10 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/1616 , H01L45/1625 , H01L45/1641 , H01L45/165 , H01L45/1658 , H01L47/00
摘要： Non-volatile resistive-switching memories are described, including a memory element having a first electrode, a second electrode, a metal oxide between the first electrode and the second electrode. The metal oxide switches using bulk-mediated switching, has a bandgap greater than 4 electron volts (eV), has a set voltage for a set operation of at least one volt per one hundred angstroms of a thickness of the metal oxide, and has a leakage current density less than 40 amps per square centimeter (A/cm2) measured at 0.5 volts (V) per twenty angstroms of the thickness of the metal oxide.
摘要翻译：描述了非易失性电阻式切换存储器，包括在第一电极和第二电极之间具有第一电极，第二电极，金属氧化物的存储元件。使用大容量介导的开关的金属氧化物开关具有大于4电子伏特（eV）的带隙，具有用于金属氧化物的厚度每100埃至少一伏特的设定操作的设定电压，并且具有漏电流密度小于每平方厘米40安培（A / cm2），每0.5伏（V），金属氧化物厚度每20埃测得。

10. 发明授权

US08049305B1 Stress-engineered resistance-change memory device 有权
标题翻译：应力工程电阻变化记忆装置
公开(公告)号：US08049305B1
公开(公告)日：2011-11-01
申请号：US12580196
申请日：2009-10-15
申请人： Michael Miller , Prashant Phatak , Tony Chiang
发明人： Michael Miller , Prashant Phatak , Tony Chiang
IPC分类号： H01L29/10
CPC分类号： H01L45/1233 , H01L23/5228 , H01L23/525 , H01L27/2409 , H01L45/08 , H01L45/146 , H01L45/1641 , H01L2924/0002 , H01L2924/00
摘要： A resistance-change memory device using stress engineering is described, including a first layer including a first conductive electrode, a second layer above the first layer including a resistive-switching element, a third layer above the second layer including a second conductive electrode, where a first stress is created in the switching element at a first interface between the first layer and the second layer upon heating the memory element, and where a second stress is created in the switching element at a second interface between the second layer and the third layer upon the heating. A stress gradient equal to a difference between the first stress and the second stress has an absolute value greater than 50 MPa, and a reset voltage of the memory element has a polarity relative to a common electrical potential that has a sign opposite the stress gradient when applied to the first conductive electrode.
摘要翻译：描述了使用应力工程的电阻变化存储器件，包括第一层，包括第一导电电极，第一层上方的第二层，包括电阻式开关元件，第二层上方的第三层包括第二导电电极，在加热存储元件时在第一层和第二层之间的第一界面处在开关元件中产生第一应力，并且其中在第二层和第三层之间的第二界面处在开关元件中产生第二应力加热。等于第一应力和第二应力之间的差的应力梯度具有大于50MPa的绝对值，并且存储元件的复位电压具有相对于具有与应力梯度相反的符号的公共电位的极性，应用于第一导电电极。

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