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51. 发明授权

US06734080B1 Semiconductor isolation material deposition system and method 失效
标题翻译：半导体隔离材料沉积系统及方法
公开(公告)号：US06734080B1
公开(公告)日：2004-05-11
申请号：US10159078
申请日：2002-05-31
申请人： Nian Yang , John Jianshi Wang , Tien-Chun Yang
发明人： Nian Yang , John Jianshi Wang , Tien-Chun Yang
IPC分类号： H01L2176
CPC分类号： H01L21/76229
摘要： A semiconductor isolation material deposition system and method that facilitates convenient and efficient integrated multi-step deposition of isolation regions is presented. In one embodiment of the present invention, an integrated circuit includes densely configured component areas and sparsely configured component areas. An active area in a wafer is created and a shallow trench space is formed. A thin layer of TEOS isolation material layer is deposited on top of the active area and the shallow trench. For example, the layer of thin layer of TEOS isolation material is in a range of 4000 to 5000 angstroms thick over the top of underlying active areas. A reverse mask and pre-planarization etch is performed on the thin layer of TEOS isolation material. The remaining TEOS edge spikes between the densely configured component area and the sparsely configured component area are minimal (e.g., about 500 angstroms. The remaining excess oxidant and silicon nitride are removed utilizing chemical mechanical polishing processes. In one exemplary implementation, the present invention facilitates an integrated approach to STI fabrication processes that achieve successful high yielding results by considering the impacts of one process step on another.
摘要翻译：介绍了半导体隔离材料沉积系统及其方法，便于实现隔离区域的多步沉积。在本发明的一个实施例中，集成电路包括密集配置的组件区域和稀疏配置的组件区域。产生晶片中的有效区域并形成浅沟槽空间。 TEOS隔离材料层的薄层沉积在有源区域和浅沟槽的顶部。例如，薄层的TEOS隔离材料层的厚度在下面有效区域顶部的4000至5000埃的范围内。在TEOS隔离材料的薄层上进行反掩模和预平面化蚀刻。在密集配置的部件区域和稀疏构造的部件区域之间的剩余的TEOS边缘尖峰是最小的（例如，约500埃），使用化学机械抛光工艺去除剩余的多余的氧化剂和氮化硅。在一个示例性实施方式中，通过考虑一个工艺步骤对另一个工艺步骤的影响，可以获得成功的高产量结果的STI制造工艺的综合方法。

52. 发明授权

US06734028B1 Method of detecting shallow trench isolation corner thinning by electrical stress 失效
标题翻译：通过电应力检测浅沟槽隔离角变薄的方法
公开(公告)号：US06734028B1
公开(公告)日：2004-05-11
申请号：US10113152
申请日：2002-03-28
申请人： Tien-Chun Yang , Nian Yang , Hyeon-Seag Kim
发明人： Tien-Chun Yang , Nian Yang , Hyeon-Seag Kim
IPC分类号： H01L2166
CPC分类号： H01L22/34 , G01R31/275 , G01R31/2831
摘要： A method and apparatus for testing semiconductors comprising shallow trench isolation (STI) edge structures. An edge intensive shallow trench isolation structure (500) is coupled to a voltage source (310) and a current versus voltage profile is recorded. A planar structure (600) on the same wafer is coupled to a voltage source and a current versus voltage profile is recorded. An electrical stress is applied to both structures. Additional current profiles of each structure are obtained after the electrical stress. A comparison of difference current profiles obtained for the two types of structures may indicate the presence and/or the extent of STI corner effects. More specifically, a value for a normalized gate current difference for an STI edge intensive structure (500) greater than normalized gate current difference of a planar structure (600) is indicative of an increased rate of electron trapping in STI corners, which may indicate that the STI corners are too thin. In this novel manner, STI corner thickness may be observed in a non-destructive, electrical test process, resulting in higher quality and greater reliability of semiconductors using STI processes.
摘要翻译：一种用于测试包括浅沟槽隔离（STI）边缘结构的半导体的方法和装置。边缘密集的浅沟槽隔离结构（500）耦合到电压源（310），并记录电流对电压曲线。在同一晶片上的平面结构（600）被耦合到电压源并且记录电流对电压曲线。对两个结构都施加电应力。在电应力之后，获得每个结构的附加电流分布。对于两种类型的结构获得的差异电流曲线的比较可以指示STI拐角效应的存在和/或程度。更具体地，大于平面结构（600）的归一化栅极电流差的STI边缘强化结构（500）的归一化栅极电流差的值表示STI拐角中的电子捕获速率增加，这可以指示 STI角落太薄了。以这种新颖的方式，可以在非破坏性电气测试过程中观察到STI拐角厚度，从而导致使用STI工艺的半导体的更高质量和更高的可靠性。

53. 发明授权

US06472236B1 Determination of effective oxide thickness of a plurality of dielectric materials in a MOS stack 失效
标题翻译：确定MOS堆叠中多个介电材料的有效氧化物厚度
公开(公告)号：US06472236B1
公开(公告)日：2002-10-29
申请号：US09904740
申请日：2001-07-13
申请人： Zhigang Wang , Nian Yang , Tien-Chun Yang
发明人： Zhigang Wang , Nian Yang , Tien-Chun Yang
IPC分类号： H01L2166
CPC分类号： H01L22/12
摘要： System and method for determining a respective effective oxide thickness for each of first and second dielectric structures that form a MOS (metal oxide semiconductor) stack. A first plurality of test MOS (metal oxide semiconductor) stacks are formed, and each test MOS stack includes a respective first dielectric structure comprised of a first dielectric material and a respective second dielectric structure comprised of a second dielectric material. A respective deposition time for forming the respective first dielectric structure corresponding to each of the first plurality of test MOS stacks is varied such that a respective first effective oxide thickness of the respective first dielectric structure varies for the first plurality of test MOS stacks. A respective second effective oxide thickness of the respective second dielectric structure is maintained to be substantially same for each of the first plurality of test MOS stacks. A respective total effective oxide thickness, EOTMOS, is measured for each of the first plurality of test MOS stacks. A first graph having total effective oxide thickness as a first axis and having deposition time for forming the first dielectric structure as a second axis is generated by plotting the respective total effective oxide thickness, EOTMOS, versus the respective deposition time for forming the respective first dielectric structure for each of the first plurality of test MOS stacks. The respective second effective oxide thickness of the respective second dielectric structure that is substantially same for each of the first plurality of test MOS stacks is determined from an intercept of the first axis of total effective oxide thickness when deposition time for forming the first dielectric structure of the second axis is substantially zero in the first graph.
摘要翻译：用于确定形成MOS（金属氧化物半导体）堆叠的第一和第二电介质结构中的每一个的相应有效氧化物厚度的系统和方法。形成第一多个测试MOS（金属氧化物半导体）堆叠，并且每个测试MOS堆叠包括由第一电介质材料和由第二电介质材料组成的相应的第二电介质结构的相应的第一电介质结构。形成对应于第一多个测试MOS堆叠中的每一个的相应的第一介电结构的各自的沉积时间被改变，使得相应的第一介电结构的相应的第一有效氧化物厚度对于第一多个测试MOS堆叠而言是变化的。相应的第二介电结构的相应的第二有效氧化物厚度被保持为对于第一多个测试MOS堆叠中的每一个基本相同。对于第一多个测试MOS堆叠中的每一个测量相应的总有效氧化物厚度EOTMOS。通过绘制相应的总有效氧化物厚度EOTMOS，相对于形成相应的第一电介质的相应沉积时间，产生具有总有效氧化物厚度作为第一轴并具有用于形成第一电介质结构作为第二轴的沉积时间的第一图所述第一多个测试MOS堆叠中的每一个的结构。对于第一多个测试MOS堆叠中的每一个基本上相同的相应的第二介电结构的相应的第二有效氧化物厚度是从形成第一介电结构的沉积时间的总有效氧化物厚度的第一轴的截距来确定的在第一图中第二轴基本为零。

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