专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US06046609A Sense amplifier circuit 有权
标题翻译：感应放大电路
公开(公告)号：US06046609A
公开(公告)日：2000-04-04
申请号：US188369
申请日：1998-11-10
申请人： Hiroshi Toyoshima , Masashige Harada , Tomohiro Nagano , Yoji Nishio , Atsushi Hiraishi , Kunihiro Komiyaji , Hideharu Yahata , Kenichi Fukui , Hirofumi Zushi , Takahiro Sonoda , Haruko Kawachino , Sadayuki Morita
发明人： Hiroshi Toyoshima , Masashige Harada , Tomohiro Nagano , Yoji Nishio , Atsushi Hiraishi , Kunihiro Komiyaji , Hideharu Yahata , Kenichi Fukui , Hirofumi Zushi , Takahiro Sonoda , Haruko Kawachino , Sadayuki Morita
IPC分类号： G11C11/419 , G11C7/06 , G11C11/409
CPC分类号： G11C7/065
摘要： A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the latch circuit, and a current source connected in series to the latch circuit and NMOS transistor pair. The NMOS transistors amplify a small voltage difference of input signals, and the inverters of the latch circuit further amplify the resulting voltage difference to produce the output signals. Based on is a small voltage difference of input signals being amplified in two stages and the amplifying circuit being a 2-stage serial connection of the current source and the NMOS transistor or CMOS inverter, the delay time of output response can be reduced.
摘要翻译：一种读出放大器，其目的是在输出放大的输出信号之后，在接收到小的电压差之后，减小输出响应时间，由一对CMOS反相器构成的锁存电路，并联的一对NMOS晶体管到锁存电路，以及与锁存电路和NMOS晶体管对串联的电流源。 NMOS晶体管放大输入信号的小电压差，并且锁存电路的反相器进一步放大所产生的电压差以产生输出信号。基于两级放大的输入信号的小电压差，并且放大电路是电流源和NMOS晶体管或CMOS反相器的2级串联，可以降低输出响应的延迟时间。

52. 发明授权

US5963483A Synchronous memory unit 失效
标题翻译：同步存储单元
公开(公告)号：US5963483A
公开(公告)日：1999-10-05
申请号：US133952
申请日：1998-08-14
申请人： Hideharu Yahata , Kenichi Fukui , Yoji Nishio , Atsushi Hiraishi , Sadayuki Morita
发明人： Hideharu Yahata , Kenichi Fukui , Yoji Nishio , Atsushi Hiraishi , Sadayuki Morita
IPC分类号： G11C7/10 , G11C7/22 , G11C7/00
CPC分类号： G11C7/22 , G11C7/1072
摘要： A synchronous memory unit which includes a plurality of input buffers for receiving address data, a plurality of input latches for holding and outputting address data from in the input buffers according to a clock signal, a plurality of decoders for decoding the address data from the input latches, and a memory cell array having a plurality of memory cells which store and output data signals via bit lines according to the address data decoded by the decoders. Also provided are a sense amplifier for amplifying the output data signals on the bit lines, a selector for selecting one of the amplified output data signals according to the address data decoded by the decoders, and a selector output latch for holding and outputting the amplified output data signal from the selector according to the clock signal. An output latch holds and outputs the amplified output data signal from the selector output latch according to the clock signal. An output buffer receives and outputs the amplified output data signal from the output latch. Each latch includes a first latch for holding and outputting a data signal according to the clock signal, a first switch connected to the first latch for allowing a data signal to pass to the first latch according to the clock signal, and a second latch for holding and outputting a data signal according to the clock signal, and a second switch, connected between the first and second latches, for allowing a data signal to pass from the first latch to the second latch according to the clock signal.
摘要翻译：一种同步存储单元，包括用于接收地址数据的多个输入缓冲器，用于根据时钟信号从输入缓冲器中保存和输出地址数据的多个输入锁存器，用于从输入端解码地址数据的多个解码器锁存器和具有多个存储器单元的存储单元阵列，存储单元根据解码器解码的地址数据经由位线存储和输出数据信号。还提供了用于放大位线上的输出数据信号的读出放大器，用于根据由解码器解码的地址数据来选择放大的输出数据信号之一的选择器，以及用于保存并输出放大的输出的选择器输出锁存器来自选择器的数据信号根据时钟信号。输出锁存器根据时钟信号保存并输出来自选择器输出锁存器的放大输出数据信号。输出缓冲器从输出锁存器接收并输出放大的输出数据信号。每个锁存器包括用于根据时钟信号保持和输出数据信号的第一锁存器，连接到第一锁存器的第一开关，用于根据时钟信号使数据信号传送到第一锁存器;以及第二锁存器，用于保持并根据时钟信号输出数据信号，以及连接在第一和第二锁存器之间的第二开关，用于根据时钟信号允许数据信号从第一锁存器传递到第二锁存器。

53. 发明授权

US5313116A Semiconductor integrated circuit device having bipolar transistor and field effect transistor 失效
标题翻译：具有双极晶体管和场效应晶体管的半导体集成电路器件
公开(公告)号：US5313116A
公开(公告)日：1994-05-17
申请号：US765018
申请日：1991-09-24
申请人： Fumio Murabayashi , Yoji Nishio , Shoichi Kotoku , Kozaburo Kurita , Kazuo Kato
发明人： Fumio Murabayashi , Yoji Nishio , Shoichi Kotoku , Kozaburo Kurita , Kazuo Kato
IPC分类号： H01L29/73 , H01L21/331 , H01L21/82 , H01L27/06 , H01L27/118 , H01L29/732 , H03K17/04 , H03K17/16 , H03K17/567 , H03K19/00 , H03K19/003 , H03K19/08 , H03K19/0944 , H03K19/01
CPC分类号： H01L27/0623 , H03K19/001 , H03K19/00353 , H03K19/09448
摘要： A semiconductor integrated circuit device having a plurality of logic circuits integrated on a semiconductor substrate is provided which can operate with a power source potential difference substantially less than 5 V. The logic circuit includes a bipolar transistor having a base and its collector-emitter current path coupled between a first power source terminal and an output terminal, together with at least one field effect transistor having its gate responsive to an input signal applied to an input terminal and its source-drain current path coupled between the first power source terminal and the base of the bipolar transistor. A semiconductor switch means is also provided which is responsive to the input signal applied to the input terminal for performing ON/OFF operations complementary to the ON/OFF operations of the bipolar transistor and which has a current path between its paired main terminals coupled between the output terminal and the second power source terminal. In order to improve the operating speed, a potential difference reducing element is provided having a current path between its paired main terminals coupled between the first power source terminal and the output terminal for reducing the potential difference, which is present between the first power source terminal and the output terminal based on the base-emitter forward voltage of the bipolar transistor when the bipolar transistor is ON.
摘要翻译：提供了具有集成在半导体衬底上的多个逻辑电路的半导体集成电路器件，其可以以基本上小于5V的电源电位差工作。逻辑电路包括具有基极和其集电极 - 发射极电流路径的双极晶体管耦合在第一电源端子和输出端子之间，以及至少一个具有栅极的场效应晶体管，其响应于施加到输入端子的输入信号及其耦合在第一电源端子和基极之间的源极 - 漏极电流路径的双极晶体管。还提供一种半导体开关装置，其响应于施加到输入端子的输入信号，用于执行与双极晶体管的导通/截止操作互补的ON / OFF操作，并且在其双绞主端子之间具有电流通路输出端子和第二电源端子。为了提高工作速度，提供了一个电位差降低元件，其具有耦合在第一电源端子和输出端子之间的成对主端子之间的电流路径，用于减小电位差，该电位差存在于第一电源端子以及当双极晶体管导通时基于双极晶体管的基极 - 发射极正向电压的输出端子。

54. 发明授权

US5059821A Bi-CMOS driver with two CMOS predrivers having different switching thresholds 失效
标题翻译：具有两个具有不同开关阈值的CMOS预驱动器的双CMOS驱动器
公开(公告)号：US5059821A
公开(公告)日：1991-10-22
申请号：US649854
申请日：1991-02-01
申请人： Fumio Murabayashi , Yoji Nishio , Shoichi Kotoku , Kozaburo Kurita , Kazuo Kato
发明人： Fumio Murabayashi , Yoji Nishio , Shoichi Kotoku , Kozaburo Kurita , Kazuo Kato
IPC分类号： H01L29/73 , H01L21/331 , H01L21/82 , H01L27/06 , H01L27/118 , H01L29/732 , H03K17/04 , H03K17/16 , H03K17/567 , H03K19/00 , H03K19/003 , H03K19/08 , H03K19/0944
CPC分类号： H01L27/0623 , H03K19/001 , H03K19/00353 , H03K19/09448
摘要： A semiconductor integrated circuit device having a plurality of logic circuits integrated on a semiconductor substrate is provided which can operate with a power source potential difference substantially less than 5V. The logic circuit includes a bipolar transistor having a base and its collector-emitter current path coupled between a first power source terminal and an output terminal, together with at least one field effect transistor having its gate responsive to an input signal applied to an input terminal and its source-drain current path coupled between the first power source terminal and the base of the bipolar transistor. A semiconductor switch means is also provided which is responsive to the input signal applied to the input terminal for performing ON/OFF operations complementary to the ON/OFF operations of the bipolar transistor and which has a current path between its paired main terminals coupled between the output terminal and the second power source terminal. In order to improve the operating speed, a potential difference reducing element is provided having a current path between its paired main terminals coupled between the first power source terminal and the output terminal for reducing the potential difference, which is present between the first power source terminal and the output terminal based on the base-emitter forward voltage of the bipolar transistor when the bipolar transistor is ON.
摘要翻译：提供了具有集成在半导体衬底上的多个逻辑电路的半导体集成电路器件，其可以以基本上小于5V的电源电位差工作。逻辑电路包括双极晶体管，其具有耦合在第一电源端子和输出端子之间的基极和集电极 - 发射极电流路径，以及至少一个场效应晶体管，其栅极响应于施加到输入端子的输入信号并且其源极 - 漏极电流路径耦合在第一电源端子和双极晶体管的基极之间。还提供一种半导体开关装置，其响应于施加到输入端子的输入信号，用于执行与双极晶体管的导通/截止操作互补的ON / OFF操作，并且在其双绞主端子之间具有电流通路输出端子和第二电源端子。为了提高工作速度，提供了一个电位差降低元件，其具有耦合在第一电源端子和输出端子之间的成对主端子之间的电流路径，用于减小电位差，该电位差存在于第一电源端子以及当双极晶体管导通时基于双极晶体管的基极 - 发射极正向电压的输出端子。

55. 发明授权

US08953406B2 Semiconductor module includes semiconductor chip initialized by reset signal 有权
标题翻译：半导体模块包括由复位信号初始化的半导体芯片
公开(公告)号：US08953406B2
公开(公告)日：2015-02-10
申请号：US13455985
申请日：2012-04-25
申请人： Yoji Nishio , Takao Hirayama , Susumu Hatano , Haruki Nagahashi , Masashi Kawamura , Tadaaki Yoshimura
发明人： Yoji Nishio , Takao Hirayama , Susumu Hatano , Haruki Nagahashi , Masashi Kawamura , Tadaaki Yoshimura
IPC分类号： G11C8/00 , G06F13/40
CPC分类号： G06F13/4086
摘要： Disclosed herein is a device that includes a plurality of semiconductor chips mounted on a module substrate. Each of the semiconductor chips includes a reset terminal to which a reset signal is supplied, and an internal circuit that is initialized based on the reset signal. The module substrate includes a reset signal line connected commonly to the reset terminals of the semiconductor chips, and an anti-resonance element connected to the reset signal line.
摘要翻译：这里公开了一种装置，其包括安装在模块基板上的多个半导体芯片。每个半导体芯片包括提供复位信号的复位端子和基于复位信号而被初始化的内部电路。模块基板包括与半导体芯片的复位端子共同连接的复位信号线以及连接到复位信号线的反谐振元件。

56. 发明授权

US08738347B2 Method for extracting IBIS simulation model 有权
标题翻译：提取IBIS仿真模型的方法
公开(公告)号：US08738347B2
公开(公告)日：2014-05-27
申请号：US13354109
申请日：2012-01-19
申请人： Tadaaki Yoshimura , Yoji Nishio , Sadahiro Nonoyama , Koji Matsuo , Shinji Itano , Yoshiyuki Yagami
发明人： Tadaaki Yoshimura , Yoji Nishio , Sadahiro Nonoyama , Koji Matsuo , Shinji Itano , Yoshiyuki Yagami
IPC分类号： G06F17/50 , G06F3/06 , G06F5/06 , G06F5/16 , G06F7/78 , G06F9/54 , G06F13/16
CPC分类号： G06F3/0656 , G06F5/06 , G06F5/065 , G06F5/16 , G06F7/78 , G06F9/544 , G06F13/1673 , G06F17/50 , G06F17/5036 , G06F2003/0691 , G06F2205/062 , G06F2205/063 , G06F2205/066
摘要： A method for extracting an accurate IBIS simulation model of a semiconductor device including a plurality of semiconductor chips comprises: extracting an AC characteristics model of a first output buffer in an IBIS simulation model by treating first and second output buffers of first and second semiconductor chips connected to a single external connection terminal as a transistor model and executing a transistor-level circuit simulation; calculating an output capacitance model of the first output buffer as an IBIS simulation model by adding output capacitances of the first and second output buffers as a transistor-level circuit simulation model; and synthesizing an IBIS simulation model of the first output buffer viewed from the external connection terminal by using the AC characteristics model and the output capacitance model.
摘要翻译：一种用于提取包括多个半导体芯片的半导体器件的精确IBIS仿真模型的方法包括：通过处理连接的第一和第二半导体芯片的第一和第二输出缓冲器来提取IBIS仿真模型中的第一输出缓冲器的AC特征模型到单个外部连接端子作为晶体管模型并执行晶体管级电路仿真; 通过将第一和第二输出缓冲器的输出电容相加作为晶体管级电路仿真模型，计算第一输出缓冲器的输出电容模型作为IBIS仿真模型; 以及通过使用AC特性模型和输出电容模型，从外部连接端子合成第一输出缓冲器的IBIS仿真模型。

57. 发明授权

US08581649B2 Semiconductor device and information processing system 有权
标题翻译：半导体器件和信息处理系统
公开(公告)号：US08581649B2
公开(公告)日：2013-11-12
申请号：US12926255
申请日：2010-11-04
申请人： Yoji Nishio
发明人： Yoji Nishio
IPC分类号： H03K5/12
CPC分类号： H03K19/00384 , H03K19/00361
摘要： The semiconductor device includes an output driver and a characteristic switching circuit that switches characteristics of the output driver. The characteristic switching circuit mutually matches a rising time and a falling time of an output signal output from the output driver, when a power voltage supplied to a power line is a first voltage, with a rising time and a falling time of the output signal output from the output driver, when the power voltage supplied to the power line is a second voltage. As a result, an increase in an influence of a harmonic component or a crosstalk when the power voltage is reduced does not occur. Moreover, because a receiving condition on a receiver side does not change even when the power voltage is reduced, signal transmission and reception can be performed correctly irrespective of the power voltage.
摘要翻译：半导体器件包括输出驱动器和切换输出驱动器的特性的特征切换电路。当提供给电力线的电源电压是第一电压时，特性切换电路相互匹配从输出驱动器输出的输出信号的上升时间和下降时间，输出信号输出的上升时间和下降时间当输出驱动器提供给电力线的电源电压是第二电压时。结果，不会发生电力电压降低时的谐波成分或串扰的影响的增加。此外，由于即使电源电压降低，接收机侧的接收状态也不变化，所以无论电源电压如何，都可以正确地进行信号的发送和接收。

58. 发明授权

US08253029B2 Filter circuit element and electronic circuit device 有权
标题翻译：滤波电路元件和电子电路器件
公开(公告)号：US08253029B2
公开(公告)日：2012-08-28
申请号：US12450690
申请日：2008-04-09
申请人： Takashi Nakano , Masaharu Imazato , Yoji Nishio
发明人： Takashi Nakano , Masaharu Imazato , Yoji Nishio
IPC分类号： H05K1/18 , H05K1/11
CPC分类号： H01P1/20336 , H01P1/20363 , H05K1/0216 , H05K1/0219 , H05K1/0222 , H05K1/115 , H05K3/429 , H05K2201/09309 , H05K2201/09618 , H05K2201/09627
摘要： A plurality of vias is disposed side by side on a multilayer board. A first via which is one of the vias disposed at one outer portion is electrically connected to a first outgoing line provided on the multilayer board. A second via at the other outer portion is electrically connected to a second outgoing line provided on the multilayer board. A plurality of the vias is connected to a first fixed potential layer (a ground layer, for example) of the multilayer board. At least one second fixed potential layer is provided, with a plurality of the vias through a clearance and having the same potential as that of the first fixed potential layer, as an inner layer of the multilayer board between the first and second outgoing lines and the fixed potential layer. Therefore, a BPF whose rate of occupied area is low is formed on the multilayer board without additional production processes.
摘要翻译：多个通孔并排设置在多层板上。设置在一个外部部分的通孔之一的第一通孔电连接到设置在多层板上的第一输出线。在另一个外部部分的第二通道电连接到设置在多层板上的第二出线。多个通孔连接到多层板的第一固定电位层（例如，接地层）。提供至少一个第二固定电位层，其中多个通孔具有与第一固定电位层相同的间隙并具有相同的电位，作为第一和第二出射线之间的多层板的内层和固定电位层。因此，在多层板上形成占用面积小的BPF，而无需附加的制造工序。

59. 发明授权

US07656744B2 Memory module with load capacitance added to clock signal input 失效
标题翻译：负载电容加到时钟信号输入的存储模块
公开(公告)号：US07656744B2
公开(公告)日：2010-02-02
申请号：US11611036
申请日：2006-12-14
申请人： Yurika Aoki , Seiji Funaba , Yoji Nishio
发明人： Yurika Aoki , Seiji Funaba , Yoji Nishio
IPC分类号： G11C8/00
CPC分类号： G11C5/063 , G11C5/04
摘要： A novel memory module with a multiple-rank configuration is provided to solve the problem that high-speed operation is impossible due to the fact that timing of a data strobe signal input to a memory is deviated from timing of a clock signal input thereto. In the memory module, a load capacity is provided at the vicinity of a clock signal input pin of a phase-locked loop circuit where the clock signal is input to match a time constant of a data strobe signal line with a time constant of a clock signal line. The matching of the input timings of the clock signal and the data strobe signal input to the memory enables the memory module to operate at a high speed.
摘要翻译：提供了具有多级配置的新型存储器模块，以解决由于输入到存储器的数据选通信号的定时偏离输入到其的时钟信号的定时的事实而无法进行高速操作的问题。在存储器模块中，在锁存环路电路的时钟信号输入引脚附近提供负载能力，其中输入时钟信号以使数据选通信号线的时间常数与时钟的时间常数相匹配信号线。时钟信号的输入定时和输入到存储器的数据选通信号的匹配使得存储器模块能够以高速运行。

60. 发明申请

US20090115442A1 Semiconductor integrated circuit and electronic device 有权
公开(公告)号：US20090115442A1
公开(公告)日：2009-05-07
申请号：US12314291
申请日：2008-12-08
申请人： Seiji Funaba , Yoji Nishio
发明人： Seiji Funaba , Yoji Nishio
IPC分类号： G01R31/02
CPC分类号： G11C7/22 , G11C5/04 , G11C7/1045 , G11C7/222 , G11C11/4076 , G11C29/02 , G11C29/025 , G11C29/028 , G11C29/50012 , H05K1/0248 , H05K1/0268 , H05K1/14 , H05K2201/044 , H05K2201/09781
摘要： A dummy wiring 25 is provided for simulating an actual wiring 26 connecting semiconductor integrated circuits 2 and 6 on a circuit board. The semiconductor integrated circuit comprises a data output circuit 28 capable of variably setting the slew rate and a circuit 29 for measuring signal delay time between a signal sending point and a signal reflection point (characteristic impedance mismatching point) using the dummy wiring 25, and the delay time so obtained by the measuring circuit is used for the determination of the signal transition time of the output circuit. The transition time of the signal is set at least twice of the signal delay time between the signal sending point and the wiring branch at the nearest end. In this way, signal transmission with alleviated reflection by the reflection point at the nearest end is realized.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式