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51. 发明授权

US08896070B2 Patterning embedded control lines for vertically stacked semiconductor elements 有权
标题翻译：为垂直堆叠的半导体元件绘制嵌入式控制线
公开(公告)号：US08896070B2
公开(公告)日：2014-11-25
申请号：US13446462
申请日：2012-04-13
申请人： Hyung-Kyu Lee , YoungPil Kim , Peter Nicholas Manos , Maroun Khoury , Dadi Setiadi , Chulmin Jung , Hsing-Kuen Liou , Paramasiyan Kamatchi Subramanian , Yongchul Ahn , Jinyoung Kim , Antoine Khoueir
发明人： Hyung-Kyu Lee , YoungPil Kim , Peter Nicholas Manos , Maroun Khoury , Dadi Setiadi , Chulmin Jung , Hsing-Kuen Liou , Paramasiyan Kamatchi Subramanian , Yongchul Ahn , Jinyoung Kim , Antoine Khoueir
IPC分类号： H01L45/00 , H01L27/24 , H01L27/22 , H01L43/08 , H01L27/10
CPC分类号： H01L27/101 , H01L27/228 , H01L27/2454 , H01L27/2463 , H01L43/08 , H01L45/04 , H01L45/085 , H01L45/1233 , H01L45/1675
摘要： The present invention is generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure.
摘要翻译：本发明一般涉及用于垂直堆叠的半导体元件的具有嵌入式（底侧）控制线的装置。根据各种实施例，第一半导体晶片设置有第一面对表面，其上形成有第一导电层。第一半导体晶片被附接到第二半导体晶片以形成多晶片结构，第二半导体晶片具有形成第二导电晶片的第二相对表面。所述第一导电层与所述第二导电层接触地接合以在所述结构内形成嵌入的组合导电层。去除组合导电层的部分以形成多个间隔开的控制线，其以选定的长度或宽度尺寸延伸穿过所述结构。

52. 发明授权

US08289804B2 Semiconductor control line address decoding circuit 有权
标题翻译：半导体控制线地址解码电路
公开(公告)号：US08289804B2
公开(公告)日：2012-10-16
申请号：US13100967
申请日：2011-05-04
申请人： Chulmin Jung , Dadi Setiadi , YoungPil Kim , Harry Hongyue Liu , Hyung-Kyu Lee
发明人： Chulmin Jung , Dadi Setiadi , YoungPil Kim , Harry Hongyue Liu , Hyung-Kyu Lee
IPC分类号： G11C8/00
CPC分类号： G11C8/10
摘要： Apparatus and method for decoding addresses of control lines in a semiconductor device, such as a solid state memory (SSM). In accordance with some embodiments, a switching circuit includes an array of switching devices coupled to 2N output lines and M input lines, wherein M and N are respective non-zero integers and each output line has a unique N-bit address. A decoder circuit coupled to the switching circuit divides the N-bit address for a selected output line into a plurality of multi-bit subgroup addresses, and asserts the M input lines in relation to respective bit values of said subgroup addresses to apply a first voltage to the selected output line and to concurrently apply a second voltage to the remaining 2N−1 output lines.
摘要翻译：用于解码诸如固态存储器（SSM）的半导体器件中的控制线的地址的装置和方法。根据一些实施例，开关电路包括耦合到2N个输出线和M个输入线的开关器件阵列，其中M和N分别是非零整数，并且每个输出线具有唯一的N位地址。耦合到开关电路的解码器电路将所选择的输出线的N位地址划分为多个多位子组地址，并且相对于所述子组地址的各个位值断言M个输入线，以施加第一电压并且向剩余的2N-1个输出线同时施加第二电压。

53. 发明授权

US08192087B2 Microfabricated fluid dynamic bearing 有权
标题翻译：微型流体动力轴承
公开(公告)号：US08192087B2
公开(公告)日：2012-06-05
申请号：US12473243
申请日：2009-05-27
申请人： Roger L. Hipwell, Jr. , Alan L. Grantz , Dadi Setiadi , Yang Li
发明人： Roger L. Hipwell, Jr. , Alan L. Grantz , Dadi Setiadi , Yang Li
IPC分类号： F16C32/06
CPC分类号： G11B19/2036 , F16C17/105 , F16C33/107 , F16C2370/12
摘要： A fluid dynamic bearing formed by a microelectromechanical systems (MEMS) wafer-level batch-fabrication process is provided. The process results in a high performance and high reliability fluid dynamic bearing having features including higher bearing lifetime at high RPM, improved bearing stiffness, durability and thrust/restoring forces capabilities. The present invention is especially useful with small form factor disc drive memory devices having constraints in motor height, such as a 2.5 inch disc drive, requiring high performance including high rotational speed and large areal density. A sacrificial layer is utilized in the process to simultaneously form symmetrical facing surfaces of relatively rotatable components. The facing surfaces define, therebetween, a desired feature, such as a journal bearing, a thrust bearing, a fluid channel, a fluid reservoir, a capillary seal, pressure generating grooves, and other profile geometries. Such geometry control allows for design freedom in obtaining a desired bearing performance and stiffness.
摘要翻译：提供了由微机电系统（MEMS）晶圆级批量制造工艺形成的流体动力轴承。该过程产生了高性能和高可靠性的流体动力轴承，其特征包括在高转速下具有较高的轴承寿命，改进的轴承刚度，耐用性和推力/恢复力能力。本发明对于具有马达高度限制的小尺寸盘驱动器存储器件是特别有用的，例如2.5英寸盘驱动器，需要包括高旋转速度和大面密度的高性能。在该过程中利用牺牲层以同时形成相对可旋转部件的对称面对表面。相对的表面在它们之间限定期望的特征，例如轴颈轴承，推力轴承，流体通道，流体储存器，毛细管密封件，压力产生槽和其它轮廓几何形状。这种几何控制允许在获得期望的轴承性能和刚度方面的设计自由度。

54. 发明授权

US08125057B2 Magnetic shielding for integrated circuit 有权
标题翻译：集成电路磁屏蔽
公开(公告)号：US08125057B2
公开(公告)日：2012-02-28
申请号：US12498574
申请日：2009-07-07
申请人： Wayne Allen Bonin , Dadi Setiadi
发明人： Wayne Allen Bonin , Dadi Setiadi
IPC分类号： H01L23/552 , H05K9/00 , G11C7/02
CPC分类号： G11C5/005 , H01L23/552 , H01L2924/0002 , H01L2924/00
摘要： A shielded integrated circuit structure including an integrated circuit having a plurality of functional elements thereon, and a tiled array comprising a plurality of shielding elements, each functional element having one of the plurality of shielding elements proximate thereto. The shielding elements comprise a magnetic material having a saturation less than or equal to 20,000 gauss.
摘要翻译：一种屏蔽集成电路结构，包括其上具有多个功能元件的集成电路和包括多个屏蔽元件的平铺阵列，每个功能元件具有靠近其的多个屏蔽元件中的一个。屏蔽元件包括具有小于或等于20,000高斯的饱和的磁性材料。

55. 发明授权

US08050092B2 NAND flash memory with integrated bit line capacitance 有权
标题翻译：具有集成位线电容的NAND闪存
公开(公告)号：US08050092B2
公开(公告)日：2011-11-01
申请号：US12474463
申请日：2009-05-29
申请人： Chulmin Jung , Harry Hongyue Liu , Brian Lee , Yong Lu , Dadi Setiadi
发明人： Chulmin Jung , Harry Hongyue Liu , Brian Lee , Yong Lu , Dadi Setiadi
IPC分类号： G11C11/34 , G11C11/24
CPC分类号： G11C11/005 , G11C16/26 , G11C2216/14
摘要： Method and apparatus for outputting data from a memory array having a plurality of non-volatile memory cells arranged into rows and columns. In accordance with various embodiments, charge is stored in a volatile memory cell connected to the memory array, and the stored charge is subsequently discharged from the volatile memory cell through a selected column. In some embodiments, the volatile memory cell is a dynamic random access memory (DRAM) cell from a row of the cells with each DRAM cell along the row coupled to a respective column in the memory array, and each column of non-volatile memory cells comprises Flash memory cells connected in a NAND configuration.
摘要翻译：用于从具有排列成行和列的多个非易失性存储单元的存储器阵列输出数据的方法和装置。根据各种实施例，电荷被存储在连接到存储器阵列的易失性存储单元中，并且随后通过所选择的列从易失性存储器单元中释放存储的电荷。在一些实施例中，易失性存储器单元是来自单元行的动态随机存取存储器（DRAM）单元，每个DRAM单元沿着与存储器阵列中的相应列耦合的行，并且每列非易失性存储单元包括以NAND配置连接的闪存单元。

56. 发明授权

US08026732B2 Probe with bi-directional electrostatic actuation 失效
标题翻译：探头采用双向静电驱动
公开(公告)号：US08026732B2
公开(公告)日：2011-09-27
申请号：US12272128
申请日：2008-11-17
申请人： Dadi Setiadi , Wayne Bonin
发明人： Dadi Setiadi , Wayne Bonin
IPC分类号： G01R31/20
CPC分类号： G01R1/06733 , G01R1/06716 , G01R1/06744
摘要： A probe system that has a probe body comprising at least three arms extending from a central region and a probe tip centrally located on the probe body in the central region. A substrate is proximate the probe body opposite the probe tip. A first electrode is positioned to provide a centrally positioned voltage across the probe body and the substrate and a second electrode set is positioned radially outward from the first electrode, to provide an outer voltage across at least one of the at least three arms and the substrate. The probe structure may have, for example, four arms. Methods of actuating the probe tip are provided.
摘要翻译：探针系统，其具有探针体，该探针体包括从中心区域延伸的至少三个臂和在中心区域中心位于探针主体上的探针末端。衬底靠近与探针尖端相对的探针体。定位第一电极以提供穿过探针主体和衬底的中心定位的电压，并且第二电极组从第一电极径向向外定位，以提供穿过至少三个臂中的至少一个臂和衬底的外部电压。探针结构可以具有例如四个臂。提供致动探针尖端的方法。

57. 发明申请

US20110205830A1 Semiconductor Control Line Address Decoding Circuit 有权
标题翻译：半导体控制线地址解码电路
公开(公告)号：US20110205830A1
公开(公告)日：2011-08-25
申请号：US13100967
申请日：2011-05-04
申请人： Chulmin Jung , Dadi Setiadi , YoungPil Kim , Harry Hongyue Liu , Hyung-Kyu Lee
发明人： Chulmin Jung , Dadi Setiadi , YoungPil Kim , Harry Hongyue Liu , Hyung-Kyu Lee
IPC分类号： G11C8/10
CPC分类号： G11C8/10
摘要： Apparatus and method for decoding addresses of control lines in a semiconductor device, such as a solid state memory (SSM). In accordance with some embodiments, a switching circuit includes an array of switching devices coupled to 2N output lines and M input lines, wherein M and N are respective non-zero integers and each output line has a unique N-bit address. A decoder circuit coupled to the switching circuit divides the N-bit address for a selected output line into a plurality of multi-bit subgroup addresses, and asserts the M input lines in relation to respective bit values of said subgroup addresses to apply a first voltage to the selected output line and to concurrently apply a second voltage to the remaining 2N−1 output lines.
摘要翻译：用于解码诸如固态存储器（SSM）的半导体器件中的控制线的地址的装置和方法。根据一些实施例，开关电路包括耦合到2N个输出线和M个输入线的开关器件阵列，其中M和N分别是非零整数，并且每个输出线具有唯一的N位地址。耦合到开关电路的解码器电路将所选择的输出线的N位地址划分为多个多位子组地址，并且相对于所述子组地址的各个位值断言M个输入线，以施加第一电压并且向剩余的2N-1个输出线同时施加第二电压。

58. 发明授权

US07969812B2 Semiconductor control line address decoding circuit 有权
标题翻译：半导体控制线地址解码电路
公开(公告)号：US07969812B2
公开(公告)日：2011-06-28
申请号：US12502219
申请日：2009-07-13
申请人： Chulmin Jung , Dadi Setiadi , YoungPil Kim , Harry Hongyue Liu , Hyung-Kyu Lee
发明人： Chulmin Jung , Dadi Setiadi , YoungPil Kim , Harry Hongyue Liu , Hyung-Kyu Lee
IPC分类号： G11C8/00
CPC分类号： G11C8/10
摘要： Apparatus and method for decoding addresses of control lines in a semiconductor device, such as a solid state memory (SSM). In accordance with some embodiments, a switching circuit includes an array of switching devices coupled to 2N output lines and M input lines, wherein M and N are respective non-zero integers and each output line has a unique N-bit address. A decoder circuit coupled to the switching circuit divides the N-bit address for a selected output line into a plurality of multi-bit subgroup addresses, and asserts the M input lines in relation to respective bit values of said subgroup addresses to apply a first voltage to the selected output line and to concurrently apply a second voltage to the remaining 2N-1 output lines.
摘要翻译：用于解码诸如固态存储器（SSM）的半导体器件中的控制线的地址的装置和方法。根据一些实施例，开关电路包括耦合到2N个输出线和M个输入线的开关器件阵列，其中M和N分别是非零整数，并且每个输出线具有唯一的N位地址。耦合到开关电路的解码器电路将所选择的输出线的N位地址划分为多个多位子组地址，并且相对于所述子组地址的各个位值断言M个输入线，以施加第一电压并且向剩余的2N-1个输出线同时施加第二电压。

59. 发明授权

US07936057B2 High bandwidth package 有权
标题翻译：高带宽封装
公开(公告)号：US07936057B2
公开(公告)日：2011-05-03
申请号：US12264522
申请日：2008-11-04
申请人： Dadi Setiadi , Patrick Ryan
发明人： Dadi Setiadi , Patrick Ryan
IPC分类号： H01L23/02
CPC分类号： H01L23/367 , H01L23/3128 , H01L24/48 , H01L25/0657 , H01L25/18 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2225/0651 , H01L2225/0652 , H01L2225/06572 , H01L2225/06596 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Method and apparatus for constructing and operating a high bandwidth package in an electronic device, such as a data storage device. In some embodiments, a high bandwidth package comprises a first known good die that has channel functions, a second known good die that has a controller function, and a third known good die that has a buffer function. Further in some embodiments, the high bandwidth package has pins that connect to each of the first, second, and third dies.
摘要翻译：在诸如数据存储设备的电子设备中构造和操作高带宽封装的方法和装置。在一些实施例中，高带宽封装包括具有通道功能的第一已知的良好裸片，具有控制器功能的第二已知的裸片以及具有缓冲功能的第三已知的裸片。此外，在一些实施例中，高带宽封装具有连接到第一，第二和第三裸片中的每一个的引脚。

60. 发明申请

US20110007540A1 MAGNETIC SHIELDING FOR INTEGRATED CIRCUIT 有权
标题翻译：集成电路磁屏蔽
公开(公告)号：US20110007540A1
公开(公告)日：2011-01-13
申请号：US12498574
申请日：2009-07-07
申请人： Wayne Allen Bonin , Dadi Setiadi
发明人： Wayne Allen Bonin , Dadi Setiadi
IPC分类号： G11C7/02 , H05K9/00
CPC分类号： G11C5/005 , H01L23/552 , H01L2924/0002 , H01L2924/00
摘要： A shielded integrated circuit structure including an integrated circuit having a plurality of functional elements thereon, and a tiled array comprising a plurality of shielding elements, each functional element having one of the plurality of shielding elements proximate thereto. The shielding elements comprise a magnetic material having a saturation less than or equal to 20,000 gauss.
摘要翻译：一种屏蔽集成电路结构，包括其上具有多个功能元件的集成电路和包括多个屏蔽元件的平铺阵列，每个功能元件具有靠近其的多个屏蔽元件中的一个。屏蔽元件包括具有小于或等于20,000高斯的饱和的磁性材料。

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