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51. 发明授权

US07453739B2 Semiconductor integrated circuit adapted to output pass/fail results of internal operations 有权
标题翻译：半导体集成电路适用于输出内部操作的通过/失败结果
公开(公告)号：US07453739B2
公开(公告)日：2008-11-18
申请号：US11742600
申请日：2007-05-01
申请人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
发明人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
IPC分类号： G11C7/10
CPC分类号： G11C16/3459 , G06F3/0659 , G06F12/0246 , G11C7/065 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1063 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/26 , G11C2207/104 , G11C2216/14
摘要： In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.
摘要翻译：在半导体集成电路中，内部电路能够同时执行第一操作和第二操作，并且输出电路向半导体集成电路的外部输出指示是否正在执行第一操作的信息以及指示是否或者不是第二操作是可执行的。

52. 发明申请

US20080200490A1 Alpha-(Aryl-or Heteroaryl-Methyl)-Beta-Piperidino Propanamide Compounds as Orl-1-Receptor Antagonists 审中-公开
标题翻译： α-（芳基或杂芳基 - 甲基） - 哌啶子基丙酰胺化合物作为Orl-1受体拮抗剂
公开(公告)号：US20080200490A1
公开(公告)日：2008-08-21
申请号：US11917218
申请日：2006-06-09
申请人： Yoshinobu Hashizume , Masako Hirota , Sachiko Mihara , Hiroshi Nakamura , Hiroki Koike , Yukari Matsumoto
发明人： Yoshinobu Hashizume , Masako Hirota , Sachiko Mihara , Hiroshi Nakamura , Hiroki Koike , Yukari Matsumoto
IPC分类号： A61K31/438 , C07D491/20 , A61P35/04
CPC分类号： C07D451/06
摘要： This invention provides the compounds of formula (I), or a pharmaceutically acceptable salt thereof, wherein R1 and R2 independently represent hydrogen or the like; R3 and R4 independently represents hydrogen or the like; R5 represents aryl or the like; —X—Y— represents —CH2O— or the like; and n represents 0, 1 or 2. These compounds have ORL1-receptor antagonist activity; and therefore, are useful to treat diseases or conditions such as pain, various CNS diseases etc.
摘要翻译：本发明提供式（I）化合物或其药学上可接受的盐，其中R 1和R 2独立代表氢或类似物; R 3和R 4独立地表示氢等; R 5表示芳基等; -X-Y-表示-CH 2 O-等; 并且n表示0,1或2.这些化合物具有ORL1受体拮抗剂活性; 因此，可用于治疗诸如疼痛，各种CNS疾病等疾病或病症。

53. 发明授权

US07380718B2 Method for reading out symbol information and device for reading out symbol information 有权
标题翻译：用于读出符号信息的方法和用于读出符号信息的装置
公开(公告)号：US07380718B2
公开(公告)日：2008-06-03
申请号：US11316546
申请日：2005-12-21
申请人： Hiroshi Nakamura
发明人： Hiroshi Nakamura
IPC分类号： G06K7/10
CPC分类号： G06K7/1456 , G06K7/14 , G06K7/1486
摘要： To provide a method for reading out symbol information and a device for reading out symbol information which are able to prevent a decline in decoding reliability by reducing noise caused by a quantized error, localized contaminations or the like. The method for reading out symbol information may comprise a process in which the image data, obtained by imaging the symbol information such as bar codes and the like, are converted to corrected image data having zero angle of inclination; a smoothing process in which the corrected image data are smoothed; and a column specifying process in which breakpoints of said symbol information column are specified by computing the total sum in the row direction on the smoothed corrected image data.
摘要翻译：提供一种读出符号信息的方法和用于读出能够通过减少由量化误差，局部污染等引起的噪声而能够防止解码可靠性下降的符号信息的装置。用于读出符号信息的方法可以包括将通过对诸如条形码等的符号信息进行成像而获得的图像数据转换为具有零倾角的校正图像数据的处理; 平滑处理，其中校正的图像数据被平滑化; 以及列指定处理，其中通过计算平滑校正图像数据上的行方向上的总和来指定所述符号信息列的断点。

54. 发明授权

US07379340B2 Sense amplifier circuit in non-volatile semiconductor memory comprising a boosting capacitor for boosting the potential at sense node 有权
标题翻译：非易失性半导体存储器中的感测放大器电路，包括用于升高感测节点处的电位的升压电容器
公开(公告)号：US07379340B2
公开(公告)日：2008-05-27
申请号：US11318524
申请日：2005-12-28
申请人： Koji Hosono , Hiroshi Nakamura , Ken Takeuchi , Kenichi Imamiya
发明人： Koji Hosono , Hiroshi Nakamura , Ken Takeuchi , Kenichi Imamiya
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C16/0483 , G11C5/145 , G11C7/1006 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/10 , G11C16/24 , G11C16/26 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642 , G11C2211/5643
摘要： A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has first and second latches that are selectively connected to the memory cell array and transfer data. A controller controls the reprogramming and retrieval circuits on a data-reprogramming operation to and a data-retrieval operation from the memory cell array. Each reprogramming and retrieval circuit has a multilevel logical operation mode and a caching operation mode. In the multilevel logical operation mode, re-programming and retrieval of upper and lower bits of two-bit four-level data is performed using the first and the second latches to store the two-bit four-level data in one of the memory cells in a predetermined threshold level range. In the caching operation mode, data transfer between one of the memory cells selected in accordance with a first address and the first latch is performed while data transfer is performed between the second latch and input/output terminals in accordance with a second address with respect to one-bit two-level data to be stored in one of the memory cells.
摘要翻译：非易失性半导体器件具有存储单元阵列，其具有电可擦除可编程非易失性存储器单元，重新编程和检索电路，其临时存储要存储在存储单元阵列中的要编程的数据并感测从存储器单元阵列检索的数据。每个重新编程和检索电路具有选择性地连接到存储单元阵列和传送数据的第一和第二锁存器。控制器控制数据重新编程操作中的重新编程和检索电路以及来自存储单元阵列的数据检索操作。每个重新编程和检索电路都具有多级逻辑操作模式和缓存操作模式。在多级逻辑操作模式中，使用第一和第二锁存器来执行二位四电平数据的高位和低位的重新编程和检索，以将两位四电平数据存储在存储单元之一中在预定的阈值电平范围内。在高速缓存操作模式中，根据第一地址选择的存储器单元之一和第一锁存器之间的数据传输是在第二锁存器和输入/输出端子之间根据第二地址相对于要存储在其中一个存储单元中的一位二电平数据。

55. 发明授权

US07371102B2 Lock structure of connector 失效
标题翻译：连接器的锁结构
公开(公告)号：US07371102B2
公开(公告)日：2008-05-13
申请号：US11178591
申请日：2005-07-12
申请人： Nobuyuki Sakamoto , Shigeru Tanaka , Hiroshi Nakamura , Makoto Yamanashi , Atsushi Nishida , Masato Minakata , Hiroshi Kobayashi
发明人： Nobuyuki Sakamoto , Shigeru Tanaka , Hiroshi Nakamura , Makoto Yamanashi , Atsushi Nishida , Masato Minakata , Hiroshi Kobayashi
IPC分类号： H01R13/627
CPC分类号： H01R13/6275 , H01R13/639
摘要： In a connector lock structure 1 provided at female and male connectors which can be fitted together, the female connector 2 has an engagement portion 14, and a slide lock member 13 is supported on the male connector 3 so as to move at least in connector-inserting and connector-withdrawing directions. The slide lock member 13 includes a retaining portion 16 for engagement with the engagement portion 14, and urging member 36 for urging the slide lock member 13. When the engagement portion 14 reaches an engagement position where it is engaged with the retaining portion 16 at the time when the female and male connectors are completely fitted together, the slide lock member 13 is automatically moved by the urging member 36, so that the retaining portion 16 is engaged with the engagement portion 14.
摘要翻译：在设置在可以装配在一起的阴连接器和公连接器的连接器锁定结构1中，阴连接器2具有接合部14，并且滑动锁定构件13被支撑在阳连接器3上，以便至少在连接器 - 插入和连接器撤回方向。滑动锁定构件13包括用于与接合部分14接合的保持部分16和用于推动滑动锁定构件13的推动构件36。当接合部分14在阴和阳连接器完全装配在一起时达到与保持部分16接合的接合位置时，滑动锁定构件13被推动构件36自动移动，使得保持部分16与接合部分14接合。

56. 发明授权

US07335937B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US07335937B2
公开(公告)日：2008-02-26
申请号：US10914422
申请日：2004-08-10
申请人： Hiroshi Nakamura , Kenichi Imamiya
发明人： Hiroshi Nakamura , Kenichi Imamiya
IPC分类号： H01L29/76
CPC分类号： H01L27/11526 , G11C11/5621 , G11C16/0483 , G11C16/26 , H01L27/115 , H01L27/11529 , H01L2924/0002 , H01L2924/00
摘要： In an EEPROM consisting of a NAND cell in which a plurality of memory cells are connected in series, the control gate voltage Vread of the memory cell in a block selected by the data read operation is made different from the each of the voltages Vsg1, Vsg2 of the select gate of the select transistor in the selected block so as to make it possible to achieve a high speed reading without bringing about the breakdown of the insulating film interposed between the select gate and the channel of the select transistor. The high speed reading can also be made possible in the DINOR cell, the AND cell, NOR cell and the NAND cell having a single memory cell connected thereto, if the control gate voltage of the memory cell is made different from the voltage of the select gate of the select transistor.
摘要翻译：在由多个存储单元串联连接的NAND单元组成的EEPROM中，通过数据读取操作选择的块中的存储单元的控制栅极电压V SUB读取不同于所选块中选择晶体管的选择栅极的电压V SUB，V S s2，...，以使得可以实现高速读取而不带来关于介于选择栅极和选择晶体管的沟道之间的绝缘膜的击穿。如果使存储器单元的控制栅极电压与选择的电压不同，则也可以在DINOR单元，AND单元，NOR单元和与其连接的单个存储单元的NAND单元中实现高速读数。选择晶体管的栅极。

57. 发明授权

US07330643B2 Information record medium, apparatus for recording the same and apparatus for reproducing the same 有权
标题翻译：信息记录媒体，记录装置及其再生装置
公开(公告)号：US07330643B2
公开(公告)日：2008-02-12
申请号：US10452376
申请日：2003-06-03
申请人： Takao Sawabe , Tokihiro Takahashi , Junichi Yoshio , Hidehiro Ishii , Hiroshi Nakamura , Kaoru Yamamoto , Akihiro Tozaki
发明人： Takao Sawabe , Tokihiro Takahashi , Junichi Yoshio , Hidehiro Ishii , Hiroshi Nakamura , Kaoru Yamamoto , Akihiro Tozaki
IPC分类号： H04N7/00 , H04N5/00
CPC分类号： G11B27/105 , G11B20/10527 , G11B27/034 , G11B2020/10592 , G11B2220/2562 , H04N5/85 , H04N9/8042 , H04N9/8063 , H04N9/8205 , H04N9/8227
摘要： An information record medium (1: DVD) has a record track (1a) to be reproduced by an information reproducing apparatus (S2). The information reproducing apparatus is provided with a read device (80) and reproduces audio information by a predetermined audio frame unit while relatively moving the read device along the record track recorded with at least the audio information by the audio frame unit. A plurality of audio packets (43, 202) are arranged along the record track, in each of which audio information pieces (207) constructing the audio information sampled by a predetermined sampling frequency and audio control information (203) for controlling a reproduction of the audio information pieces by the information reproducing apparatus are respectively recorded. The audio control information is provided with time management information (203f: PTS) for specifying a time, by a predetermined specification frequency, to manage a timing of outputting the audio information, which is included in the audio frame which head is positioned in the audio packet including the audio control information, in the reproduction by the information reproducing apparatus.
摘要翻译：信息记录介质（1：DVD）具有要由信息再现装置再现的记录磁道（1a）（S 2）。信息再现装置具有读取装置（80），并且通过预定音频帧单元再现音频信息，同时沿着由音频帧单元至少记录有音频信息的记录轨道相对移动读取装置。沿着记录轨道布置多个音频分组（43,42），其中每个音频信息片段（207）构成由预定采样频率采样的音频信息，音频控制信息（203）用于控制分别记录信息再现装置的音频信息。音频控制信息被提供有用于指定时间的时间管理信息（203f：PTS）以预定的指定频率来管理输出音频信息的定时，该定时包括在头部位于音频数据包包括音频控制信息。

58. 发明申请

US20080031056A1 Semiconductor memory device having a plurality of chips and capability of outputting a busy signal 有权
标题翻译：具有多个芯片的半导体存储器件和输出忙信号的能力
公开(公告)号：US20080031056A1
公开(公告)日：2008-02-07
申请号：US11904565
申请日：2007-09-27
申请人： Hiroshi Nakamura , Kenichi Imamiya , Ken Takeuchi
发明人： Hiroshi Nakamura , Kenichi Imamiya , Ken Takeuchi
IPC分类号： G11C7/06
CPC分类号： G11C16/04 , G11C5/143 , G11C7/1006 , G11C7/1051 , G11C7/1063 , G11C7/1072 , G11C7/1078 , G11C7/20 , G11C7/22 , G11C16/20
摘要： One package contains a plurality of memory chips. Each memory chip has an I/O terminal which generates a busy signal. The busy signal enables a busy state when a power supply voltage value reaches a specified and guaranteed range after a power-on sequence. The busy signal maintains the busy state until completion of initialization operations for, the plurality of memory chips. The busy signal releases the busy state after completion of all initialization operations for the plurality of memory chips.
摘要翻译：一个包装包含多个存储器芯片。每个存储器芯片具有产生忙信号的I / O端子。当电源电压值在上电序列之后达到指定和保证的范围时，忙信号使能忙状态。忙信号保持忙状态直到完成多个存储器芯片的初始化操作。在完成多个存储器芯片的所有初始化操作之后，忙信号释放忙状态。

59. 发明申请

US20080019190A1 Nonvolatile Semiconductor Memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20080019190A1
公开(公告)日：2008-01-24
申请号：US11829320
申请日：2007-07-27
申请人： Hiroshi Watanabe , Hiroshi Nakamura , Kazuhiro Shimizu , Seiichi Aritome , Toshitake Yaegashi , Yuji Takeuchi , Kenichi Imamiya , Ken Takeuchi , Hideko Oodaira
发明人： Hiroshi Watanabe , Hiroshi Nakamura , Kazuhiro Shimizu , Seiichi Aritome , Toshitake Yaegashi , Yuji Takeuchi , Kenichi Imamiya , Ken Takeuchi , Hideko Oodaira
IPC分类号： G11C16/06
CPC分类号： H01L27/11521 , G11C16/0483 , G11C16/10 , H01L27/105 , H01L27/115 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.
摘要翻译：选择栅极晶体管具有由第一级导电层和第二级导电层构成的选择栅电极。第一级导电层具有接触区域。第二级导电层的部分被去除，位于接触区域上方。在列方向上彼此相邻的两个相邻的选择栅电极被布置成使得一个选择栅电极的接触区域不与另一个选择栅电极的接触区域相对。一个选择栅电极在其与另一个选择栅电极的接触区域相对的部分中移除其第一和第二级导电层。

60. 发明申请

US20070278555A1 NON VOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非挥发性半导体存储器件
公开(公告)号：US20070278555A1
公开(公告)日：2007-12-06
申请号：US11756936
申请日：2007-06-01
申请人： Michio Nakagawa , Hiroshi Nakamura
发明人： Michio Nakagawa , Hiroshi Nakamura
IPC分类号： H01L29/76
CPC分类号： G11C16/08
摘要： A non volatile semiconductor memory device wherein it is possible to transfer Vpp without a drop in voltage of the transfer transistor Vth (threshold voltage) in a transfer circuit or decoder circuit for selectively transferring Vpp by using a usual LVP (low voltage P type transistor) to reduce step(s) of production process and costs. An LVP (low voltage P type transistor) instead of a HVP (high voltage P type transistor) for a transfer circuit is used. Two-way diodes each of which threshold value becomes about Vdd are inserted between the gate and the drain.
摘要翻译：一种非易失性半导体存储器件，其中可以在用于通过使用通常的LVP（低电压P型晶体管）选择性地传输Vpp的传输电路或解码器电路中传输Vpp而不会传输晶体管Vth的电压下降（阈值电压）以减少生产过程和成本的步骤。使用LVP（低电压P型晶体管）代替用于传输电路的HVP（高压P型晶体管）。阈值变为约Vdd的双向二极管插入在栅极和漏极之间。

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