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51. 发明申请

US20060187706A1 2-Transistor floating-body dram 有权
标题翻译： 2晶体管浮体电容
公开(公告)号：US20060187706A1
公开(公告)日：2006-08-24
申请号：US11008666
申请日：2005-02-22
申请人： Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Vivek De
发明人： Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Vivek De
IPC分类号： G11C11/34
CPC分类号： G11C11/405 , H01L21/84 , H01L27/108 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： A dynamic random access memory includes a cell having a circuit between a floating-body transistor and a bit line. Activation of the circuit is controlled to provide isolation between the floating body and bit-line voltage both during write operations and during times when the cell is unselected. The added isolation improves performance, for example, by reducing the need for gate-to-body coupling and the magnitude of voltage swings between the bit lines.
摘要翻译：动态随机存取存储器包括具有浮体晶体管和位线之间的电路的单元。控制电路的激活以在写入操作期间和在单元未被选择的时间期间在浮体和位线电压之间提供隔离。增加的隔离可以提高性能，例如，通过减少门到体耦合的需要和位线之间的电压摆幅的大小。

52. 发明申请

US20060139995A1 One time programmable memory 审中-公开
标题翻译：一次可编程存储器
公开(公告)号：US20060139995A1
公开(公告)日：2006-06-29
申请号：US11027476
申请日：2004-12-28
申请人： Ali Keshavarzi , Fabrice Paillet , Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Stephen Tang , Mohsen Alavi , Vivek De
发明人： Ali Keshavarzi , Fabrice Paillet , Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Stephen Tang , Mohsen Alavi , Vivek De
IPC分类号： G11C11/34
CPC分类号： G11C17/146 , G11C17/12
摘要： A one time programmable memory includes isolated gate transistors that may be programmed by subjecting the isolated gate transistors to voltage conditions that degrade characteristics of the isolated gate transistors. The degraded characteristics may be sensed to read the memory.
摘要翻译：一次性可编程存储器包括隔离栅极晶体管，其可以通过使隔离栅极晶体管受到降低隔离栅极晶体管特性的电压条件而被编程。可以感测劣化的特性以读取存储器。

53. 发明申请

US20060098482A1 Floating-body dynamic random access memory with purge line 失效
公开(公告)号：US20060098482A1
公开(公告)日：2006-05-11
申请号：US11289621
申请日：2005-11-30
申请人： Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Vivek De
发明人： Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Vivek De
IPC分类号： G11C11/34
CPC分类号： H01L27/108 , G11C11/404
摘要： Embodiments relate to a Floating Body Dynamic Random Access Memory (FBDRAM). The FBDRAM utilizes a purge line to reset a FBDRAM cell, prior to writing data to the FBDRAM cell.

54. 发明申请

US20050285616A1 Overvoltage detection apparatus, method, and system 有权
标题翻译：过电压检测装置，方法和系统
公开(公告)号：US20050285616A1
公开(公告)日：2005-12-29
申请号：US10880337
申请日：2004-06-29
申请人： Ali Keshavarzi , Fabrice Paillet , Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Stephen Tang , Mohsen Alavi , Vivek De
发明人： Ali Keshavarzi , Fabrice Paillet , Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Stephen Tang , Mohsen Alavi , Vivek De
IPC分类号： G01R19/165 , G01R31/26
CPC分类号： G01R31/2621 , G01R19/16571
摘要： A transistor may have degraded characteristics because of an overvoltage condition. The degraded characteristics may be sensed to determine that the transistor has previously been subjected to an overvoltage condition.
摘要翻译：由于过电压状态，晶体管可能具有劣化特性。可以感测劣化特性以确定晶体管先前已经经受过压状态。

55. 发明申请

US20050146921A1 1P1N 2T gain cell 有权
标题翻译： 1P1N 2T增益电池
公开(公告)号：US20050146921A1
公开(公告)日：2005-07-07
申请号：US10749734
申请日：2003-12-30
申请人： Yibin Ye , Dinesh Somasekhar , Muhammad Khellah , Fabrice Paillet , Stephen Tang , Ali Keshavarzi , Shih-Lien Lu , Vivek De
发明人： Yibin Ye , Dinesh Somasekhar , Muhammad Khellah , Fabrice Paillet , Stephen Tang , Ali Keshavarzi , Shih-Lien Lu , Vivek De
IPC分类号： G11C11/24 , G11C11/405
CPC分类号： G11C11/405
摘要： A two-transistor DRAM cell includes an NMOS device and a PMOS device coupled to the NMOS device.
摘要翻译：双晶体管DRAM单元包括耦合到NMOS器件的NMOS器件和PMOS器件。

56. 发明申请

US20050145935A1 Memory cell without halo implant 失效
标题翻译：无光晕植入的记忆细胞
公开(公告)号：US20050145935A1
公开(公告)日：2005-07-07
申请号：US10750566
申请日：2003-12-31
申请人： Ali Keshavarzi , Stephen Tang , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Vivek De
发明人： Ali Keshavarzi , Stephen Tang , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Vivek De
IPC分类号： G11C11/404 , H01L21/8239 , H01L27/02 , H01L27/105 , H01L27/108 , H01L29/76
CPC分类号： G11C11/404 , G11C2211/4016 , H01L27/0207 , H01L27/0214 , H01L27/105 , H01L27/1052 , H01L27/108
摘要： Some embodiments provide a memory cell comprising a body region doped with charge carriers of a first type, a source region disposed in the body region and doped with charge carriers of a second type, and a drain region disposed in the body region and doped with charge carriers of the second type. According to some embodiments, the body region, the source region, and the drain region are oriented in a first direction, the body region and the source region form a first junction, and the body region and the drain region form a second junction. Moreover, a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased. Some embodiments further include a transistor oriented in a second direction, wherein the second direction is not parallel to the first direction.
摘要翻译：一些实施例提供一种存储单元，其包括掺杂有第一类型的电荷载体的体区，设置在体区中的源极区，并掺杂有第二类型的电荷载流子，以及设置在体区中的掺杂电荷第二种载体。根据一些实施例，身体区域，源区域和漏极区域在第一方向上定向，身体区域和源区域形成第一结，并且体区域和漏区域形成第二结。此外，在第一结无偏置的情况下，从体区到源极区的第一结的导电率基本上小于从体区到漏区的第二结的导电率，在第二结是不偏不倚的一些实施例还包括在第二方向上取向的晶体管，其中第二方向不平行于第一方向。

57. 发明申请

US20050105342A1 Floating-body dram with two-phase write 失效
标题翻译：浮动车身两相写
公开(公告)号：US20050105342A1
公开(公告)日：2005-05-19
申请号：US10716755
申请日：2003-11-19
申请人： Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Vivek De
发明人： Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Vivek De
IPC分类号： G11C5/00 , G11C7/00 , G11C11/404 , G11C11/4076 , G11C11/408 , G11C11/4094
CPC分类号： G11C11/4094 , G11C11/404 , G11C11/4076 , G11C11/4085
摘要： A row of floating-body single transistor memory cells is written to in two phases.
摘要翻译：一行浮体单晶体管存储单元分两个阶段写入。

58. 发明授权

US06683467B1 Method and apparatus for providing rotational burn-in stress testing 失效
标题翻译：提供旋转老化压力测试的方法和装置
公开(公告)号：US06683467B1
公开(公告)日：2004-01-27
申请号：US09672689
申请日：2000-09-29
申请人： Ali Keshavarzi , David M. Wu , Yibin Ye , Vivek K. De
发明人： Ali Keshavarzi , David M. Wu , Yibin Ye , Vivek K. De
IPC分类号： G01R3102
CPC分类号： G01R31/2817
摘要： A method and device are provided for stress testing a chip. The chip may be partitioned into at least a first block and a second block. Burn-in stress testing may be performed on electronic devices within the first block without simultaneously performing burn-in stress testing on electronic devices within the second block. A burn-in stress testing device may perform the burn-in testing. A control device may be coupled to the burn-in stress testing device to enable burn-in stress testing on electronic devices within at least the first block of the chip without simultaneously enabling burn-in stress testing on the second block of the chip.
摘要翻译：提供了一种用于芯片压力测试的方法和装置。芯片可以被划分成至少第一块和第二块。老化压力测试可以在第一块内的电子设备上执行，而不对第二块内的电子设备进行同时进行老化压力测试。老化压力测试装置可执行老化测试。控制装置可以耦合到老化压力测试装置，以在芯片的至少第一块内的电子装置上实现耐久性测试，而不必在芯片的第二块上同时进行老化压力测试。

59. 发明授权

US06181608B2 Dual Vt SRAM cell with bitline leakage control 有权
标题翻译：双Vt SRAM单元，具有位线泄漏控制
公开(公告)号：US06181608B2
公开(公告)日：2001-01-30
申请号：US09261915
申请日：1999-03-03
申请人： Ali Keshavarzi , Kevin Zhang , Yibin Ye , Vivek K. De
发明人： Ali Keshavarzi , Kevin Zhang , Yibin Ye , Vivek K. De
IPC分类号： G11C1134
CPC分类号： G11C11/412 , G11C11/418
摘要： In some embodiments, the invention includes an integrated circuit including a bitline and a bitline#, wordlines, and memory cells. The memory cells each corresponding to one of the wordlines and each include first and second pass transistors coupled between first and second storage nodes, respectively, and the bitline and bitline#, respectively, the corresponding wordline being coupled to gates of the first and second pass transistors. The memory cells include first and second inverters cross-coupled between the first and second storage nodes, wherein the first and second pass transistors each have a lower threshold voltage than do transistors of the first and second inverters. Wordline voltage control circuitry coupled to the wordlines selectively controls wordline signals on the wordlines. In some embodiments, the wordline voltage control circuitry asserts the wordline signal for a selected wordline corresponding to a memory cell selected to be read and underdrives the wordline signals for the wordlines not corresponding to the selected memory cell.
摘要翻译：在一些实施例中，本发明包括包括位线和位线＃，字线和存储器单元的集成电路。每个对应于一个字线的存储单元分别包括分别耦合在第一和第二存储节点之间的第一和第二传输晶体管，位线和位线＃分别耦合到第一和第二通道的栅极晶体管。存储单元包括交叉耦合在第一和第二存储节点之间的第一和第二反相器，其中第一和第二传输晶体管每个具有比第一和第二反相器的晶体管更低的阈值电压。耦合到字线的字线电压控制电路有选择地控制字线上的字线信号。在一些实施例中，字线电压控制电路为对应于被选择要读取的存储器单元选择的字线断言字线信号，并驱动不对应于所选存储单元的字线的字线信号。

60. 发明授权

US06519176B1 Dual threshold SRAM cell for single-ended sensing 失效
标题翻译：用于单端感测的双阈值SRAM单元
公开(公告)号：US06519176B1
公开(公告)日：2003-02-11
申请号：US09675579
申请日：2000-09-29
申请人： Fatih Hamzaoglu , Ali Keshavarzi , Yibin Ye , Siva G. Narendra , Vivek K. De
发明人： Fatih Hamzaoglu , Ali Keshavarzi , Yibin Ye , Siva G. Narendra , Vivek K. De
IPC分类号： G11C1100
CPC分类号： G11C11/412
摘要： A six transistor SRAM cell for single-ended sensing is described along with related memory architecture. The cell comprises a bistable circuit connected to complementary bit lines through a pair of passgate transistors. One of the passgate transistors has a lower threshold voltage than the other transistor. The lower threshold voltage is used to couple the cell to a single-ended sense amplifier through one of the bit lines. In one embodiment fewer than all the bit lines in an array are precharged in order to reduce power consumption in the array.
摘要翻译：描述了用于单端感测的六晶体管SRAM单元以及相关的存储器架构。该单元包括通过一对通道晶体管连接到互补位线的双稳态电路。一个通道晶体管具有比另一个晶体管更低的阈值电压。较低的阈值电压用于通过其中一条位线将单元耦合到单端读出放大器。在一个实施例中，少于阵列中的所有位线被预充电以便减少阵列中的功耗。

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