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51. 发明授权

US08587336B2 Reconfigurable logic block, programmable logic device provided with the reconfigurable logic block, and method of fabricating the reconfigurable logic block 失效
标题翻译：可配置逻辑块，可配置逻辑块的可编程逻辑器件，以及制造可重构逻辑块的方法
公开(公告)号：US08587336B2
公开(公告)日：2013-11-19
申请号：US11598679
申请日：2006-11-14
申请人： Toshinori Sueyoshi , Masahiro Iida , Motoki Amagasaki , Kazuhiko Taketa , Taketo Heishi , Nobuharu Suzuki
发明人： Toshinori Sueyoshi , Masahiro Iida , Motoki Amagasaki , Kazuhiko Taketa , Taketo Heishi , Nobuharu Suzuki
IPC分类号： H03K19/173
CPC分类号： H03K19/17748 , H03K19/17728
摘要： A reconfigurable logic block has a first circuit that configures an arithmetic circuit and a second circuit that configures a circuit outside of the arithmetic circuit. A plurality of different circuits are configured by changing the settings of predetermined signals in the first and second circuits.
摘要翻译：可重配置逻辑块具有配置运算电路的第一电路和将运算电路外部的电路配置的第二电路。通过改变第一和第二电路中的预定信号的设置来配置多个不同的电路。

52. 发明申请

US20050091478A1 Processor using less hardware and instruction conversion apparatus reducing the number of types of instructions 审中-公开
标题翻译：处理器使用较少的硬件和指令转换设备减少指令类型的数量
公开(公告)号：US20050091478A1
公开(公告)日：2005-04-28
申请号：US10617506
申请日：2003-07-11
申请人： Shuichi Takayama , Kensuke Odani , Akira Tanaka , Nobuo Higaki , Masato Suzuki , Tetsuya Tanaka , Taketo Heishi , Shinya Miyaji
发明人： Shuichi Takayama , Kensuke Odani , Akira Tanaka , Nobuo Higaki , Masato Suzuki , Tetsuya Tanaka , Taketo Heishi , Shinya Miyaji
IPC分类号： G06F9/30 , G06F9/318 , G06F9/32 , G06F9/38 , G06F9/45 , G06F9/00
CPC分类号： G06F9/30058 , G06F8/447 , G06F9/30021 , G06F9/30072 , G06F9/30094 , G06F9/30145 , G06F9/30167 , G06F9/30181 , G06F9/3842
摘要： A processor which decodes and executes an instruction sequence includes: a state hold unit for holding, when a predetermined instruction is executed, a renewal state for an execution result of the predetermined instruction; an obtaining unit for obtaining an instruction sequence composed of instructions matching instructions assigned to an instruction set of the processor, where the instruction set is assigned first conditional instructions, a first state condition for a first conditional instruction being mutually exclusive with a second state condition for a second conditional instruction which has a same operation code as the first conditional instruction, the instruction set not being assigned the second conditional instruction, and the first state condition and the second state condition specifying either of one state and a plurality of states; a decoding unit for decoding each instruction in the obtained instruction sequence one by one; a judging unit for judging whether the renewal state is included in either of the state and the plurality of states specified by the first state condition in the first conditional instruction, when the decoding unit decodes the first conditional instruction; and an execution unit for executing, only if a judgement result by the judging unit is affirmative, an operation specified by the operation code in the first conditional instruction decoded by the decoding unit.
摘要翻译：解码并执行指令序列的处理器包括：状态保持单元，用于当执行预定指令时，保持所述预定指令的执行结果的更新状态; 获取单元，用于获得指令序列，所述指令序列由与分配给所述处理器的指令集的指令相匹配的指令组合，其中所述指令集被分配了第一条件指令;第一条件指令的第一状态条件与第二状态条件相互排斥，第二条件指令，其具有与第一条件指令相同的操作码，指令集不被分配第二条件指令，以及指定一个状态和多个状态中的一个状态和多个状态的第一状态条件和第二状态条件; 解码单元，用于逐个地解码所获得的指令序列中的每个指令; 判断单元，用于当解码单元解码第一条件指令时，判断更新状态是否包括在第一条件指令中由第一状态条件指定的状态和多个状态中的任一状态; 以及执行单元，用于仅当判断单元的判断结果为肯定时，执行由解码单元解码的第一条件指令中由操作码指定的操作。

53. 发明授权

US07877743B2 Program translation method and notifying instruction inserting method 有权
标题翻译：程序翻译方法和通知指令插入方法
公开(公告)号：US07877743B2
公开(公告)日：2011-01-25
申请号：US11595900
申请日：2006-11-13
申请人： Yoko Makiyori , Taketo Heishi , Akira Takuma
发明人： Yoko Makiyori , Taketo Heishi , Akira Takuma
IPC分类号： G06F9/44 , G06F9/45 , G06F11/00 , G06F15/00
CPC分类号： G06F8/41
摘要： The present invention comprises: a converting step for converting a source program into a machine language program; an inserting step for inserting notifying instructions for notifying that the source program has been executed in the machine language program; and a program generating step for generating the executable program from the machine language program in which the notifying instructions are inserted. Further, in the inserting step, the notifying instructions are placed at the entry points of each basic block that constitutes the machine language program and the notifying instructions to which the same conditions as those of the conditional instruction groups are granted are placed at the entry points of conditional instruction groups provided in the machine language program. In the program generating step, identification information for identifying the notifying instructions is granted to each of the notifying instructions. According to this, the present invention enables analysis of the executed range in the program that includes the conditional instructions as well.
摘要翻译：本发明包括：转换步骤，用于将源程序转换为机器语言程序; 插入步骤，用于插入用于通知在程序语言程序中执行源程序的通知指令; 以及程序生成步骤，用于从其中插入通知指令的机器语言程序生成可执行程序。此外，在插入步骤中，通知指令被放置在构成机器语言程序的每个基本块的入口点，并且与条件指令组的条件相同的通知指令被放置在入口点的机器语言程序中提供的条件指令组。在程序生成步骤中，向通知指示的每一个授予用于识别通知指令的识别信息。据此，本发明还能够对包括条件指令的程序中的执行范围进行分析。

54. 发明申请

US20090037696A1 PROCESSOR 审中-公开
标题翻译：处理器
公开(公告)号：US20090037696A1
公开(公告)日：2009-02-05
申请号：US11908002
申请日：2006-03-07
申请人： Tetsuya Tanaka , Nobuo Higaki , Taketo Heishi
发明人： Tetsuya Tanaka , Nobuo Higaki , Taketo Heishi
IPC分类号： G06F9/312
CPC分类号： G06F9/381 , G06F9/30047 , G06F9/30054 , G06F9/3804 , G06F9/3808
摘要： A processor (100) includes an ordinary instruction buffer (122) for storing and supplying one or more instructions fetched from an instruction cache (10), a TAR instruction buffer (123) for storing the one or more instructions fetched from the instruction cache (10) and supplying them secondarily, a selector (121) for selecting either the ordinary instruction buffer (122) or the TAR instruction buffer (123) as an instruction supplying source, and an instruction fetch control unit (102) for fetching, when a TAR filling instruction is executed, one or more instructions specified by the TAR filling instruction, and for controlling the selector (121) to select the TAR instruction buffer (123), in the case where case one or more fetched instructions are repeatedly supplied, thereby to supply an instruction through the selector (121) from the TAR instruction buffer (123).
摘要翻译：处理器（100）包括用于存储和提供从指令高速缓存（10）取出的一个或多个指令的普通指令缓冲器（122），用于存储从指令高速缓冲存储器（10）提取的一个或多个指令的TAR指令缓冲器（123） 10），并且二次供给，用于选择普通指令缓冲器（122）或TAR指令缓冲器（123）作为指令提供源的选择器（121），以及用于取指令的指令获取控制单元（102），当在情况下重复提供一个或多个获取的指令的情况下，执行TAR填充指令，由TAR填充指令指定的一个或多个指令，以及用于控制选择器（121）选择TAR指令缓冲器（123）以从TAR指令缓冲器（123）通过选择器（121）提供指令。

55. 发明授权

US06209080B1 Constant reconstruction processor that supports reductions in code size and processing time 失效
标题翻译：恒定重建处理器，支持缩小代码大小和处理时间
公开(公告)号：US06209080B1
公开(公告)日：2001-03-27
申请号：US09124335
申请日：1998-07-29
申请人： Taketo Heishi , Nobuo Higaki , Akira Tanaka , Tetsuya Tanaka , Shuichi Takayama , Kensuke Odani , Shinya Miyaji
发明人： Taketo Heishi , Nobuo Higaki , Akira Tanaka , Tetsuya Tanaka , Shuichi Takayama , Kensuke Odani , Shinya Miyaji
IPC分类号： G06F930
CPC分类号： G06F9/30167 , G06F9/30163 , G06F9/383 , G06F9/3853
摘要： A processor for executing operations based on instructions includes an operation constant register 361, a branching constant register 362, a decoding unit 20 for decoding an instruction stored in an instruction register 10, a constant register control unit 32, and an execution unit 30. When the decoding unit 20 finds that the instruction includes a constant to be stored in the branching constant register 362, the constant register control unit 32 shifts a present value in the branching constant register 362 and inserts the constant to be stored, thereby storing a new constant in the branching constant register 362. When the decoding unit 20 finds that a constant is to be stored in the operation constant register 361, the constant register control unit 32 shifts the present value in the operation constant register 361 and inserts the constant to be stored, thereby storing a new constant in the operation constant register 361. When the decoding unit 20 finds that the instruction includes a branch operation, the execution unit 30 executes the branch operation using the constant stored in the branching constant register 362. When the decoding unit 20 finds that the instruction includes an arithmetic operation, the execution unit 30 executes the arithmetic operation using the constant stored in the operation constant register 361.
摘要翻译：用于基于指令执行操作的处理器包括操作常数寄存器361，分支常数寄存器362，用于解码存储在指令寄存器10中的指令的解码单元20，常数寄存器控制单元32和执行单元30.当解码单元20发现指令包括要存储在分支常数寄存器362中的常数，常数寄存器控制单元32移位分支常数寄存器362中的当前值并插入要存储的常数，从而存储新常数在分支常数寄存器362中。当解码单元20发现将常数存储在操作常数寄存器361中时，常数寄存器控制单元32移动操作常数寄存器361中的当前值，并插入要存储的常数，从而在操作常数寄存器361中存储新常数。当解码单元20发现指令包括时分支操作，执行单元30使用存储在分支常数寄存器362中的常数来执行分支操作。当解码单元20发现指令包括算术运算时，执行单元30使用存储在操作常数寄存器361。

56. 再颁专利

USRE41751E1 Instruction converting apparatus using parallel execution code 有权
标题翻译：指令转换装置采用并行执行码
公开(公告)号：USRE41751E1
公开(公告)日：2010-09-21
申请号：US10720030
申请日：2003-11-24
申请人： Taketo Heishi , Tetsuya Tanaka , Nobuo Higaki , Shuichi Takayama , Kensuke Odani
发明人： Taketo Heishi , Tetsuya Tanaka , Nobuo Higaki , Shuichi Takayama , Kensuke Odani
IPC分类号： G06F9/30
CPC分类号： G06F9/30149 , G06F9/30167 , G06F9/3802 , G06F9/3814 , G06F9/3822 , G06F9/3838 , G06F9/3853 , G06F9/3885
摘要： A processor can decode short instructions with a word length equal to one unit field and long instructions with a word length equal to two unit fields. An opcode of each kind of instruction is arranged into the first unit field assigned to the instruction. The number of instructions to be executed by the processor in parallel is s. When the ratio of short to long instructions is s-1:1, the s-1 short instructions are assigned to the first unit field to the s-1tA unit field in the parallel execution code, and the long instruction is assigned to the sth unit field to the (s+k−1)th unit field in the same parallel execution code.
摘要翻译：处理器可以解码具有等于一个单位字段的字长度和长度等于两个单位字段的长指令的短指令。每种指令的操作码被布置到分配给指令的第一单位字段中。由处理器并行执行的指令数是s。当短指令与长指令的比率为s-1：1时，将s-1短指令分配给并行执行代码中的s-1tA单位字段的第一个单位字段，并将长指令分配给sth 单位字段到同一个并行执行代码中的（s + k-1）个单位字段。

57. 发明授权

US06606703B2 Processor using less hardware and instruction conversion apparatus reducing the number of types of instructions 有权
标题翻译：处理器使用较少的硬件和指令转换设备减少指令类型的数量
公开(公告)号：US06606703B2
公开(公告)日：2003-08-12
申请号：US09756068
申请日：2001-01-08
申请人： Shuichi Takayama , Kensuke Odani , Akira Tanaka , Nobuo Higaki , Masato Suzuki , Tetsuya Tanaka , Taketo Heishi , Shinya Miyaji
发明人： Shuichi Takayama , Kensuke Odani , Akira Tanaka , Nobuo Higaki , Masato Suzuki , Tetsuya Tanaka , Taketo Heishi , Shinya Miyaji
IPC分类号： G06F1500
CPC分类号： G06F9/30058 , G06F8/447 , G06F9/30021 , G06F9/30072 , G06F9/30094 , G06F9/30145 , G06F9/30167 , G06F9/30181 , G06F9/3842
摘要： Processor and instruction conversion apparatus, including a technique for reducing the number of types of instructions and processor hardware scale when conditional instructions are used. The processor includes a stare hold unit, an obtaining unit, a decoding unit, a judging unit, and an execution unit. The judging unit judges whether a state hold unit renewal state is included in either of the state and the plurality of states specified by the first state condition in the first conditional instruction when decoded by the decoding unit. When the judgment is affirmative, the execution unit executes an operation specified by the operation code in the first conditional instruction decoded by the decoding unit. The instruction set is assigned first conditional instructions with a first state condition which is mutually exclusive with a second state condition for an unassigned second conditional instruction, both having the same operation code.
摘要翻译：处理器和指令转换装置，包括当使用条件指令时减少指令类型数量和处理器硬件比例的技术。处理器包括凝视保持单元，获取单元，解码单元，判断单元和执行单元。当由解码单元解码时，判断单元判断状态保持单元更新状态是否包括在第一条件指令中由第一状态条件指定的状态和多个状态中的任一状态。当判断为肯定时，执行单元执行由解码单元解码的第一条件指令中由操作码指定的操作。指令集被分配具有第一状态条件的第一条件指令，该第一状态条件与用于未分配的第二条件指令的第二状态条件相互排斥，所述第二状态条件具有相同的操作代码。

58. 发明授权

US06195740B1 Constant reconstructing processor that execute an instruction using an operand divided between instructions 失效
标题翻译：使用在指令之间划分的操作数来执行指令的恒定重构处理器
公开(公告)号：US06195740B1
公开(公告)日：2001-02-27
申请号：US09124659
申请日：1998-07-29
申请人： Taketo Heishi , Nobuo Higaki , Akira Tanaka , Tetsuya Tanaka , Shuichi Takayama , Kensuke Odani , Shinya Miyaji
发明人： Taketo Heishi , Nobuo Higaki , Akira Tanaka , Tetsuya Tanaka , Shuichi Takayama , Kensuke Odani , Shinya Miyaji
IPC分类号： G06F930
CPC分类号： G06F9/30167 , G06F9/30156 , G06F9/30163 , G06F9/3822 , G06F9/3853
摘要： A processor for decoding and executing an instruction includes: an instruction register 10 for storing an instruction; a format decoder 21 for decoding a format code located in the P0.0 field 11 of the instruction stored in the instruction register 10; a constant storage unit including a storage region; a constant register control unit 32 which, when the format decoder 21 has referred to the format code and decoded that an operation field includes a constant to be stored in the constant register 36, transfers the constant from the instruction register 10 to the constant storage unit 36; and a constant register output unit 41 which, when the format decoder 21 has referred to the format code and decoded that an operation field includes an operation code showing an operation that should be executed and a piece of an operand that should be used for the operation, links the constant stored in the constant register 36 with the piece of the operand.
摘要翻译：用于解码和执行指令的处理器包括：用于存储指令的指令寄存器10; 格式解码器21，用于对存储在指令寄存器10中的指令的P0.0字段11中的格式代码进行解码; 包括存储区域的恒定存储单元; 常数寄存器控制单元32，当格式解码器21参考格式代码并解码时，操作字段包括要存储在常数寄存器36中的常数时，将常数从指令寄存器10传送到恒定存储单元 36; 以及常数寄存器输出单元41，当格式解码器21参考格式代码并解码时，操作字段包括表示应该执行的操作的操作码和应该用于操作的操作数，将存储在常数寄存器36中的常数与操作数的段连接起来。

59. 发明申请

US20070186203A1 Reconfigurable logic block, programmable logic device provided with the reconfigurable logic block, and method of fabricating the reconfigurable logic block 失效
标题翻译：可配置逻辑块，可配置逻辑块的可编程逻辑器件，以及制造可重构逻辑块的方法
公开(公告)号：US20070186203A1
公开(公告)日：2007-08-09
申请号：US11598679
申请日：2006-11-14
申请人： Toshinori Sueyoshi , Masahiro Iida , Motoki Amagasaki , Kazuhiko Taketa , Taketo Heishi , Nobuharu Suzuki
发明人： Toshinori Sueyoshi , Masahiro Iida , Motoki Amagasaki , Kazuhiko Taketa , Taketo Heishi , Nobuharu Suzuki
IPC分类号： G06F17/50 , H03K17/693
CPC分类号： H03K19/17748 , H03K19/17728
摘要： A reconfigurable logic block has a first circuit that configures an arithmetic circuit and a second circuit that configures a circuit outside of the arithmetic circuit. A plurality of different circuits are configured by changing the settings of predetermined signals in the first and second circuits.
摘要翻译：可重配置逻辑块具有配置运算电路的第一电路和将运算电路外部的电路配置的第二电路。通过改变第一和第二电路中的预定信号的设置来配置多个不同的电路。

60. 发明申请

US20070113220A1 Program translation method and notifying instruction inserting method 有权
标题翻译：程序翻译方法和通知指令插入方法
公开(公告)号：US20070113220A1
公开(公告)日：2007-05-17
申请号：US11595900
申请日：2006-11-13
申请人： Yoko Makiyori , Taketo Heishi , Akira Takuma
发明人： Yoko Makiyori , Taketo Heishi , Akira Takuma
IPC分类号： G06F9/45
CPC分类号： G06F8/41
摘要： The present invention comprises: a converting step for converting a source program into a machine language program; an inserting step for inserting notifying instructions for notifying that the source program has been executed in the machine language program; and a program generating step for generating the executable program from the machine language program in which the notifying instructions are inserted. Further, in the inserting step, the notifying instructions are placed at the entry points of each basic block that constitutes the machine language program and the notifying instructions to which the same conditions as those of the conditional instruction groups are granted are placed at the entry points of conditional instruction groups provided in the machine language program. In the program generating step, identification information for identifying the notifying instructions is granted to each of the notifying instructions. According to this, the present invention enables analysis of the executed range in the program that includes the conditional instructions as well.
摘要翻译：本发明包括：转换步骤，用于将源程序转换为机器语言程序; 插入步骤，用于插入用于通知在程序语言程序中执行源程序的通知指令; 以及程序生成步骤，用于从其中插入通知指令的机器语言程序生成可执行程序。此外，在插入步骤中，通知指令被放置在构成机器语言程序的每个基本块的入口点，并且与条件指令组的条件相同的通知指令被放置在入口点的机器语言程序中提供的条件指令组。在程序生成步骤中，向通知指示的每一个授予用于识别通知指令的识别信息。据此，本发明还能够对包括条件指令的程序中的执行范围进行分析。

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