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1. 发明授权

US07877743B2 Program translation method and notifying instruction inserting method 有权
标题翻译：程序翻译方法和通知指令插入方法
公开(公告)号：US07877743B2
公开(公告)日：2011-01-25
申请号：US11595900
申请日：2006-11-13
申请人： Yoko Makiyori , Taketo Heishi , Akira Takuma
发明人： Yoko Makiyori , Taketo Heishi , Akira Takuma
IPC分类号： G06F9/44 , G06F9/45 , G06F11/00 , G06F15/00
CPC分类号： G06F8/41
摘要： The present invention comprises: a converting step for converting a source program into a machine language program; an inserting step for inserting notifying instructions for notifying that the source program has been executed in the machine language program; and a program generating step for generating the executable program from the machine language program in which the notifying instructions are inserted. Further, in the inserting step, the notifying instructions are placed at the entry points of each basic block that constitutes the machine language program and the notifying instructions to which the same conditions as those of the conditional instruction groups are granted are placed at the entry points of conditional instruction groups provided in the machine language program. In the program generating step, identification information for identifying the notifying instructions is granted to each of the notifying instructions. According to this, the present invention enables analysis of the executed range in the program that includes the conditional instructions as well.
摘要翻译：本发明包括：转换步骤，用于将源程序转换为机器语言程序; 插入步骤，用于插入用于通知在程序语言程序中执行源程序的通知指令; 以及程序生成步骤，用于从其中插入通知指令的机器语言程序生成可执行程序。此外，在插入步骤中，通知指令被放置在构成机器语言程序的每个基本块的入口点，并且与条件指令组的条件相同的通知指令被放置在入口点的机器语言程序中提供的条件指令组。在程序生成步骤中，向通知指示的每一个授予用于识别通知指令的识别信息。据此，本发明还能够对包括条件指令的程序中的执行范围进行分析。

2. 发明授权

US08402445B2 Program translation method and notifying instruction inserting method 有权
标题翻译：程序翻译方法和通知指令插入方法
公开(公告)号：US08402445B2
公开(公告)日：2013-03-19
申请号：US12962075
申请日：2010-12-07
申请人： Yoko Makiyori , Taketo Heishi , Akira Takuma
发明人： Yoko Makiyori , Taketo Heishi , Akira Takuma
IPC分类号： G06F9/44 , G06F9/45
CPC分类号： G06F8/41
摘要： The present invention comprises: a converting step for converting a source program into a machine language program; an inserting step for inserting notifying instructions for notifying that the source program has been executed in the machine language program; and a program generating step for generating the executable program from the machine language program in which the notifying instructions are inserted. Further, in the inserting step, the notifying instructions are placed at the entry points of each basic block that constitutes the machine language program and the notifying instructions to which the same conditions as those of the conditional instruction groups are granted are placed at the entry points of conditional instruction groups provided in the machine language program. In the program generating step, identification information for identifying the notifying instructions is granted to each of the notifying instructions. According to this, the present invention enables analysis of the executed range in the program that includes the conditional instructions as well.
摘要翻译：本发明包括：转换步骤，用于将源程序转换为机器语言程序; 插入步骤，用于插入用于通知在程序语言程序中执行源程序的通知指令; 以及程序生成步骤，用于从其中插入通知指令的机器语言程序生成可执行程序。此外，在插入步骤中，通知指令被放置在构成机器语言程序的每个基本块的入口点，并且与条件指令组的条件相同的通知指令被放置在入口点的机器语言程序中提供的条件指令组。在程序生成步骤中，向通知指示的每一个授予用于识别通知指令的识别信息。据此，本发明还能够对包括条件指令的程序中的执行范围进行分析。

3. 发明申请

US20070113220A1 Program translation method and notifying instruction inserting method 有权
标题翻译：程序翻译方法和通知指令插入方法
公开(公告)号：US20070113220A1
公开(公告)日：2007-05-17
申请号：US11595900
申请日：2006-11-13
申请人： Yoko Makiyori , Taketo Heishi , Akira Takuma
发明人： Yoko Makiyori , Taketo Heishi , Akira Takuma
IPC分类号： G06F9/45
CPC分类号： G06F8/41
摘要： The present invention comprises: a converting step for converting a source program into a machine language program; an inserting step for inserting notifying instructions for notifying that the source program has been executed in the machine language program; and a program generating step for generating the executable program from the machine language program in which the notifying instructions are inserted. Further, in the inserting step, the notifying instructions are placed at the entry points of each basic block that constitutes the machine language program and the notifying instructions to which the same conditions as those of the conditional instruction groups are granted are placed at the entry points of conditional instruction groups provided in the machine language program. In the program generating step, identification information for identifying the notifying instructions is granted to each of the notifying instructions. According to this, the present invention enables analysis of the executed range in the program that includes the conditional instructions as well.
摘要翻译：本发明包括：转换步骤，用于将源程序转换为机器语言程序; 插入步骤，用于插入用于通知在程序语言程序中执行源程序的通知指令; 以及程序生成步骤，用于从其中插入通知指令的机器语言程序生成可执行程序。此外，在插入步骤中，通知指令被放置在构成机器语言程序的每个基本块的入口点，并且与条件指令组的条件相同的通知指令被放置在入口点的机器语言程序中提供的条件指令组。在程序生成步骤中，向通知指示的每一个授予用于识别通知指令的识别信息。据此，本发明还能够对包括条件指令的程序中的执行范围进行分析。

4. 发明授权

US5663729A Control apparatus and control method of AD converter 失效
标题翻译： AD转换器的控制装置和控制方法
公开(公告)号：US5663729A
公开(公告)日：1997-09-02
申请号：US471532
申请日：1995-06-06
申请人： Yoshimi Wada , Akira Takuma
发明人： Yoshimi Wada , Akira Takuma
IPC分类号： G06F3/05 , H03M1/12
CPC分类号： H03M1/12 , G06F3/05
摘要： The AD conversion control section of the processor sets the clock generating circuit of the output port alternately to an L-level output condition and an H-level output condition to generate a clock signal. A chip select signal is caused to be output from the chip select circuit of the output port in synchronization with output of the first clock signal by the interruption signal. Furthermore, the bit data output in series bit by bit from the AD converter in synchronization with occurrence of a clock signal is incorporated bit by bit in synchronization with the interruption signal from the input ports to be stored in the register.
摘要翻译：处理器的AD转换控制部分将输出端口的时钟产生电路交替设置为L电平输出条件和H电平输出条件以产生时钟信号。通过中断信号，与第一时钟信号的输出同步地使芯片选择信号从输出端口的芯片选择电路输出。此外，与来自AD转换器的时钟信号的发生同步地逐位输出的位数据与来自输入端口的中断信号同步地并入，以被存储在寄存器中。

5. 发明申请

US20070006158A1 Instruction execution device, debugging method, debugging device, and debugging program 有权
标题翻译：指令执行装置，调试方法，调试装置和调试程序
公开(公告)号：US20070006158A1
公开(公告)日：2007-01-04
申请号：US11440253
申请日：2006-05-25
申请人： Akira Takuma , Kohsaku Shibata
发明人： Akira Takuma , Kohsaku Shibata
IPC分类号： G06F9/44
CPC分类号： G06F11/3648
摘要： In executing debugging of an executable program in which a breakpoint is set at a conditional instruction using a software break technique, judgment of whether or not to stop the debugging is made, without use of a debugging device, in accordance with whether an execution condition expression of the conditional instruction is true or false. A processor capable of decoding and executing a program that includes conditional instructions executes debugging of the program. When a decoded instruction is a conditional break instruction (S201: YES, S202: YES), the processor identifies the type of the execution condition of the conditional break instruction (step S203), and refers to a status register to check a status flag of the execution condition (S204). If the execution condition is satisfied (S205: YES), the processor executes interrupt processing to suspend debugging (S206), and if the execution condition is not satisfied (S205: NO), the processor continues debugging.
摘要翻译：在执行使用软件断开技术在条件指令中设置断点的可执行程序的调试中，根据执行条件表达式是否进行调试的判断，而不使用调试装置的条件指令是true或false。能够解码和执行包括条件指令的程序的处理器执行程序的调试。当解码指令是条件中断指令（S 201：是，S 202：是）时，处理器识别条件中断指令的执行条件的类型（步骤203），并且参考状态寄存器来检查执行条件的状态标志（S 204）。如果满足执行条件（S 205：是），则处理器执行中断处理以暂停调试（S 206），如果不满足执行条件（S 205：否），则处理器继续调试。

6. 发明授权

US6141791A Debug aid device, program compiler device, storage medium storing computer-readable debugger program, and storage medium storing program compiler program 失效
标题翻译：调试辅助装置，程序编译装置，存储计算机可读调试程序的存储介质和存储程序编译程序的存储介质
公开(公告)号：US6141791A
公开(公告)日：2000-10-31
申请号：US143628
申请日：1998-08-28
申请人： Akira Takuma , Shuichi Takayama
发明人： Akira Takuma , Shuichi Takayama
IPC分类号： G06F11/28 , G06F9/06 , G06F9/44 , G06F9/45 , G06F11/36 , G06F11/00
CPC分类号： G06F11/3664 , G06F11/3624
摘要： On receiving a target address specification from a programmer, an execution code reconversion unit reconverts an operation code of an execution code loaded in the specified address to a mnemonic code. When the execution code includes a subconstant as an operand, a constant restoration unit detects constant division information that shows the subconstant included in the execution code in a debug information storage unit, in order to specify the long-word constant from which the subconstant has been generated. The constant restoration unit then replaces the subconstant with the long-word constant. As a result, the mnemonic code is displayed with the long-word constant.
摘要翻译：在从程序员接收到目标地址指定的情况下，执行代码重新转换单元将加载在指定地址中的执行代码的操作码重新转换为助记符代码。当执行代码包括作为操作数的子定时时，常数恢复单元检测在调试信息存储单元中显示包括在执行代码中的子代码的常数分割信息，以便指定从子代数已经被写入的长字常数生成。常数恢复单元然后用长字常数代替子恒定。结果，记忆码用长字常数显示。

7. 发明授权

US07620802B2 Instruction execution device, debugging method, debugging device, and debugging program 有权
标题翻译：指令执行装置，调试方法，调试装置和调试程序
公开(公告)号：US07620802B2
公开(公告)日：2009-11-17
申请号：US11440253
申请日：2006-05-25
申请人： Akira Takuma , Kohsaku Shibata
发明人： Akira Takuma , Kohsaku Shibata
IPC分类号： G06F11/36
CPC分类号： G06F11/3648
摘要： In executing debugging of an executable program in which a breakpoint is set at a conditional instruction using a software break technique, judgment of whether or not to stop the debugging is made, without use of a debugging device, in accordance with whether an execution condition expression of the conditional instruction is true or false. A processor capable of decoding and executing a program that includes conditional instructions executes debugging of the program. When a decoded instruction is a conditional break instruction (S201: YES, S202: YES), the processor identifies the type of the execution condition of the conditional break instruction (step S203), and refers to a status register to check a status flag of the execution condition (S204). If the execution condition is satisfied (S205: YES), the processor executes interrupt processing to suspend debugging (S206), and if the execution condition is not satisfied (S205: NO), the processor continues debugging.
摘要翻译：在执行使用软件断开技术在条件指令中设置断点的可执行程序的调试中，根据执行条件表达式是否进行调试的判断，而不使用调试装置的条件指令是true或false。能够解码和执行包括条件指令的程序的处理器执行程序的调试。当解码指令是条件中断指令（S201：是，S202：是）时，处理器识别条件中断指令的执行条件的类型（步骤S203），并且参考状态寄存器来检查状态标志执行条件（S204）。如果执行条件满足（S205：是），则处理器执行中断处理以暂停调试（S206），如果执行条件不满足（S205：否），则处理器继续调试。

8. 发明申请

US20090164764A1 PROCESSOR AND DEBUGGING DEVICE 审中-公开
标题翻译：处理器和调试器件
公开(公告)号：US20090164764A1
公开(公告)日：2009-06-25
申请号：US12394538
申请日：2009-02-27
申请人： Akira Takuma , Kohsaku Shibata
发明人： Akira Takuma , Kohsaku Shibata
IPC分类号： G06F9/318
CPC分类号： G06F11/3652
摘要： A processor according to the present invention is capable of executing instructions in parallel, the processor further executing a string of instructions consisting of a plurality of instructions allocated at continuous addresses as an execution unit, comprising an instruction analyzer, an instruction executor and an instruction canceling unit. The instruction analyzer comprising debug instruction detectors for detecting a debug instruction which generates debug interruption, the instruction detectors of the same number as the instructions executable in parallel by the processor is provided. The instruction executor for executing a group of instructions comprising at least one of the instructions that is included in the same string of the instructions as the detected debug instruction and allocated at an address of a lower-order position than the detected debug instruction when the debug instruction is detected by the instruction analyzer, and an instruction canceller for canceling execution of a group of instructions comprising at least one of the instructions that is included in the same string of the instructions as the detected debug instruction and allocated at an address of a higher-order position than the detected debug instruction when the debug instruction is detected by the instruction analyzer.
摘要翻译：根据本发明的处理器能够并行执行指令，处理器还执行由连续地址分配的多条指令作为执行单元的指令串，包括指令分析器，指令执行器和指令取消单元。该指令分析器包括用于检测产生调试中断的调试指令的调试指令检测器，提供与由处理器并行执行的指令相同数量的指令检测器。指令执行器，用于执行一组指令，该指令组包括与所检测的调试指令相同的指令串中包括的指令中的至少一个，并且在调试时被分配在比检测到的调试指令低的位置的地址指令由指令分析器检测，以及指令消除器，用于取消一组指令的执行，所述指令组包括与检测到的调试指令相同的指令串中包括的指令中的至少一个，并分配在较高的地址当指令分析器检测到调试指令时，检测到的调试指令的顺序位置。

9. 发明申请

US20070050682A1 Processor and debugging device 审中-公开
标题翻译：处理器和调试设备
公开(公告)号：US20070050682A1
公开(公告)日：2007-03-01
申请号：US11509797
申请日：2006-08-25
申请人： Akira Takuma , Kohsaku Shibata
发明人： Akira Takuma , Kohsaku Shibata
IPC分类号： G06F11/00
CPC分类号： G06F11/3652
摘要： A processor according to the present invention is capable of executing instructions in parallel, the processor further executing a string of instructions consisting of a plurality of instructions allocated at continuous addresses as an execution unit, comprising an instruction analyzer, an instruction executor and an instruction canceling unit. The instruction analyzer comprising debug instruction detectors for detecting a debug instruction which generates debug interruption, the instruction detectors of the same number as the instructions executable in parallel by the processor is provided. The instruction executor for executing a group of instructions comprising at least one of the instructions that is included in the same string of the instructions as the detected debug instruction and allocated at an address of a lower-order position than the detected debug instruction when the debug instruction is detected by the instruction analyzer, and an instruction canceller for canceling execution of a group of instructions comprising at least one of the instructions that is included in the same string of the instructions as the detected debug instruction and allocated at an address of a higher-order position than the detected debug instruction when the debug instruction is detected by the instruction analyzer.
摘要翻译：根据本发明的处理器能够并行执行指令，处理器还执行由连续地址分配的多条指令作为执行单元的指令串，包括指令分析器，指令执行器和指令取消单元。该指令分析器包括用于检测产生调试中断的调试指令的调试指令检测器，提供与由处理器并行执行的指令相同数量的指令检测器。指令执行器，用于执行一组指令，该指令组包括与所检测的调试指令相同的指令串中包括的指令中的至少一个，并且在调试时被分配在比检测到的调试指令低的位置的地址指令由指令分析器检测，以及指令消除器，用于取消一组指令的执行，所述指令组包括与检测到的调试指令相同的指令串中包括的指令中的至少一个，并分配在较高的地址当指令分析器检测到调试指令时，检测到的调试指令的顺序位置。

10. 发明授权

US5590340A Apparatus and method for suspending and resuming software application on a computer 失效
标题翻译：在计算机上暂停和恢复软件应用程序的装置和方法
公开(公告)号：US5590340A
公开(公告)日：1996-12-31
申请号：US221993
申请日：1994-04-01
申请人： Mitsuaki Morita , Masaya Miyazaki , Nobuyuki Enoki , Akira Takuma
发明人： Mitsuaki Morita , Masaya Miyazaki , Nobuyuki Enoki , Akira Takuma
IPC分类号： G06F1/00 , G06F1/30 , G06F3/048 , G06F3/14 , G06F9/445 , G06F11/14 , G06F1/32
CPC分类号： G06F9/4418 , G06F1/30 , Y02B60/186
摘要： The control unit of a computer system comprises a first storing device for holding written data while the power is on, a second storing device for holding the written data, even when the power is off and a power-off preserving device for terminating power to the system after transferring the data held in the first storing device to the second storing device. The control system can be utilized to only store the effective contents of the operating data to thereby enable data reconstruction upon resumption of power. The control device can interface with a window system processing device which can enable the refreshing of graphic display information upon resumption of power. The second storing device may have limited memory capacity and the operator can be informed of its capacity prior to a final shut-off of power. The control unit can further identify those programs that are not capable of being restored to their original condition and accordingly canceling any program execution when such a condition is judged.
摘要翻译：计算机系统的控制单元包括用于在电源接通时保持写入数据的第一存储装置，即使电源关闭时用于保存写入数据的第二存储装置和用于将电力终止于电源的断电保持装置系统将保存在第一存储装置中的数据传送到第二存储装置。控制系统可以用于仅存储操作数据的有效内容，从而使得在恢复电力时能够进行数据重建。控制装置可以与窗口系统处理装置连接，该窗口系统处理装置能够在恢复电力时使图形显示信息更新。第二存储装置可能具有有限的存储器容量，并且可以在最终关闭电源之前通知操作者其容量。控制单元可以进一步识别那些不能恢复到其原始状态的程序，从而在判断出这种状况时取消任何程序的执行。

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