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51. 发明授权

US5965923A Lateral bipolar transistor and apparatus using same 失效
标题翻译：侧面双极晶体管及其使用的装置
公开(公告)号：US5965923A
公开(公告)日：1999-10-12
申请号：US26235
申请日：1998-02-19
申请人： Kirk D. Prall , Mike P. Violette
发明人： Kirk D. Prall , Mike P. Violette
IPC分类号： H01L21/331 , H01L21/8222 , H01L21/8249 , H01L27/06 , H01L27/082 , H01L29/735 , H01L27/102 , H01L29/70 , H01L31/11
CPC分类号： H01L29/6625 , H01L21/8222 , H01L21/8249 , H01L27/0623 , H01L27/082 , H01L29/735
摘要： A substantially concentric lateral bipolar transistor and the method of forming same. A base region is disposed about a periphery of an emitter region, and a collector region is disposed about a periphery of the base region to form the concentric lateral bipolar transistor of the invention. A gate overlies the substrate and at least a portion of the base region. At least one electrical contact is formed connecting the base and the gate, although a plurality of contacts may be formed. A further bipolar transistor is formed according to the following method of the invention. A base region is formed in a substrate and a gate region is formed overlying at least a portion of the base region. Emitter and collector terminals are formed on opposed sides of the base region. The gate is used as a mask during first and second ion implants. During the first ion implant the ions bombard the substrate from a first direction to grade a base/emitter junction, and during the second ion implant ions bombard the substrate from a second direction to grade a base/collector junction. Aso a lateral bipolar transistor having a decreased base width as a result of implanting ions after fabrication of collector and emitter regions to enlarge the collector and emitter regions, thereby decreasing the base region and increasing gain.
摘要翻译：基本同心的横向双极晶体管及其形成方法。基极区域围绕发射极区域的周边设置，并且集电极区域围绕基极区域的周边设置以形成本发明的同心横向双极晶体管。栅极覆盖衬底和基极区域的至少一部分。形成连接基座和栅极的至少一个电触头，尽管可以形成多个触点。根据本发明的以下方法形成另外的双极晶体管。在基板中形成基极区域，并且形成覆盖基极区域的至少一部分的栅极区域。发射极和集电极端子形成在基极区域的相对侧上。在第一和第二离子注入期间，门用作掩模。在第一离子注入期间，离子从第一方向轰击衬底以分级基极/发射极结，并且在第二离子注入期间，离子从第二方向轰击衬底以对基极/集电极结进行分级。 Aso是在制造集电极和发射极区域之后注入离子的结果，具有减小的基极宽度的横向双极晶体管，以扩大集电极和发射极区域，从而减小基极区域并增加增益。

52. 再颁专利

USRE35810E Plug-based floating gate memory 失效
标题翻译：基于插头的浮动存储器
公开(公告)号：USRE35810E
公开(公告)日：1998-05-26
申请号：US591702
申请日：1996-01-25
申请人： Kirk D. Prall
发明人： Kirk D. Prall
IPC分类号： H01L29/788 , H01L21/8247
CPC分类号： H01L29/7885
摘要： A device and a method of forming a floating gate memory transistor of very small area, thereby allowing a high-density integrated circuit chip, more specifically for Erasable Programmable Read-Only Memory (EPROM) or similar non-volatile devices. In a first embodiment, a method is disclosed that fabricates a programmable memory cell described as a "diffusion cut" cell where a plug-type floating gate contact hole cuts through a diffusion region and partially into a substrate region. In a second embodiment, a method is disclosed that fabricates a programmable memory cell described as an "oxide cut" cell, where the plug-type floating gate contact hole only penetrates a silicon oxide layer. This "oxide cut" cell is formed in a similar fashion except penetration does not go into the diffusion region or substrate.
摘要翻译：一种形成非常小面积的浮动栅极存储晶体管的器件和方法，从而允许高密度集成电路芯片，更具体地说可用于可擦除可编程只读存储器（EPROM）或类似的非易失性器件。在第一实施例中，公开了一种制造被描述为“扩散切割”单元的可编程存储器单元的方法，其中插头式浮栅接触孔穿过扩散区并且部分地切入衬底区域。在第二实施例中，公开了一种制造被描述为“氧化物切割”电池的可编程存储器单元的方法，其中插塞式浮栅接触孔仅穿透氧化硅层。这种“氧化物切割”电池以类似的方式形成，除了渗透不进入扩散区域或衬底。

53. 发明授权

US5345104A Flash memory cell having antimony drain for reduced drain voltage during programming 失效
标题翻译：具有锑漏极的闪存单元，用于在编程期间降低漏极电压
公开(公告)号：US5345104A
公开(公告)日：1994-09-06
申请号：US089382
申请日：1993-07-08
申请人： Kirk D. Prall , Wayne I. Kinney
发明人： Kirk D. Prall , Wayne I. Kinney
IPC分类号： H01L29/167 , H01L29/788 , H01L29/68
CPC分类号： H01L29/7885 , H01L29/167
摘要： An improved ETOX-type flash memory cell which requires only a single 5-volt power supply for read, write and erase functions. By substituting antimony or the combination of antimony and arsenic for the usual arsenic drain dopant, drain junction depth is reduced, due to the low diffusivity of antimony during high-temperature cycling. In order to maximize the concentration of antimony in the drain region, which is limited to approximately 3.times.10.sup.19 atoms/cm.sup.3 (due to solid solubility characteristics of antimony at standard silicon process activation temperatures in the 800.degree.-1,000.degree. C. range), an antimony implant concentration of approximately 1.times.10.sup.15 atoms/cm.sup.2 is employed. The resulting shallow junction raises the electric field strength at the cell's drain junction, thus increasing the hot electron generation rate and improving the programming efficiency. The decreased junction depth also acts to improve short channel effects such as punch-through and drain-to-gate capacitive coupling. The addition of a boron halo implant to obtain a traditional doubly diffused drain further enhances programming efficiency.
摘要翻译：一个改进的ETOX型闪存单元，只需要一个5伏电源进行读，写和擦除功能。通过将锑或锑和砷的组合替代为通常的砷排出掺杂剂，由于在高温循环期间锑的低扩散率，漏极结深度减小。为了使漏极区域中的锑浓度最大化，限制在约3×1019原子/ cm3（由于标准硅工艺活性温度在800°-1000℃范围内的锑的固体溶解度特性），锑使用约1×10 15原子/ cm 2的注入浓度。所产生的浅结点提高了电池漏极结处的电场强度，从而提高了热电子发生速率，提高了编程效率。减小的结深也可以改善短沟道效应，例如穿通和漏极 - 栅极电容耦合。添加硼卤素植入物以获得传统的双扩散漏极进一步提高了编程效率。

54. 发明授权

US08415223B2 Memory devices and methods of forming memory devices 有权
公开(公告)号：US08415223B2
公开(公告)日：2013-04-09
申请号：US13365472
申请日：2012-02-03
申请人： Kirk D. Prall , Behnam Moradi , Seiichi Aritome , Di Li , Chris Larsen
发明人： Kirk D. Prall , Behnam Moradi , Seiichi Aritome , Di Li , Chris Larsen
IPC分类号： H01L21/336
CPC分类号： H01L29/66825 , H01L21/22 , H01L21/265 , H01L21/26506 , H01L21/324 , H01L27/1052 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/6659 , H01L29/66659 , H01L29/788
摘要： Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.

55. 发明申请

US20120241711A1 MULTI-LEVEL MEMORY CELL 有权
标题翻译：多级记忆体
公开(公告)号：US20120241711A1
公开(公告)日：2012-09-27
申请号：US13072504
申请日：2011-03-25
申请人： Durai Vishak Nirmal Ramaswamy , Kirk D. Prall
发明人： Durai Vishak Nirmal Ramaswamy , Kirk D. Prall
IPC分类号： H01L45/00 , H01L21/8239
CPC分类号： H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147
摘要： Some embodiments include a memory device and methods of forming the same. The memory device can include an electrode coupled to a memory element. The electrode can include different materials located at different portions of the electrode. The materials can create different dielectrics contacting the memory elements at different locations. Various states of the materials in the memory device can be used to represent stored information. Other embodiments are described.
摘要翻译：一些实施例包括存储器件及其形成方法。存储器件可以包括耦合到存储元件的电极。电极可以包括位于电极的不同部分的不同材料。这些材料可以在不同位置产生接触存储元件的不同电介质。可以使用存储器件中的材料的各种状态来表示存储的信息。描述其他实施例。

56. 发明授权

US08102714B2 Programming methods for multi-level memory devices 有权
标题翻译：多级存储器件的编程方法
公开(公告)号：US08102714B2
公开(公告)日：2012-01-24
申请号：US12699658
申请日：2010-02-03
申请人： Chun Chen , Kirk D. Prall
发明人： Chun Chen , Kirk D. Prall
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483
摘要： A method is provided for programming a memory cell. The memory cell is fabricated on a substrate and comprises a source region, a drain region, a floating gate, and a control gate. The memory cell has a threshold voltage selectively configurable into one of at least three programming states. The method includes generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region. The method further includes injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate. A selected threshold voltage for the memory cell corresponding to a selected one of the programming states is generated by applying a different selected gate voltage.
摘要翻译：提供了一种用于对存储器单元进行编程的方法。存储单元制造在衬底上，并且包括源极区域，漏极区域，浮动栅极和控制栅极。存储单元具有可选地配置为至少三个编程状态之一的阈值电压。该方法包括通过在漏极区域和源极区域之间施加漏极 - 源极偏置电压来在漏极区域和源极区域之间产生漏极电流。该方法还包括通过向控制栅极施加栅极电压将热电子从漏极电流注入到浮置栅极。通过施加不同的选择的栅极电压来产生对应于选择的一个编程状态的存储单元的选定的阈值电压。

57. 发明申请

US20090046508A1 Programming methods for multi-level flash EEPROMs 失效
标题翻译：多级闪存EEPROM的编程方法
公开(公告)号：US20090046508A1
公开(公告)日：2009-02-19
申请号：US11496969
申请日：2006-08-01
申请人： Chun Chen , Kirk D. Prall
发明人： Chun Chen , Kirk D. Prall
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C11/5628 , G11C16/0483
摘要： A method is provided for programming a memory cell of an electrically erasable programmable read only memory. The memory cell is fabricated on a substrate and comprises a source region, a drain region, a floating gate, and a control gate. The memory cell has a threshold voltage selectively configurable into one of at least three programming states. The method includes generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region. The method further includes injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate. A selected threshold voltage for the memory cell corresponding to a selected one of the programming states is generated by applying a selected constant drain-to-source bias voltage and a selected gate voltage.
摘要翻译：提供了一种用于对电可擦除可编程只读存储器的存储单元进行编程的方法。存储单元制造在衬底上，并且包括源极区域，漏极区域，浮动栅极和控制栅极。存储单元具有可选地配置为至少三个编程状态之一的阈值电压。该方法包括通过在漏极区域和源极区域之间施加漏极 - 源极偏置电压来在漏极区域和源极区域之间产生漏极电流。该方法还包括通过向控制栅极施加栅极电压将热电子从漏极电流注入到浮置栅极。通过施加所选择的恒定的漏极 - 源极偏置电压和所选择的栅极电压来产生对应于所选择的编程状态的存储单元的选定阈值电压。

58. 发明授权

US07417280B2 Method and apparatus for a flash memory device comprising a source local interconnect 有权
标题翻译：一种用于包括源局部互连的闪存器件的方法和装置
公开(公告)号：US07417280B2
公开(公告)日：2008-08-26
申请号：US11440646
申请日：2006-05-24
申请人： Kirk D. Prall , Chun Chen
发明人： Kirk D. Prall , Chun Chen
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L21/76831 , H01L21/76895 , H01L21/76897 , H01L27/115
摘要： A method for forming a flash memory device having a local interconnect connecting source regions of a plurality of transistors within a sector allows for a highly selective wet etch of a dielectric region overlying the source region. An embodiment of the method comprises the use of an etch-resistant layer covering various features such as any gate oxide remaining over the source region, spacers along sidewalls of the transistor stacks, and a capping layer of the transistor. An in-process semiconductor device resulting from the inventive method is also disclosed.
摘要翻译：用于形成具有连接在扇区内的多个晶体管的源极区域的局部互连的快闪存储器件的方法允许覆盖源极区域的电介质区域的高度选择性的湿蚀刻。该方法的一个实施例包括使用覆盖各种特征的耐蚀刻层，例如在源极区域上残留的任何栅极氧化物，沿着晶体管叠层的侧壁的间隔物，以及晶体管的覆盖层。还公开了由本发明方法得到的过程中半导体器件。

59. 发明授权

US07338856B2 Double-doped polysilicon floating gate 有权
标题翻译：双掺杂多晶硅浮栅
公开(公告)号：US07338856B2
公开(公告)日：2008-03-04
申请号：US10649050
申请日：2003-08-27
申请人： Chun Chen , Kirk D. Prall
发明人： Chun Chen , Kirk D. Prall
IPC分类号： H01L21/336 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/42332 , H01L21/28273 , H01L29/42324 , H01L29/7883
摘要： The present invention provides a method and apparatus for forming a double-doped polysilicon floating gate in a semiconductor memory element. The method includes forming a first dielectric layer on a semiconductor substrate and forming a floating gate above the first dielectric layer, the floating gate comprised of a first layer doped with a first type of dopant material and a second layer doped with a second type of dopant material that is opposite the first type of dopant material in the first layer. The method further includes forming a second dielectric layer above the floating gate, forming a control gate above the second dielectric layer, and forming a source and a drain in the substrate.
摘要翻译：本发明提供一种在半导体存储元件中形成双掺杂多晶硅浮动栅极的方法和装置。该方法包括在半导体衬底上形成第一介电层并在第一介电层上形成浮置栅极，浮置栅极包括掺杂有第一类掺杂剂材料的第一层和掺杂有第二类掺杂剂的第二层与第一层中的第一种掺杂剂材料相反的材料。该方法还包括在浮置栅极上形成第二电介质层，在第二电介质层上形成控制栅极，以及在衬底中形成源极和漏极。

60. 发明授权

US07269071B2 NROM memory cell, memory array, related devices and methods 有权
公开(公告)号：US07269071B2
公开(公告)日：2007-09-11
申请号：US11345982
申请日：2006-02-02
申请人： Kirk D. Prall , Leonard Forbes
发明人： Kirk D. Prall , Leonard Forbes
IPC分类号： G11C11/34 , H01L29/792
CPC分类号： H01L27/11568 , G11C11/5692 , G11C16/0475 , H01L27/115
摘要： An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store more than one bit per gate. The array also includes electrical contacts to the memory cells including the substantially vertical structures. The cells can be programmed to have one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2) and such that the programmed cell operates at reduced drain source current.

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