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1. 发明授权

US06369431B1 Method for forming conductors in semiconductor devices 有权
标题翻译：在半导体器件中形成导体的方法
公开(公告)号：US06369431B1
公开(公告)日：2002-04-09
申请号：US09570106
申请日：2000-05-12
申请人： Fernando Gonzalez , Gurtej S. Sandhu , Mike P. Violette
发明人： Fernando Gonzalez , Gurtej S. Sandhu , Mike P. Violette
IPC分类号： H01L29792
CPC分类号： H01L21/76804 , H01L21/28518 , H01L21/76895 , H01L21/76897 , H01L27/10 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： A memory device wherein a diode is serially connected to a programmable resistor and is in electrical communication with a buried digit line. An electrically conductive plug is electrically interposed between the digit line and a strapping layer, thereby creating a double metal scheme wherein the strapping layer is a second metal layer overlying metal wordlines. In a method of a first embodiment the strapping material is electrically connected to the digit line through a planar landing pad overlying the conductive plug. An insulative material is sloped to the planar landing pad in order to provide a surface conducive to the formation of the strapping material. In a method of a second embodiment diodes are formed, each having a maximum width equal to f, which is equal to the minimum photolithographic limit of the photolithographic equipment being used, and distanced one from the other along a length of the digit line by a maximum distance equals to f; at least portions of the diodes are masked; at least a portion of an insulative material interposed between two diodes is removed to expose the buried digit line; and the conductive plug is formed in contact with the exposed portion of the buried digit line. After the formation of a programmable resistor in series with the diode a wordline is formed in electrical communication with each of the programmable resistors, and an insulative layer is formed overlying each wordline. Next an insulative spacer layer is deposited and etched to expose the conductive plug. The strapping layer is then formed overlying and in contact with the conductive plug.
摘要翻译：一种存储器件，其中二极管串联连接到可编程电阻并与埋地数字线电连通。导电插头电插入数字线和捆扎层之间，从而产生双金属方案，其中捆扎层是覆盖金属字线的第二金属层。在第一实施例的方法中，捆扎材料通过覆盖在导电插塞上的平面着陆垫电连接到数字线。绝缘材料倾斜到平面着陆垫，以提供有利于形成捆扎材料的表面。在第二实施例的方法中，形成二极管，每个二极管具有等于f的最大宽度，其等于所使用的光刻设备的最小光刻极限，并且沿着数字线的长度彼此间隔一个最大距离等于f; 二极管的至少部分被掩蔽; 插入在两个二极管之间的绝缘材料的至少一部分被去除以露出掩埋的数字线; 并且导电插塞形成为与掩埋的数字线的暴露部分接触。在与二极管串联形成可编程电阻器之后，形成与每个可编程电阻器电连通的字线，并且在每个字线上形成绝缘层。接下来，沉积和蚀刻绝缘间隔层以暴露导电插塞。然后将捆扎层覆盖并与导电塞接触。

2. 发明授权

US06166426A Lateral bipolar transistors and systems using such 有权
标题翻译：侧面双极晶体管和使用这种系统的系统
公开(公告)号：US06166426A
公开(公告)日：2000-12-26
申请号：US233871
申请日：1999-01-20
申请人： Kirk D. Prall , Mike P. Violette
发明人： Kirk D. Prall , Mike P. Violette
IPC分类号： H01L21/331 , H01L21/8222 , H01L21/8249 , H01L27/06 , H01L27/082 , H01L29/735 , H01L27/102 , H01L29/70 , H01L31/11
CPC分类号： H01L29/6625 , H01L21/8222 , H01L21/8249 , H01L27/0623 , H01L27/082 , H01L29/735
摘要： A substantially concentric lateral bipolar transistor and the method of forming same. A base region is disposed about a periphery of an emitter region, and a collector region is disposed about a periphery of the base region to form the concentric lateral bipolar transistor of the invention. A gate overlies the substrate and at least a portion of the base region. At least one electrical contact is formed connecting the base and the gate, although a plurality of contacts may be formed. A further bipolar transistor is formed according to the following method of the invention. A base region is formed in a substrate and a gate region is formed overlying at least a portion of the base region. Emitter and collector terminals are formed on opposed sides of the base region. The gage is used as a mask during first and second ion implants. During the first ion implant the ions bombard the substrate from a first direction to grade a base/emitter junction, and during the second ion implant ions bombard the substrate from a second direction to grade a base/collector junction. Also a lateral bipolar transistor having a decreased base width as a result of implanting ions after fabrication of collector and emitter regions to enlarge the collector and emitter regions, thereby decreasing the base region and increasing gain.
摘要翻译：基本同心的横向双极晶体管及其形成方法。基极区域围绕发射极区域的周边设置，并且集电极区域围绕基极区域的周边设置以形成本发明的同心横向双极晶体管。栅极覆盖衬底和基极区域的至少一部分。形成连接基座和栅极的至少一个电触头，尽管可以形成多个触点。根据本发明的以下方法形成另外的双极晶体管。在基板中形成基极区域，并且形成覆盖基极区域的至少一部分的栅极区域。发射极和集电极端子形成在基极区域的相对侧上。在第一和第二离子植入物期间，将量规用作掩模。在第一离子注入期间，离子从第一方向轰击衬底以分级基极/发射极结，并且在第二离子注入期间，离子从第二方向轰击衬底以对基极/集电极结进行分级。另外，作为在集电极和发射极区域制造之后注入离子的结果，具有减小的基极宽度的横向双极晶体管，以扩大集电极和发射极区域，从而减小基极区域并增加增益。

3. 发明授权

US07087468B2 Method for forming conductors in semiconductor devices 有权
公开(公告)号：US07087468B2
公开(公告)日：2006-08-08
申请号：US10081915
申请日：2002-02-22
申请人： Fernando Gonzalez , Gurtej S. Sandhu , Mike P. Violette
发明人： Fernando Gonzalez , Gurtej S. Sandhu , Mike P. Violette
IPC分类号： H01L21/82
CPC分类号： H01L21/76804 , H01L21/28518 , H01L21/76895 , H01L21/76897 , H01L27/10 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： A memory device wherein a diode is serially connected to a programmable resistor and is in electrical communication with a buried digit line. An electrically conductive plug is electrically interposed between the digit line and a strapping layer, thereby creating a double metal scheme wherein the strapping layer is a second metal layer overlying metal wordlines. In a method of a first embodiment the strapping material is electrically connected to the digit line through a planar landing pad overlying the conductive plug. An insulative material is sloped to the planar landing pad in order to provide a surface conducive to the formation of the strapping material. In a method of a second embodiment diodes are formed, each having a maximum width equal to f, which is equal to the minimum photolithographic limit of the photolithographic equipment being used, and distanced one from the other along a length of the digit line by a maximum distance equal to f; at least portions of the diodes are masked; at least a portion of an insulative material interposed between two diodes is removed to expose the buried digit line; and the conductive plug is formed in contact with the exposed portion of the buried digit line. After the formation of a programmable resistor in series with the diode a wordline is formed in electrical communication with each of the programmable resistors, and an insulative layer is formed overlying each wordline. Next an insulative spacer layer is deposited and etched to expose the conductive plug. The strapping layer is then formed overlying and in contact with the conductive plug.

4. 发明授权

US06670713B2 Method for forming conductors in semiconductor devices 有权
公开(公告)号：US06670713B2
公开(公告)日：2003-12-30
申请号：US10326690
申请日：2002-12-20
申请人： Fernando Gonzalez , Gurtej S. Sandhu , Mike P. Violette
发明人： Fernando Gonzalez , Gurtej S. Sandhu , Mike P. Violette
IPC分类号： H01L23528
CPC分类号： H01L21/76804 , H01L21/28518 , H01L21/76895 , H01L21/76897 , H01L27/10 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： A memory device wherein a diode is serially connected to a programmable resistor and is in electrical communication with a buried digit line. An electrically conductive plug is electrically interposed between the digit line and a strapping layer, thereby creating a double metal scheme wherein the strapping layer is a second metal layer overlying metal wordlines. In a method of a first embodiment the strapping material is electrically connected to the digit line through a planar landing pad overlying the conductive plug. An insulative material is sloped to the planar landing pad in order to provide a surface conducive to the formation of the strapping material. In a method of a second embodiment diodes are formed, each having a maximum width equal to f, which is equal to the minimum photolithographic limit of the photolithographic equipment being used, and distanced one from the other along a length of the digit line by a maximum distance equal to f; at least portions of the diodes are masked; at least a portion of an insulative material interposed between two diodes is removed to expose the buried digit line; and the conductive plug is formed in contact with the exposed portion of the buried digit line. After the formation of a programmable resistor in series with the diode a wordline is formed in electrical communication with each of the programmable resistors, and an insulative layer is formed overlying each wordline. Next an insulative spacer layer is deposited and etched to expose the conductive plug. The strapping layer is then formed overlying and in contact with the conductive plug.

5. 发明授权

US06653733B1 Conductors in semiconductor devices 失效
标题翻译：半导体器件导体
公开(公告)号：US06653733B1
公开(公告)日：2003-11-25
申请号：US08604751
申请日：1996-02-23
申请人： Fernando Gonzalez , Gurtej S. Sandhu , Mike P. Violette
发明人： Fernando Gonzalez , Gurtej S. Sandhu , Mike P. Violette
IPC分类号： H01L2352
CPC分类号： H01L21/76804 , H01L21/28518 , H01L21/76895 , H01L21/76897 , H01L27/10 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： A memory device wherein a diode is serially connected to a programmable resistor and is in electrical communication with a buried digit line. An electrically conductive plug is electrically interposed between the digit line and a strapping layer, thereby creating a double metal scheme wherein the strapping layer is a second metal layer overlying metal wordlines. In a method of a first embodiment the strapping material is electrically connected to the digit line through a planar landing pad overlying the conductive plug. An insulative material is sloped to the planar landing pad in order to provide a surface conducive to the formation of the strapping material. In a method of a second embodiment diodes are formed, each having a maximum width equal to f, which is equal to the minimum photolithographic limit of the photolithographic equipment being used, and distanced one from the other along a length of the digit line by a maximum distance equal to f; at least portions of the diodes are masked; at least a portion of an insulative material interposed between two diodes is removed to expose the buried digit line; and the conductive plug is formed in contact with the exposed portion of the buried digit line. After the formation of a programmable resistor in series with the diode a wordline is formed in electrical communication with each of the programmable resistors, and an insulative layer is formed overlying each wordline. Next an insulative spacer layer is deposited and etched to expose the conductive plug. The strapping layer is then formed overlying and in contact with the conductive plug.
摘要翻译：一种存储器件，其中二极管串联连接到可编程电阻并与埋地数字线电连通。导电插头电插入数字线和捆扎层之间，从而产生双金属方案，其中捆扎层是覆盖金属字线的第二金属层。在第一实施例的方法中，捆扎材料通过覆盖在导电插塞上的平面着陆垫电连接到数字线。绝缘材料倾斜到平面着陆垫，以提供有利于形成捆扎材料的表面。在第二实施例的方法中，形成二极管，每个二极管具有等于f的最大宽度，其等于所使用的光刻设备的最小光刻极限，并且沿着数字线的长度彼此间隔一个最大距离等于f; 二极管的至少部分被掩蔽; 插入在两个二极管之间的绝缘材料的至少一部分被去除以露出掩埋的数字线; 并且导电插塞形成为与掩埋的数字线的暴露部分接触。在与二极管串联形成可编程电阻器之后，形成与每个可编程电阻器电连通的字线，并且在每个字线上形成绝缘层。接下来，沉积和蚀刻绝缘间隔层以暴露导电插塞。然后将捆扎层覆盖并与导电塞接触。

6. 发明授权

US06893957B2 Method of forming a dual damascene interconnect by selective metal deposition 失效
标题翻译：通过选择性金属沉积形成双镶嵌互连的方法
公开(公告)号：US06893957B2
公开(公告)日：2005-05-17
申请号：US10038305
申请日：2002-01-02
申请人： Jigish D. Trivedi , Mike P. Violette
发明人： Jigish D. Trivedi , Mike P. Violette
IPC分类号： H01L21/285 , H01L21/44 , H01L21/4763 , H01L21/768 , H01L23/48
CPC分类号： H01L21/76877 , H01L21/28562 , H01L21/76879
摘要： A dual damascene process is disclosed, in which a contact via and trench pattern is etched into insulating layer(s). The via is first partially filled by selective metal (e.g., tungsten) deposition, thereby forming a partial plug that raises the floor and reduces the effective aspect ratio of the trench and via structure. The remaining portion of the contact via is then filled with a more conductive material (e.g., aluminum). This deposition also at least partially fills the overlying trench to form metal runners. In the illustrated embodiment, hot aluminum deposition fills the portion of the contact via left unoccupied by the selective deposition and overfills into the trench. A further, cold aluminum deposition then follows, topping off the trench prior to planarization. The dual damascene structure thus exhibits a raised floor relative to conventional dual damascene metallization, while still retaining the conduction benefits of aluminum through a significant portion of the contact and the metal runner formed in the trench.
摘要翻译：公开了一种双镶嵌工艺，其中接触通孔和沟槽图案被蚀刻到绝缘层中。首先通过选择性金属（例如钨）沉积来部分地填充通孔，从而形成部分插头，其使地板上升并降低沟槽和通孔结构的有效纵横比。接触通孔的剩余部分然后用更导电的材料（例如铝）填充。该沉积还至少部分地填充上覆的沟槽以形成金属流道。在所示实施例中，热铝沉积通过左侧未被占用的选择性沉积填充接触部分，并且过度填充到沟槽中。然后再进行冷铝沉积，然后在平坦化之前将沟槽顶起来。因此，双镶嵌结构相对于传统的双镶嵌金属化显示出高的地板，同时仍然保持铝通过形成在沟槽中的大部分接触和金属流道的传导优点。

7. 发明授权

US06489665B2 Lateral bipolar transistor 有权
标题翻译：侧面双极晶体管
公开(公告)号：US06489665B2
公开(公告)日：2002-12-03
申请号：US09742706
申请日：2000-12-20
申请人： Kirk D. Prall , Mike P. Violette
发明人： Kirk D. Prall , Mike P. Violette
IPC分类号： H01L27082
CPC分类号： H01L29/6625 , H01L21/8222 , H01L21/8249 , H01L27/0623 , H01L27/082 , H01L29/735
摘要： A substantially concentric lateral bipolar transistor and the method of forming same. A base region is disposed about a periphery of an emitter region, and a collector region is disposed about a periphery of the base region to form the concentric lateral bipolar transistor of the invention. A gate overlies the substrate and at least a portion of the base region. At least one electrical contact is formed connecting the base and the gate, although a plurality of contacts may be formed. A further bipolar transistor is formed according to the following method of the invention. A base region is formed in a substrate and a gate region is formed overlying at least a portion of the base region. Emitter and collector terminals are formed on opposed sides of the base region. The gate is used as a mask during first and second ion implants. During the first ion implant the ions bombard the substrate from a first direction to grade a base/emitter junction, and during the second ion implant ions bombard the substrate from a second direction to grade a base/collector junction. Also a lateral bipolar transistor having a decreased base width as a result of implanting ions after fabrication of collector and emitter regions to enlarge the collector and emitter regions, thereby decreasing the base region and increasing gain.
摘要翻译：基本同心的横向双极晶体管及其形成方法。基极区域围绕发射极区域的周边设置，并且集电极区域围绕基极区域的周边设置以形成本发明的同心横向双极晶体管。栅极覆盖衬底和基极区域的至少一部分。形成连接基座和栅极的至少一个电触头，尽管可以形成多个触点。根据本发明的以下方法形成另外的双极晶体管。在基板中形成基极区域，并且形成覆盖基极区域的至少一部分的栅极区域。发射极和集电极端子形成在基极区域的相对侧上。在第一和第二离子注入期间，门用作掩模。在第一离子注入期间，离子从第一方向轰击衬底以分级基极/发射极结，并且在第二离子注入期间，离子从第二方向轰击衬底以对基极/集电极结进行分级。另外，作为在制造集电极和发射极区域之后注入离子的结果，具有减小的基极宽度的横向双极晶体管，以扩大集电极和发射极区域，从而减小基极区域并增加增益。

8. 发明授权

US06376284B1 Method of fabricating a memory device 失效
标题翻译：制造存储器件的方法
公开(公告)号：US06376284B1
公开(公告)日：2002-04-23
申请号：US09570614
申请日：2000-05-12
申请人： Fernando Gonzalez , Gurtej S. Sandhu , Mike P. Violette
发明人： Fernando Gonzalez , Gurtej S. Sandhu , Mike P. Violette
IPC分类号： H01L2182
CPC分类号： H01L21/76804 , H01L21/28518 , H01L21/76895 , H01L21/76897 , H01L27/10 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： A memory device wherein a diode is serially connected to a programmable resistor and is in electrical communication with a buried digit line. An electrically conductive plug is electrically interposed between the digit line and a strapping layer, thereby creating a double metal scheme wherein the strapping layer is a second metal layer overlying metal wordlines. In a method of a first embodiment the strapping material is electrically connected to the digit line through a planar landing pad overlying the conductive plug. An insulative material is sloped to the planar landing pad in order to provide a surface conducive to the formation of the strapping material. In a method of a second embodiment diodes are formed, each having a maximum width equal to f, which is equal to the minimum photolithographic limit of the photolithographic equipment being used, and distanced one from the other along a length of the digit line by a maximum distance equal to f; at least portions of the diodes are masked; at least a portion of an insulative material interposed between two diodes is removed to expose the buried digit line; and the conductive plug is formed in contact with the exposed portion of the buried digit line. After the formation of a programmable resistor in series with the diode a wordline is formed in electrical communication with each of the programmable resistors, and an insulative layer is formed overlying each wordline. Next an insulative spacer layer is deposited and etched to expose the conductive plug. The strapping layer is then formed overlying and in contact with the conductive plug.
摘要翻译：一种存储器件，其中二极管串联连接到可编程电阻并与埋地数字线电连通。导电插头电插入数字线和捆扎层之间，从而产生双金属方案，其中捆扎层是覆盖金属字线的第二金属层。在第一实施例的方法中，捆扎材料通过覆盖在导电插塞上的平面着陆垫电连接到数字线。绝缘材料倾斜到平面着陆垫，以提供有利于形成捆扎材料的表面。在第二实施例的方法中，形成二极管，每个二极管具有等于f的最大宽度，其等于所使用的光刻设备的最小光刻极限，并且沿着数字线的长度彼此间隔一个最大距离等于f; 二极管的至少部分被掩蔽; 插入在两个二极管之间的绝缘材料的至少一部分被去除以露出掩埋的数字线; 并且导电插塞形成为与掩埋的数字线的暴露部分接触。在与二极管串联形成可编程电阻器之后，形成与每个可编程电阻器电连通的字线，并且在每个字线上形成绝缘层。接下来，沉积和蚀刻绝缘间隔层以暴露导电插塞。然后将捆扎层覆盖并与导电塞接触。

9. 发明授权

US6127236A Method of forming a lateral bipolar transistor 有权
标题翻译：形成横向双极晶体管的方法
公开(公告)号：US6127236A
公开(公告)日：2000-10-03
申请号：US131454
申请日：1998-08-10
申请人： Kirk D. Prall , Mike P. Violette
发明人： Kirk D. Prall , Mike P. Violette
IPC分类号： H01L21/331 , H01L21/8222 , H01L21/8249 , H01L27/06 , H01L27/082 , H01L29/735
CPC分类号： H01L29/6625 , H01L21/8222 , H01L21/8249 , H01L27/0623 , H01L27/082 , H01L29/735
摘要： A substantially concentric lateral bipolar transistor and the method of forming same. A base region is disposed about a periphery of an emitter region, and a collector region is disposed about a periphery of the base region to form the concentric lateral bipolar transistor of the invention. A gate overlies the substrate and at least a portion of the base region. At least one electrical contact is formed connecting the base and the gate, although a plurality of contacts may be formed. A further bipolar transistor is formed according to the following method of the invention. A base region is formed in a substrate and a gate region is formed overlying at least a portion of the base region. Emitter and collector terminals are formed on opposed sides of the base region. The gate is used as a mask during first and second ion implants. During the first ion implant the ions bombard the substrate from a first direction to grade a base/emitter junction, and during the second ion implant ions bombard the substrate from a second direction to grade a base/collector junction. Also a lateral bipolar transistor having a decreased base width as a result of implanting ions after fabrication of collector and emitter regions to enlarge the collector and emitter regions, thereby decreasing the base region and increasing gain.
摘要翻译：基本同心的横向双极晶体管及其形成方法。基极区域围绕发射极区域的周边设置，并且集电极区域围绕基极区域的周边设置以形成本发明的同心横向双极晶体管。栅极覆盖基板和基极区域的至少一部分。形成连接基座和栅极的至少一个电触头，尽管可以形成多个触点。根据本发明的以下方法形成另外的双极晶体管。在基板中形成基极区域，并且形成覆盖基极区域的至少一部分的栅极区域。发射极和集电极端子形成在基极区域的相对侧上。在第一和第二离子注入期间，门用作掩模。在第一离子注入期间，离子从第一方向轰击衬底以分级基极/发射极结，并且在第二离子注入期间，离子从第二方向轰击衬底以对基极/集电极结进行分级。另外，作为在集电极和发射极区域制造之后注入离子的结果，具有减小的基极宽度的横向双极晶体管，以扩大集电极和发射极区域，从而减小基极区域并增加增益。

10. 发明授权

US08022385B2 Memory devices with buried lines 有权
标题翻译：具有埋线的存储器件
公开(公告)号：US08022385B2
公开(公告)日：2011-09-20
申请号：US11471236
申请日：2006-06-20
申请人： Fernando Gonzalez , Gurtej S. Sandhu , Mike P. Violette
发明人： Fernando Gonzalez , Gurtej S. Sandhu , Mike P. Violette
IPC分类号： H01L47/00
CPC分类号： H01L21/76804 , H01L21/28518 , H01L21/76895 , H01L21/76897 , H01L27/10 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： A memory device wherein a diode is serially connected to a programmable resistor and is in electrical communication with a buried digit line. An electrically conductive plug is electrically interposed between the digit line and a strapping layer, thereby creating a double metal scheme wherein the strapping layer is a second metal layer overlying metal wordlines. In a method of a first embodiment the strapping material is electrically connected to the digit line through a planar landing pad overlying the conductive plug. An insulative material is sloped to the planar landing pad in order to provide a surface conducive to the formation of the strapping material.
摘要翻译：一种存储器件，其中二极管串联连接到可编程电阻并与埋地数字线电连通。导电插头电插入数字线和捆扎层之间，从而产生双金属方案，其中捆扎层是覆盖金属字线的第二金属层。在第一实施例的方法中，捆扎材料通过覆盖在导电插塞上的平面着陆垫电连接到数字线。绝缘材料倾斜到平面着陆垫，以提供有利于形成捆扎材料的表面。

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