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1. 发明授权

US07053444B2 Method and apparatus for a flash memory device comprising a source local interconnect 失效
公开(公告)号：US07053444B2
公开(公告)日：2006-05-30
申请号：US11105834
申请日：2005-04-14
申请人： Kirk D. Prall , Chun Chen
发明人： Kirk D. Prall , Chun Chen
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L21/76831 , H01L21/76895 , H01L21/76897 , H01L27/115
摘要： A method for forming a flash memory device having a local interconnect connecting source regions of a plurality of transistors within a sector allows for a highly selective wet etch of a dielectric region overlying the source region. An embodiment of the method comprises the use of an etch-resistant layer covering various features such as any gate oxide remaining over the source region, spacers along sidewalls of the transistor stacks, and a capping layer of the transistor. An in-process semiconductor device resulting from the inventive method is also disclosed.

2. 发明授权

US07956402B2 Double-doped polysilicon floating gate 有权
标题翻译：双掺杂多晶硅浮栅
公开(公告)号：US07956402B2
公开(公告)日：2011-06-07
申请号：US11970843
申请日：2008-01-11
申请人： Chun Chen , Kirk D. Prall
发明人： Chun Chen , Kirk D. Prall
IPC分类号： H01L29/788
CPC分类号： H01L29/42332 , H01L21/28273 , H01L29/42324 , H01L29/7883
摘要： The present invention provides a method and apparatus for forming a double-doped polysilicon floating gate in a semiconductor memory element. The method includes forming a first dielectric layer on a semiconductor substrate and forming a floating gate above the first dielectric layer, the floating gate comprised of a first layer doped with a first type of dopant material and a second layer doped with a second type of dopant material that is opposite the first type of dopant material in the first layer. The method further includes forming a second dielectric layer above the floating gate, forming a control gate above the second dielectric layer, and forming a source and a drain in the substrate.
摘要翻译：本发明提供一种在半导体存储元件中形成双掺杂多晶硅浮动栅极的方法和装置。该方法包括在半导体衬底上形成第一介电层并在第一介电层上形成浮置栅极，浮置栅极包括掺杂有第一类掺杂剂材料的第一层和掺杂有第二类掺杂剂的第二层与第一层中的第一种掺杂剂材料相反的材料。该方法还包括在浮置栅极上形成第二电介质层，在第二电介质层上形成控制栅极，以及在衬底中形成源极和漏极。

3. 发明授权

US08102714B2 Programming methods for multi-level memory devices 有权
标题翻译：多级存储器件的编程方法
公开(公告)号：US08102714B2
公开(公告)日：2012-01-24
申请号：US12699658
申请日：2010-02-03
申请人： Chun Chen , Kirk D. Prall
发明人： Chun Chen , Kirk D. Prall
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483
摘要： A method is provided for programming a memory cell. The memory cell is fabricated on a substrate and comprises a source region, a drain region, a floating gate, and a control gate. The memory cell has a threshold voltage selectively configurable into one of at least three programming states. The method includes generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region. The method further includes injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate. A selected threshold voltage for the memory cell corresponding to a selected one of the programming states is generated by applying a different selected gate voltage.
摘要翻译：提供了一种用于对存储器单元进行编程的方法。存储单元制造在衬底上，并且包括源极区域，漏极区域，浮动栅极和控制栅极。存储单元具有可选地配置为至少三个编程状态之一的阈值电压。该方法包括通过在漏极区域和源极区域之间施加漏极 - 源极偏置电压来在漏极区域和源极区域之间产生漏极电流。该方法还包括通过向控制栅极施加栅极电压将热电子从漏极电流注入到浮置栅极。通过施加不同的选择的栅极电压来产生对应于选择的一个编程状态的存储单元的选定的阈值电压。

4. 发明申请

US20090046508A1 Programming methods for multi-level flash EEPROMs 失效
标题翻译：多级闪存EEPROM的编程方法
公开(公告)号：US20090046508A1
公开(公告)日：2009-02-19
申请号：US11496969
申请日：2006-08-01
申请人： Chun Chen , Kirk D. Prall
发明人： Chun Chen , Kirk D. Prall
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C11/5628 , G11C16/0483
摘要： A method is provided for programming a memory cell of an electrically erasable programmable read only memory. The memory cell is fabricated on a substrate and comprises a source region, a drain region, a floating gate, and a control gate. The memory cell has a threshold voltage selectively configurable into one of at least three programming states. The method includes generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region. The method further includes injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate. A selected threshold voltage for the memory cell corresponding to a selected one of the programming states is generated by applying a selected constant drain-to-source bias voltage and a selected gate voltage.
摘要翻译：提供了一种用于对电可擦除可编程只读存储器的存储单元进行编程的方法。存储单元制造在衬底上，并且包括源极区域，漏极区域，浮动栅极和控制栅极。存储单元具有可选地配置为至少三个编程状态之一的阈值电压。该方法包括通过在漏极区域和源极区域之间施加漏极 - 源极偏置电压来在漏极区域和源极区域之间产生漏极电流。该方法还包括通过向控制栅极施加栅极电压将热电子从漏极电流注入到浮置栅极。通过施加所选择的恒定的漏极 - 源极偏置电压和所选择的栅极电压来产生对应于所选择的编程状态的存储单元的选定阈值电压。

5. 发明授权

US07417280B2 Method and apparatus for a flash memory device comprising a source local interconnect 有权
标题翻译：一种用于包括源局部互连的闪存器件的方法和装置
公开(公告)号：US07417280B2
公开(公告)日：2008-08-26
申请号：US11440646
申请日：2006-05-24
申请人： Kirk D. Prall , Chun Chen
发明人： Kirk D. Prall , Chun Chen
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L21/76831 , H01L21/76895 , H01L21/76897 , H01L27/115
摘要： A method for forming a flash memory device having a local interconnect connecting source regions of a plurality of transistors within a sector allows for a highly selective wet etch of a dielectric region overlying the source region. An embodiment of the method comprises the use of an etch-resistant layer covering various features such as any gate oxide remaining over the source region, spacers along sidewalls of the transistor stacks, and a capping layer of the transistor. An in-process semiconductor device resulting from the inventive method is also disclosed.
摘要翻译：用于形成具有连接在扇区内的多个晶体管的源极区域的局部互连的快闪存储器件的方法允许覆盖源极区域的电介质区域的高度选择性的湿蚀刻。该方法的一个实施例包括使用覆盖各种特征的耐蚀刻层，例如在源极区域上残留的任何栅极氧化物，沿着晶体管叠层的侧壁的间隔物，以及晶体管的覆盖层。还公开了由本发明方法得到的过程中半导体器件。

6. 发明授权

US07338856B2 Double-doped polysilicon floating gate 有权
标题翻译：双掺杂多晶硅浮栅
公开(公告)号：US07338856B2
公开(公告)日：2008-03-04
申请号：US10649050
申请日：2003-08-27
申请人： Chun Chen , Kirk D. Prall
发明人： Chun Chen , Kirk D. Prall
IPC分类号： H01L21/336 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/42332 , H01L21/28273 , H01L29/42324 , H01L29/7883
摘要： The present invention provides a method and apparatus for forming a double-doped polysilicon floating gate in a semiconductor memory element. The method includes forming a first dielectric layer on a semiconductor substrate and forming a floating gate above the first dielectric layer, the floating gate comprised of a first layer doped with a first type of dopant material and a second layer doped with a second type of dopant material that is opposite the first type of dopant material in the first layer. The method further includes forming a second dielectric layer above the floating gate, forming a control gate above the second dielectric layer, and forming a source and a drain in the substrate.
摘要翻译：本发明提供一种在半导体存储元件中形成双掺杂多晶硅浮动栅极的方法和装置。该方法包括在半导体衬底上形成第一介电层并在第一介电层上形成浮置栅极，浮置栅极包括掺杂有第一类掺杂剂材料的第一层和掺杂有第二类掺杂剂的第二层与第一层中的第一种掺杂剂材料相反的材料。该方法还包括在浮置栅极上形成第二电介质层，在第二电介质层上形成控制栅极，以及在衬底中形成源极和漏极。

7. 发明授权

US07035145B2 Programming methods for multi-level flash EEPROMs 失效
公开(公告)号：US07035145B2
公开(公告)日：2006-04-25
申请号：US10998697
申请日：2004-11-29
申请人： Chun Chen , Kirk D. Prall
发明人： Chun Chen , Kirk D. Prall
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483
摘要： A method is provided for programming a memory cell of an electrically erasable programmable read only memory. The memory cell is fabricated on a substrate and comprises a source region, a drain region, a floating gate, and a control gate. The memory cell has a threshold voltage selectively configurable into one of at least three programming states. The method includes generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region. The method further includes injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate. A selected threshold voltage for the memory cell corresponding to a selected one of the programming states is generated by applying a selected constant drain-to-source bias voltage and a selected gate voltage.

8. 发明授权

US06624024B1 Method and apparatus for a flash memory device comprising a source local interconnect 有权
标题翻译：一种用于包括源局部互连的闪存器件的方法和装置
公开(公告)号：US06624024B1
公开(公告)日：2003-09-23
申请号：US10232221
申请日：2002-08-29
申请人： Kirk D. Prall , Chun Chen
发明人： Kirk D. Prall , Chun Chen
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L21/76831 , H01L21/76895 , H01L21/76897 , H01L27/115
摘要： A method for forming a flash memory device having a local interconnect connecting source regions of a plurality of transistors within a sector allows for a highly-selective wet etch of a dielectric region overlying the source region. An embodiment of the method comprises the use of an etch-resistant layer covering various features such as any gate oxide remaining over the source region, spacers along sidewalls of the transistor stacks, and a capping layer of the transistor. An in-process semiconductor device resulting from the inventive method is also disclosed.
摘要翻译：用于形成具有连接在扇区内的多个晶体管的源极区域的局部互连的闪存器件的方法允许覆盖源极区域的电介质区域的高选择性湿蚀刻。该方法的一个实施例包括使用覆盖各种特征的耐蚀刻层，例如在源极区域上残留的任何栅极氧化物，沿着晶体管叠层的侧壁的间隔物，以及晶体管的覆盖层。还公开了由本发明方法得到的过程中半导体器件。

9. 发明申请

US20100142273A1 PROGRAMMING METHODS FOR MULTI-LEVEL MEMORY DEVICES 有权
标题翻译：多级存储器件的编程方法
公开(公告)号：US20100142273A1
公开(公告)日：2010-06-10
申请号：US12699658
申请日：2010-02-03
申请人： CHUN CHEN , Kirk D. Prall
发明人： CHUN CHEN , Kirk D. Prall
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483
摘要： A method is provided for programming a memory cell. The memory cell is fabricated on a substrate and comprises a source region, a drain region, a floating gate, and a control gate. The memory cell has a threshold voltage selectively configurable into one of at least three programming states. The method includes generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region. The method further includes injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate. A selected threshold voltage for the memory cell corresponding to a selected one of the programming states is generated by applying a different selected gate voltage.
摘要翻译：提供了一种用于对存储单元进行编程的方法。存储单元制造在衬底上，并且包括源极区域，漏极区域，浮动栅极和控制栅极。存储单元具有可选地配置为至少三个编程状态之一的阈值电压。该方法包括通过在漏极区域和源极区域之间施加漏极 - 源极偏置电压来在漏极区域和源极区域之间产生漏极电流。该方法还包括通过向控制栅极施加栅极电压将热电子从漏极电流注入到浮置栅极。通过施加不同的选择的栅极电压来产生对应于选择的一个编程状态的存储单元的选定的阈值电压。

10. 发明授权

US07684249B2 Programming methods for multi-level memory devices 失效
标题翻译：多级存储器件的编程方法
公开(公告)号：US07684249B2
公开(公告)日：2010-03-23
申请号：US11496969
申请日：2006-08-01
申请人： Chun Chen , Kirk D. Prall
发明人： Chun Chen , Kirk D. Prall
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483
摘要： A method is provided for programming a memory cell. The memory cell is fabricated on a substrate and comprises a source region, a drain region, a floating gate, and a control gate. The memory cell has a threshold voltage selectively configurable into one of at least three programming states. The method includes generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region. The method further includes injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate. A selected threshold voltage for the memory cell corresponding to a selected one of the programming states is generated by applying a different selected gate voltage.
摘要翻译：提供了一种用于对存储器单元进行编程的方法。存储单元制造在衬底上，并且包括源极区域，漏极区域，浮动栅极和控制栅极。存储单元具有可选地配置为至少三个编程状态之一的阈值电压。该方法包括通过在漏极区域和源极区域之间施加漏极 - 源极偏置电压来在漏极区域和源极区域之间产生漏极电流。该方法还包括通过向控制栅极施加栅极电压将热电子从漏极电流注入到浮置栅极。通过施加不同的选择的栅极电压来产生对应于选择的一个编程状态的存储单元的选定的阈值电压。

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