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51. 发明申请

US20060240635A1 Self-aligned STI SONOS 有权
标题翻译：自对准STI SONOS
公开(公告)号：US20060240635A1
公开(公告)日：2006-10-26
申请号：US11113509
申请日：2005-04-25
申请人： Hidehiko Shiraiwa , Mark Randolph , Yu Sun
发明人： Hidehiko Shiraiwa , Mark Randolph , Yu Sun
IPC分类号： H01L21/76
CPC分类号： H01L21/76229 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L27/11573
摘要： Methods 300 and 350 are disclosed for fabricating shallow isolation trenches and structures in multi-bit SONOS flash memory devices. One method aspect 300 comprises forming 310 a multi-layer dielectric-charge trapping-dielectric stack 420 over a substrate 408 of the wafer 402, for example, an ONO stack 420, removing 312 the multi-layer dielectric-charge trapping-dielectric stack 420 in a periphery region 406 of the wafer 402, thereby defining a multi-layer dielectric-charge trapping-dielectric stack 420 in a core region 404 of the wafer 402. The method 300 further comprises forming 314 a gate dielectric layer 426 over the periphery region 406 of the substrate 408, forming 316 a first polysilicon layer 428 over the multi-layer dielectric-charge trapping-dielectric stack 420 in the core region 402 and the gate dielectric 426 in the periphery region 406 , then concurrently forming 318 an isolation trench 438 in the substrate 408 in the core region 404 and in the periphery region 406. Thereafter, the isolation trenches are filled 326 with a dielectric material 446, and a second polysilicon layer 452 that is formed 332 over the first polysilicon layer 428 and the filled trenches 438, forming an self-aligned STI structure 446. The method 300 avoids ONO residual stringers at STI edges in the periphery region, reduces active region losses, reduces thinning of the periphery gate oxide and the ONO at the STI edge, and reduces dopant diffusion during isolation implantations due to reduced thermal process steps.
摘要翻译：公开了用于在多位SONOS闪存器件中制造浅隔离沟槽和结构的方法300和350。一个方法方面300包括在晶片402的衬底408（例如，ONO堆叠420）上形成310多层介电电荷俘获 - 电介质堆叠420，去除312多层介电电荷俘获 - 电介质堆叠420 在晶片402的外围区域406中，由此在晶片402的芯区域404中限定多层介电电荷捕获 - 电介质叠层420.方法300还包括在周边区域314上形成314栅极电介质层426 406，在芯区域402中的多层介电 - 电荷俘获 - 电介质堆叠层420和周边区域406中的栅极电介质426之间形成316第一多晶硅层428，然后同时形成318隔离沟槽438 在核心区域404和外围区域406中的衬底408中。此后，隔离沟槽用介电材料446填充326，第二多晶硅层452形成为332o 形成第一多晶硅层428和填充沟槽438，形成自对准STI结构446.方法300避免在外围区域的STI边缘处的ONO残余桁条，减少有源区域损耗，减少外围栅极氧化物的稀化和 ONO在STI边缘，并且由于减少的热处理步骤，在隔离注入期间减少掺杂剂扩散。

52. 发明授权

US07003464B2 Dialog recognition and control in a voice browser 有权
标题翻译：语音浏览器中的对话框识别和控制
公开(公告)号：US07003464B2
公开(公告)日：2006-02-21
申请号：US10339067
申请日：2003-01-09
申请人： James Ferrans , Jonathan Engelsma , Michael Pearce , Mark Randolph , Jerome Vogedes
发明人： James Ferrans , Jonathan Engelsma , Michael Pearce , Mark Randolph , Jerome Vogedes
IPC分类号： G10L21/00
CPC分类号： H04M1/72561 , G10L15/26 , H04M3/4938 , H04M2207/40 , H04M2250/74
摘要： A voice browser dialog enabler for multimodal dialog uses a multimodal markup document with fields have markup-based forms associated with each field and defining fragments. A voice browser driver resides on a communication device and provides the fragments and identifiers that identify the fragments. A voice browser implementation resides on a remote voice server and receives the fragments from the driver and downloads a plurality of speech grammars. Input speech is matched against those speech grammars associated with the corresponding identifiers received in a recognition request from the voice browser driver.
摘要翻译：用于多模式对话框的语音浏览器对话框启用程序使用多模式标记文档，其中字段具有与每个字段相关联的基于标记的表单并定义片段。语音浏览器驱动程序驻留在通信设备上，并提供标识片段的片段和标识符。语音浏览器实现驻留在远程语音服务器上，并从驱动程序接收片段并下载多个语音语法。输入语音与来自语音浏览器驱动程序的识别请求中接收到的相应标识符相关联的那些语音语法相匹配。

53. 发明申请

US20050250278A1 Methods and apparatus for wordline protection in flash memory devices 有权
标题翻译：闪存设备中字线保护的方法和装置
公开(公告)号：US20050250278A1
公开(公告)日：2005-11-10
申请号：US10839614
申请日：2004-05-05
申请人： Mark Randolph
发明人： Mark Randolph
IPC分类号： H01L21/8246 , H01L21/8247 , H01L27/115 , H01L21/8238 , H01L21/336 , H01L21/8234 , H01L21/8244 , H01L29/76
CPC分类号： H01L27/115 , H01L27/11517 , H01L27/11568
摘要： Methods and structures are presented for protecting flash memory wordlines and memory cells from process-related charging during fabrication. Undoped polysilicon is formed at the ends of doped polysilicon wordlines to create resistors through which process charges are discharged to a doped polysilicon discharge structure coupled with a substrate. The wordlines, resistors, and the discharge structure can be formed as a unitary patterned polysilicon structure, where the wordline and discharge portions are selectively doped to be conductive and the resistor portions are substantially undoped to provide a resistance high enough to allow normal cell operation after fabrication while providing a discharge path for process-related charging during fabrication.
摘要翻译：提出了用于在制造期间保护闪存字线和存储器单元免于与处理相关的充电的方法和结构。在掺杂多晶硅字线的端部形成未掺杂的多晶硅，以产生电阻器，通过该电阻将工艺电荷放电到与衬底耦合的掺杂多晶硅放电结构。字线，电阻器和放电结构可以形成为整体图案化多晶硅结构，其中字线和放电部分被选择性地掺杂为导电的，并且电阻器部分基本上未被掺杂以提供足够高的电阻以允许在同时在制造期间提供用于处理相关充电的放电路径。

54. 发明申请

US20050077567A1 Memory cell array with staggered local inter-connect structure 失效
标题翻译：具有交错局部互连结构的存储单元阵列
公开(公告)号：US20050077567A1
公开(公告)日：2005-04-14
申请号：US10685044
申请日：2003-10-14
申请人： Mark Randolph , Sameer Haddad , Timothy Thurgate , Richard Fastow
发明人： Mark Randolph , Sameer Haddad , Timothy Thurgate , Richard Fastow
IPC分类号： G11C16/04 , H01L21/8246 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11568 , G11C16/0483 , H01L27/115 , H01L27/11521
摘要： A memory cell array comprises a two dimensional array of memory cells fabricated on a semiconductor substrate. The memory cells are arranged in a plurality of rows and a plurality columns. Each column of memory cells comprising a plurality of alternating channel regions and source/drain regions. A conductive interconnect is positioned above each source/drain region and coupled to only one other source/drain region. The one other source/drain region is in a second column that is adjacent to the column. The conductive interconnects are positioned such that every other conductive interconnect connects to the adjacent column to a right side of the column and every other conductive interconnect connects to adjacent column to the left side of the column. A plurality of source/drain control lines extends between adjacent columns of memory cells and electrically couples to each conductive interconnect that couples between the adjacent columns.
摘要翻译：存储单元阵列包括在半导体衬底上制造的存储器单元的二维阵列。存储单元布置成多行和多列。每列存储单元包括多个交替沟道区和源极/漏极区。导电互连位于每个源极/漏极区域上方并且仅耦合到另一个源极/漏极区域。另一个源/漏区位于与该列相邻的第二列中。导电互连被定位成使得每隔一个导电布线连接到列的右侧的相邻列，并且每隔一个导电布线连接到列的左侧的相邻列。多个源极/漏极控制线在相邻列的存储器单元之间延伸，并且电耦合到在相邻列之间耦合的每个导电互连。

55. 发明授权

US06465303B1 Method of manufacturing spacer etch mask for silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile memory 有权
标题翻译：制造用于氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）型非易失性存储器的间隔物蚀刻掩模的方法
公开(公告)号：US06465303B1
公开(公告)日：2002-10-15
申请号：US09885490
申请日：2001-06-20
申请人： Mark T. Ramsbey , Narbeh Derhacobian , Janet Wang , Angela Hui , Tuan Pham , Ravi Sunkavalli , Mark Randolph
发明人： Mark T. Ramsbey , Narbeh Derhacobian , Janet Wang , Angela Hui , Tuan Pham , Ravi Sunkavalli , Mark Randolph
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573
摘要： One aspect of the present invention relates to a method of forming spacers in a silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile semiconductor memory device, involving the steps of providing a semiconductor substrate having a core region and periphery region, the core region containing SONOS type memory cells and the periphery region containing gate transistors; implanting a first implant into the core region and a first implant into the periphery region of the semiconductor substrate; forming a spacer material over the semiconductor substrate; masking the core region and forming spacers adjacent the gate transistors in the periphery region; and implanting a second implant into the periphery region of the semiconductor substrate.
摘要翻译：本发明的一个方面涉及一种在氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）型非易失性半导体存储器件中形成间隔物的方法，包括以下步骤：提供具有核心区域和外围区域的半导体衬底，包含SONOS型存储单元的核心区域和包含栅极晶体管的外围区域; 将第一注入植入到所述芯区域中，并将第一注入植入所述半导体衬底的周边区域; 在所述半导体衬底上形成隔离材料; 掩蔽所述芯区域并在所述周边区域中形成与所述栅极晶体管相邻的间隔物; 以及将第二植入物植入所述半导体衬底的周边区域。

56. 发明授权

US06168637A Use of a large angle implant and current structure for eliminating a critical mask in flash memory processing 失效
标题翻译：使用大角度注入和电流结构来消除闪存处理中的关键掩模
公开(公告)号：US06168637A
公开(公告)日：2001-01-02
申请号：US08991322
申请日：1997-12-16
申请人： Mark Randolph , Timothy J. Thurgate , Scott D. Luning
发明人： Mark Randolph , Timothy J. Thurgate , Scott D. Luning
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , Y10T29/41
摘要： A method and system for providing a flash memory cell on a semiconductor is disclosed. In one aspect, the method and system include providing a plurality of gate stacks and providing a drain implant at an angle. The plurality of gate stacks define a plurality of drain areas and a plurality of source areas. The angle is measured from a direction perpendicular to the surface of the semiconductor. The angle allows the plurality of gate stacks to block the drain implant from reaching the plurality of source areas. In another aspect, the method and system include providing a plurality of gate stacks and providing a source implant at an angle. The plurality of gate stacks define a plurality of drain areas and a plurality of source areas. The angle is measured from a direction perpendicular to the surface of the semiconductor. The angle allows the plurality of gate stacks to block the source implant from reaching the plurality of drain areas.
摘要翻译：公开了一种用于在半导体上提供闪存单元的方法和系统。在一个方面，该方法和系统包括提供多个栅极堆叠并以一定角度提供漏极注入。多个栅极堆叠限定多个漏极区域和多个源极区域。该角度是从垂直于半导体表面的方向测量的。该角度允许多个栅极堆叠阻挡漏极植入物到达多个源极区域。在另一方面，该方法和系统包括提供多个栅极叠层并以一定角度提供源植入物。多个栅极堆叠限定多个漏极区域和多个源极区域。该角度是从垂直于半导体表面的方向测量的。该角度允许多个栅极堆叠阻挡源植入物到达多个漏极区域。

57. 发明授权

US6127222A Non-self-aligned side channel implants for flash memory cells 失效
标题翻译：用于闪存单元的非自对准侧通道植入物
公开(公告)号：US6127222A
公开(公告)日：2000-10-03
申请号：US991687
申请日：1997-12-16
申请人： Scott D. Luning , Mark Randolph
发明人： Scott D. Luning , Mark Randolph
IPC分类号： H01L21/336
CPC分类号： H01L29/66825
摘要： A system and method for providing a flash memory cell on a semiconductor substrate are disclosed. The system and method include providing a side implant and providing an implant in at least one of a drain or a source of the flash memory cell.
摘要翻译：公开了一种用于在半导体衬底上提供闪存单元的系统和方法。该系统和方法包括提供侧植入物并在闪速存储器单元的漏极或源极中的至少一个中提供植入物。

58. 发明授权

US08215314B2 Photochemical tissue bonding 有权
标题翻译：光化学组织粘结
公开(公告)号：US08215314B2
公开(公告)日：2012-07-10
申请号：US10732032
申请日：2003-12-09
申请人： Barbara Chan , Timothy Shane Johnson , Irene E. Kochevar , Mark Randolph , Robert W. Redmond , Jonathan M. Winograd
发明人： Barbara Chan , Timothy Shane Johnson , Irene E. Kochevar , Mark Randolph , Robert W. Redmond , Jonathan M. Winograd
IPC分类号： A61B19/00
CPC分类号： A61B17/11 , A61B2017/00508 , A61B2017/00517 , A61F9/0079 , A61F9/0081 , A61F9/00821 , A61F2009/00842 , A61F2009/00853 , A61F2009/00872 , A61F2009/00887 , A61L24/001 , A61L2430/32 , A61N5/062
摘要： Photochemical tissue boding methods for bonding neural tissues include the application of a photosensitizer to a tissue and/or tissue graft, followed by irradiation with electromagnetic energy to produce a tissue seal. The methods are useful for tissue adhesion, such as in wound closure, tissue grafting, skin grafting, musculoskeletal tissue repair, ligament or tendon repair, neural repair, blood vessel repair and corneal repair.
摘要翻译：用于粘合神经组织的光化学组织编织方法包括将光敏剂施用于组织和/或组织移植物，随后用电磁能照射以产生组织密封。该方法可用于组织粘连，例如伤口闭合，组织移植，皮肤移植，肌肉骨骼组织修复，韧带或肌腱修复，神经修复，血管修复和角膜修复。

59. 发明申请

US20110152898A1 TISSUE ENGINEERED CONSTRUCTS 审中-公开
标题翻译：组织工程建设
公开(公告)号：US20110152898A1
公开(公告)日：2011-06-23
申请号：US12991643
申请日：2009-05-08
申请人： Irene E. Kochevar , Robert W. Redmond , Anne C. O'Neill , Mark Randolph
发明人： Irene E. Kochevar , Robert W. Redmond , Anne C. O'Neill , Mark Randolph
IPC分类号： A61F2/02
CPC分类号： A61B17/1128
摘要： The present invention relates to a field of biocompatible membranes, tubes and conduits which comprising a photosensitizer which is capable of being crosslinked to form a three dimensional structure which can be implanted into a subject to assist in tissue bonding and nerve maintenance and development. Methods of making such membranes, tubes and conduits and kits comprising them are also described.
摘要翻译：本发明涉及生物相容性膜，管和导管领域，其包含能够交联以形成三维结构的光敏剂，该三维结构可被植入受试者以辅助组织粘合和神经维持和发育。还描述了制造这种膜，管和导管以及包括它们的试剂盒的方法。

60. 发明授权

US07561457B2 Select transistor using buried bit line from core 有权
标题翻译：选择晶体管使用埋入位线从核心
公开(公告)号：US07561457B2
公开(公告)日：2009-07-14
申请号：US11465701
申请日：2006-08-18
申请人： Mark Randolph , Zhizheng Liu , Ashot Melik-Martirosian , Yi He , Shankar Sinha
发明人： Mark Randolph , Zhizheng Liu , Ashot Melik-Martirosian , Yi He , Shankar Sinha
IPC分类号： G11C17/00
CPC分类号： G11C5/063 , H01L27/0207 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11531
摘要： A semiconductor device includes a core memory array and a periphery area. The core memory array area includes a group of memory cells. The periphery area includes a group of select transistors. The select transistors are formed at substantially the same pitch as the memory cells in the core memory array and with substantially the same channel length.
摘要翻译：半导体器件包括核心存储器阵列和周边区域。核心存储器阵列区域包括一组存储器单元。外围区域包括一组选择晶体管。选择晶体管以与芯存储器阵列中的存储器单元基本相同的间距形成并具有基本上相同的沟道长度。

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