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    • 52. 发明申请
    • Disposable Stereoscopic Endoscope System
    • 一次性立体内窥镜系统
    • US20090076329A1
    • 2009-03-19
    • US12212625
    • 2008-09-17
    • Wei SuGary Zhang
    • Wei SuGary Zhang
    • A61B1/06A61B1/005
    • A61B1/0607A61B1/0008A61B1/00103A61B1/00193
    • A disposable simultaneous stereo endoscope system is disclosed. The disposable endoscope does not include image relay. Instead, two electronic imaging sensors and solid illumination lighting are arranged inside the endoscope. A demultiplexing beam splitter is used for splitting the two imaging light beams to the two imaging devices. A wedged multi-facet illumination window is used to create an illumination field that is larger than the field of view of the imaging optics. An electrically conductive heat sink is engaged for dissipating the heat generated by the solid light source and also for shielding end side of the endoscope. The disposable endoscope is shielded from electromagnetic interferences. A repeater unit is used to electrically connect the disposable endoscope with a remote receiver and to increase the data transfer rate. An electrical isolation means is provided between the endoscope and an image processing and power conditioning unit to protect the endoscope against electric shock.
    • 公开了一次性同时立体声内窥镜系统。 一次性内窥镜不包括图像继电器。 相反,两个电子成像传感器和固体照明照明布置在内窥镜内部。 解复用分束器用于将两个成像光束分裂成两个成像装置。 楔形多面照明窗用于产生比成像光学系统的视场大的照明场。 导电散热器被接合以消散由固体光源产生的热量并且还用于屏蔽内窥镜的端侧。 一次性内窥镜屏蔽电磁干扰。 中继器单元用于将一次性内窥镜与远程接收器电连接并提高数据传输速率。 在内窥镜和图像处理和功率调节单元之间设置电气隔离装置,以保护内窥镜免受电击。
    • 53. 发明申请
    • Antenna Radiator Assembly and Radio Communications Assembly
    • 天线散热器装配和无线电通信大会
    • US20080272964A1
    • 2008-11-06
    • US10596526
    • 2004-12-07
    • Wei SuGuang Ping Zhou
    • Wei SuGuang Ping Zhou
    • H01Q1/38H01Q1/24
    • H01Q9/045H01Q1/243H01Q1/38
    • An antenna radiator assembly (2) and radio communications assembly (1) comprising a circuit board (5) formed from dielectric layers dielectric layers (21, 22) supporting electrical conductors. The electrical conductors include a feed point conductive trace (23) and conductive sheets (7, 24) comprising a ground plane. An antenna radiator element (8) is spaced from the circuit board (5) and when viewed in plan view there is an overlapping area (25) where most of a surface area of the antenna radiator element (8) overlaps a surface area of the circuit board (26) thereby forming a sandwiched dielectric region (25). A feed point connector (11) couples the antenna radiator element (8) to the feed point conductive trace (23) and a ground connector (10) couples the antenna radiator element (8) to the ground plane. The circuit board dielectric layers (21, 22) in the sandwiched dielectric region (25) are disposed between the antenna radiator element (8) and the ground plane.
    • 一种天线辐射器组件(2)和无线电通信组件(1),包括由支撑电导体的电介质层介质层(21,22)形成的电路板(5)。 电导体包括馈电点导电迹线(23)和包括接地平面的导电片(7,24)。 天线辐射器元件(8)与电路板(5)间隔开,并且当在平面图中观察时,存在重叠区域(25),其中天线辐射器元件(8)的大部分表面区域与 电路板(26),从而形成夹层电介质区域(25)。 馈电点连接器(11)将天线辐射器元件(8)耦合到馈电点导电迹线(23),并且接地连接器(10)将天线辐射器元件(8)耦合到接地平面。 夹在介质区域(25)中的电路板电介质层(21,22)设置在天线辐射体元件(8)和接地平面之间。
    • 55. 发明授权
    • Method for generating test files from scanned test vector pattern drawings
    • 从扫描的测试矢量图形图生成测试文件的方法
    • US06332032B1
    • 2001-12-18
    • US09210529
    • 1998-12-03
    • Gerald T. MichaelWei SuMichael A. Dukes
    • Gerald T. MichaelWei SuMichael A. Dukes
    • G06K962
    • G06T7/0004G01R31/318307G06T2207/30141G06T2207/30148
    • A graphical bitmap image of a scanned test pattern drawing is transformed into a test file in a file format that is readily usable to provide stimuli for computer-aided design (CAD) tools or integrated circuit (IC) testing equipment. A bitmap image of each page of the test pattern drawing is produced as a graphical image of the rows and columns of test pattern data. Non-essential drawing symbols are then removed from the bitmap image, such as the lines used to draw the table. Essential test pattern information is recognized and is converted into a machine readable format by first storing the data in a tabular format having rows and columns which correspond to the rows and columns of the test pattern drawing. The stored test pattern data is then integrated with a machine readable file format which is adaptable to the CAD and IC tool in order to produce the machine readable test file.
    • 扫描的测试图形图形的图形位图图像被转换成文件格式的测试文件,该文件格式易于用于为计算机辅助设计(CAD)工具或集成电路(IC)测试设备提供刺激。 测试图形图的每一页的位图图像被生成为测试图案数据的行和列的图形图像。 然后从位图图像中删除非必需的图形符号,例如用于绘制表格的行。 基本测试图案信息被识别并通过首先以具有与测试图案图形的行和列对应的行和列的表格格式存储数据而被转换成机器可读格式。 然后将存储的测试图案数据与适用于CAD和IC工具的机器可读文件格式集成,以便产生机器可读测试文件。
    • 56. 发明授权
    • Method for generating computer aided design programming circuit designs from scanned images of the design
    • 用于从设计的扫描图像生成计算机辅助设计编程电路设计的方法
    • US06314194B1
    • 2001-11-06
    • US08506943
    • 1995-07-26
    • Gerald T. MichaelWei SuMichael A. Dukes
    • Gerald T. MichaelWei SuMichael A. Dukes
    • G06K900
    • G06K9/00476G06F17/5045
    • A VHSIC hardware description language model is generated from a scanned image of an electronic circuit by: a. producing a bitmap image of a schematic using standard scanning devices that takes a paper drawing and produces an image of a drawing in electronic form where the white and black parts of the drawing image are represented by different values, for example, 0 representing white and 1 representing black; locating and identifying the text portions of the schematic which is used later to tag signal and pin names to reassemble hierarchical schematic drawing sets into models where the links between the various schematic drawings are included in the model; locating and identifying the drawing symbols, such as logic gates, transistors, and resistors, as well as the pins that link one schematic drawing to other schematics in a set of drawings, which is used to type each component in the schematic; locating and identifying the signals (or nets) which is a three stage process where the individual signal paths are located and identified, the inversion circles, which are critical to the correct identification of component function, are located and the ports (connections to signals) for each component are located and identified; integrating the information about component type, ports, inversion circles, and fanout (number of input ports driven by an output port) to uniquely identify each component; and combining the component information with the signal information to provide all of the information required to generate the netlist in the desired form (VHDL, Verilog, EDIF, or other).
    • 通过以下方式从电子电路的扫描图像生成VHSIC硬件描述语言模型:a。 使用采用纸张绘制的标准扫描装置产生原理图的位图图像,并以电子形式产生图形的图像,其中绘制图像的白色和黑色部分由不同的值表示,例如0表示白色和1 代表黑色 定位和识别原理图的文本部分,其稍后用于标记信号和引脚名称以将分层示意图集合重新组合到模型中,其中各种示意图之间的链接包括在模型中; 定位和识别图形符号,例如逻辑门,晶体管和电阻器,以及将一个示意图链接到一组附图中的其他原理图的引脚,其用于在原理图中键入每个部件; 定位和识别信号(或网络),它们是各个信号路径所在和标识的三个阶段过程,对组件功能的正确识别至关重要的反转圆圈和端口(与信号的连接) 为每个组件定位和识别; 集成关于组件类型,端口,反转圆和扇出(由输出端口驱动的输入端口的数量)的信息以唯一地标识每个组件; 以及将组件信息与信号信息组合以提供以所需形式(VHDL,Verilog,EDIF或其他)生成网表所需的所有信息。
    • 58. 发明授权
    • Recursive frequency aging estimation and prediction devices, methods and
computer programs for crystal oscillators
    • 递归频率老化估计和预测装置,晶体振荡器的方法和计算机程序
    • US5790412A
    • 1998-08-04
    • US869341
    • 1997-06-05
    • Wei Su
    • Wei Su
    • G01R23/02G01R29/22G01R23/00
    • G01R23/02G01R29/22
    • A recursive crystal oscillator aging estimation and prediction device is vided comprising a crystal oscillator connected to a calculation means having several software programs, including frequency aging calculation algorithms based on new mathematical models for estimating and predicting frequency aging, respectively. The calculation means, being an oscillator model, and having a means to use a plurality of shifted logarithmic functions which describe the effects of a given frequency output of said crystal oscillator is connected to a frequency correction circuit. When a frequency reference is available, the calculation means performs a plurality of parameter. When a frequency reference is not available, an output of oscillator is compared to an output of the oscillator model of the calculation means, resulting in a frequency error, which is then fed to the crystal oscillator to correct the frequency with the calculation means acting as a temporary frequency reference to correct the frequency error within said frequency output. The present invention also discloses recursive crystal oscillator aging estimation and prediction methods and a computer-readable medium whose contents cause a computer system to recursively estimate and predict the aging of a crystal oscillator, as an article of manufacture.
    • 提供了递归晶体振荡器老化估计和预测装置,其包括连接到具有若干软件程序的计算装置的晶体振荡器,包括基于用于估计和预测频率老化的新数学模型的频率老化计算算法。 作为振荡器模型并且具有使用描述所述晶体振荡器的给定频率输出的影响的多个移位对数函数的装置的计算装置连接到频率校正电路。 当频率参考值可用时,计算装置执行多个参数。 当频率参考不可用时,将振荡器的输出与计算装置的振荡器模型的输出进行比较,导致频率误差,然后将其馈送到晶体振荡器以校正频率,计算装置用作 临时频率参考以校正所述频率输出内的频率误差。 本发明还公开了递归晶体振荡器老化估计和预测方法,以及其内容导致计算机系统递归地估计和预测晶体振荡器的老化的计算机可读介质,作为制造品。
    • 59. 发明授权
    • Built-in self testing for the identification of faulty integrated
circuit chips in a multichip module
    • 内置自检,用于识别多芯片模块中的故障集成电路芯片
    • US5745500A
    • 1998-04-28
    • US734819
    • 1996-10-22
    • Thyagaraju DamarlaMoon J. ChungWei SuGerald T. Michael
    • Thyagaraju DamarlaMoon J. ChungWei SuGerald T. Michael
    • G01R31/28G01R31/3185
    • G01R31/318505G01R31/2884
    • A built-in self test method and circuit identifies a faulty integrated ciit chip in a multichip module. The built-in self test method first applies a test pattern to a multichip module having a plurality of integrated circuit chips and to a reference signal generator, generates a first and second reference signal representing test responses for a fault free multichip module, compresses the outputs from the multichip module into a first and second bit using a first and second linear space compressor, uses exclusive OR logic to combine the first bit with the first reference signal to produce a first fault detection output and to combine the second bit with the second reference signal to produce a second fault detection output, stores the first and second fault detection outputs in a pair of N-bit shift registers; compares the stored outputs to detect a fault condition, and applies a series of recursive logic operations to identify the faulty integrated circuit chip in the multichip module. The built-in self test circuit includes a test pattern generator, a reference signal generator, at least two linear space compressors, at least two N-bit shift registers, and a plurality of logic gates. Identification of the faulty integrated circuit chip in an multichip module using the present invention thereby facilitates the replacement of the specific faulty chip in order to repair the multichip module.
    • 内置的自检方法和电路识别多芯片模块中的故障集成电路芯片。 内置的自检方法首先将测试图案应用于具有多个集成电路芯片的多芯片模块和参考信号发生器,产生表示无故障多芯片模块的测试响应的第一和第二参考信号,压缩输出 使用第一和第二线性空间压缩器从多芯片模块进入第一和第二位,使用异或逻辑将第一位与第一参考信号组合以产生第一故障检测输出并将第二位与第二参考 信号以产生第二故障检测输出,将第一和第二故障检测输出存储在一对N位移位寄存器中; 比较存储的输出以检测故障状况,并应用一系列递归逻辑运算来识别多芯片模块中的故障集成电路芯片。 内置的自检电路包括测试图形发生器,参考信号发生器,至少两个线性空间压缩器,至少两个N位移位寄存器和多个逻辑门。 因此,使用本发明的多芯片模块中的故障集成电路芯片的识别便于更换特定故障芯片以便修复多芯片模块。