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51. 发明申请

US20140156790A1 BITSTREAM PROCESSING USING COALESCED BUFFERS AND DELAYED MATCHING AND ENHANCED MEMORY WRITES 有权
标题翻译：使用加密缓存和延迟匹配和增强存储器写入的BITSTREAM处理
公开(公告)号：US20140156790A1
公开(公告)日：2014-06-05
申请号：US13994129
申请日：2011-12-23
申请人： Vinodh Gopal , Jim D. Guilford , Gilbert M. Wolrich , Wajdi K. Feghail , Deniz Karakoyunlu , Erdinc Ozturk , Martin Dixon , Kahraman Akdemir
发明人： Vinodh Gopal , Jim D. Guilford , Gilbert M. Wolrich , Wajdi K. Feghail , Deniz Karakoyunlu , Erdinc Ozturk , Martin Dixon , Kahraman Akdemir
IPC分类号： H04L29/06
CPC分类号： H04L65/607 , H03M7/30 , H03M7/3086 , H04L65/608 , H04L69/04 , H04L69/22 , H04W28/06
摘要： Methods and apparatus for processing bitstreams and byte streams. According to one aspect, bitstream data is compressed using coalesced string match tokens with delayed matching. A matcher is employed to perform search string match operations using a shortened maximum string length search criteria, resulting in generation of a token stream having data and literal data. A distance match operation is performed on sequentially adjacent tokens to determine if they contain the same distance data. If they do, the len values of the tokens are added through use of a coalesce buffer. Upon detection of a distance non-match, a final coalesced length of a matching string is calculated and output along with the prior matching distance as a coalesced token. Also disclosed is a scheme for writing variable-length tokens into a bitstream under which token data is input into a bit accumulator and written to memory (or cache to be subsequently written to memory) as each token is processed in a manner that eliminates branch mispredict operations associated with detecting whether the bit accumulator is full or close to full.
摘要翻译：用于处理比特流和字节流的方法和装置。根据一个方面，使用具有延迟匹配的合并字符串匹配令牌来压缩比特流数据。使用匹配器来执行搜索字符串匹配操作，使用缩短的最大字符串长度搜索条件，导致生成具有数据和文字数据的令牌流。对顺序相邻的令牌执行距离匹配操作，以确定它们是否包含相同的距离数据。如果这样做，令牌的len值通过使用合并缓冲区来添加。在检测到距离不匹配时，计算匹配串的最终合并长度，并将其与先前匹配距离一起作为合并令牌输出。还公开了一种用于将可变长度令牌写入比特流的方案，在该比特流中，令牌数据被输入到比特累加器中，并且以消除分支错误预测的方式将每个令牌进行处理，并将其写入存储器（或高速缓存以随后写入存储器）检测位累加器是满或接近满的操作。

52. 发明申请

US20140082328A1 METHOD AND APPARATUS TO PROCESS 4-OPERAND SIMD INTEGER MULTIPLY-ACCUMULATE INSTRUCTION 有权
标题翻译：过程4操作的方法和装置SIMD INTEGER MULTIPLY-ACCUMULATE指令
公开(公告)号：US20140082328A1
公开(公告)日：2014-03-20
申请号：US13617021
申请日：2012-09-14
申请人： Vinodh Gopal , Erdinc Ozturk , James D. Guilford , Gilbert M. Wolrich
发明人： Vinodh Gopal , Erdinc Ozturk , James D. Guilford , Gilbert M. Wolrich
IPC分类号： G06F9/302 , G06F9/30
CPC分类号： G06F9/3001 , G06F7/5443 , G06F9/30014 , G06F9/30036 , G06F9/30145 , G06F9/3016 , G06F9/34 , G06F9/3887
摘要： According to one embodiment, a processor includes an instruction decoder to receive an instruction to process a multiply-accumulate operation, the instruction having a first operand, a second operand, a third operand, and a fourth operand. The first operand is to specify a first storage location to store an accumulated value; the second operand is to specify a second storage location to store a first value and a second value; and the third operand is to specify a third storage location to store a third value. The processor further includes an execution unit coupled to the instruction decoder to perform the multiply-accumulate operation to multiply the first value with the second value to generate a multiply result and to accumulate the multiply result and at least a portion of a third value to an accumulated value based on the fourth operand.
摘要翻译：根据一个实施例，处理器包括指令解码器，用于接收处理多重累积运算的指令，该指令具有第一操作数，第二操作数，第三操作数和第四操作数。第一个操作数是指定一个存储累积值的第一个存储位置; 第二操作数是指定存储第一值和第二值的第二存储位置; 并且第三操作数是指定存储第三值的第三存储位置。所述处理器还包括执行单元，其耦合到所述指令解码器以执行所述乘法运算，以将所述第一值乘以所述第二值以产生乘法结果，并将乘法结果和第三值的至少一部分累积到基于第四操作数的累计值。

53. 发明申请

US20130326201A1 PROCESSOR-BASED APPARATUS AND METHOD FOR PROCESSING BIT STREAMS 有权
标题翻译：基于处理器的设备和处理位流的方法
公开(公告)号：US20130326201A1
公开(公告)日：2013-12-05
申请号：US13995494
申请日：2011-12-22
申请人： Vinodh Gopal , James d. Guilford , Gilbert M. Wolrich , Erdinc Ozturk , Wajdi K. Feghali , Kirk S. Yap , Sean M. Gulley , Martin G. Dixon , Robert S. Chappell
发明人： Vinodh Gopal , James d. Guilford , Gilbert M. Wolrich , Erdinc Ozturk , Wajdi K. Feghali , Kirk S. Yap , Sean M. Gulley , Martin G. Dixon , Robert S. Chappell
IPC分类号： G06F9/30
CPC分类号： G06F9/30043 , G06F9/30018 , G06F9/34
摘要： An apparatus and method are described for processing bit streams using bit-oriented instructions. For example, a method according to one embodiment includes the operations of: executing an instruction to get bits for an operation, the instruction identifying a start bit address and a number of bits to be retrieved; retrieving the bits identified by the start bit address and number of bits from a bit-oriented register or cache; and performing a sequence of specified bit operations on the retrieved bits to generate results.
摘要翻译：描述了一种用于使用面向位的指令来处理比特流的装置和方法。例如，根据一个实施例的方法包括以下操作：执行用于获得用于操作的比特的指令，所述指令标识起始比特地址和要检索的比特数; 从面向比特的寄存器或高速缓存中检索由起始位地址和位数标识的位; 并对所检索的位执行指定位操作的序列以产生结果。

54. 发明授权

US08484147B2 Pattern matching 有权
标题翻译：模式匹配
公开(公告)号：US08484147B2
公开(公告)日：2013-07-09
申请号：US12340360
申请日：2008-12-19
申请人： Christopher F. Clark , Vinodh Gopal , Gilbert M. Wolrich
发明人： Christopher F. Clark , Vinodh Gopal , Gilbert M. Wolrich
IPC分类号： G06F17/00 , G06N5/02
CPC分类号： H04L63/1416 , G06F21/552
摘要： A method and apparatus to perform pattern matching is provided. The apparatus includes a first storage to store data representing a first set of pattern components, and a second storage to store data representing a second set of pattern components each corresponding to one or more components of the first set of pattern components. A first pattern matcher is configured to detect in an input stream a first component of one or more patterns and to generate a signal indicative of the detection of the first component. A second pattern matcher is configured to receive the signal from the first pattern matcher and to detect if a second component of the one or more patterns of the set of patterns immediately follows the first component in the input stream.
摘要翻译：提供了执行模式匹配的方法和装置。该装置包括第一存储器，用于存储表示第一组模式组件的数据，以及第二存储器，用于存储表示第二组模式组件的数据，每个模式组件对应于第一组模式组件的一个或多个组件。第一模式匹配器被配置为在输入流中检测一个或多个模式的第一分量，并且生成指示第一分量的检测的信号。第二模式匹配器被配置为从第一模式匹配器接收信号并且检测该模式集合中的一个或多个模式的第二分量是否紧跟在输入流中的第一分量之后。

55. 发明授权

US08380767B2 Polynomial-basis to normal-basis transformation for binary Galois-Fields GF(2m) 有权
标题翻译：对于二值Galois-Fields GF（2m）的正态基变换的多项式
公开(公告)号：US08380767B2
公开(公告)日：2013-02-19
申请号：US11772172
申请日：2007-06-30
申请人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali
发明人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali
IPC分类号： G06F7/72
CPC分类号： G06F7/724
摘要： Basis conversion from polynomial-basis form to normal-basis form is provided for both generic polynomials and special irreducible polynomials in the form of “all ones”, referred to as “all-ones-polynomials” (AOP). Generation and storing of large matrices is minimized by creating matrices on the fly, or by providing an alternate means of computing a result with minimal hardware extensions.
摘要翻译：对于通用多项式和以全1形式的特殊不可约多项式，提供了从多项式基形式到正态形式的基础转换，称为全要素多项式（AOP）。通过在飞行中创建矩阵，或者通过提供以最小的硬件扩展来计算结果的替代方法来最小化大矩阵的生成和存储。

56. 发明授权

US08363828B2 Diffusion and cryptographic-related operations 有权
标题翻译：扩散和加密相关操作
公开(公告)号：US08363828B2
公开(公告)日：2013-01-29
申请号：US12368196
申请日：2009-02-09
申请人： Vinodh Gopal , Kirk Yap , Gilbert Wolrich , Wajdi Feghali , Robert Ottavi , Sean Gulley
发明人： Vinodh Gopal , Kirk Yap , Gilbert Wolrich , Wajdi Feghali , Robert Ottavi , Sean Gulley
IPC分类号： G06F21/00
CPC分类号： G09C1/00 , H04L9/0637 , H04L2209/12
摘要： An embodiment includes at least one processing unit to perform at least first and second sets of diffusion-related operations to produce a resulting block from a data block, and that includes at least one stage and at least one other stage. The at least one stage is to select one of first operands and second operands input to the at least one other stage. The first and second operands are respectively associated with the first and second sets of operations, respectively. The at least one other stage involves arithmetic and logical operations common to both the first and second sets of operations. At least one other processing unit is to perform at least one set of cryptographic-related operations (different, at least in part, from the first and second sets of operations) on at least one of (1) another block to produce the data block and (2) the resulting block.
摘要翻译：一个实施例包括至少一个处理单元，用于执行至少第一和第二组扩散相关操作以从数据块产生结果块，并且其包括至少一个阶段和至少一个其他阶段。所述至少一个级是选择输入至少一个其他级的第一操作数和第二操作数之一。第一和第二操作数分别分别与第一和第二组操作相关联。所述至少一个其他阶段涉及对于第一和第二组操作共同的算术和逻辑运算。至少一个其他处理单元将在（1）另一个块中的至少一个上执行至少一组密码相关操作（至少部分地不同于第一和第二组操作），以产生数据块和（2）得到的块。

57. 发明授权

US08346839B2 Efficient advanced encryption standard (AES) datapath using hybrid rijndael S-box 失效
标题翻译：使用混合rijndael S盒的高效加密标准（AES）数据通路
公开(公告)号：US08346839B2
公开(公告)日：2013-01-01
申请号：US11731159
申请日：2007-03-30
申请人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali , Kirk S. Yap
发明人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali , Kirk S. Yap
IPC分类号： G06F7/52
CPC分类号： H04L9/0631 , G06F9/30007 , H04L2209/12
摘要： The speed at which an AES decrypt operation may be performed in a general purpose processor is increased by providing a separate decrypt data path. The critical path delay of the aes decrypt path is reduced by combining multiply and inverse operations in the Inverse SubBytes transformation. A further decrease in critical path delay in the aes decrypt data path is provided by merging appropriate constants of the inverse mix-column transform into a map function.
摘要翻译：可以通过提供单独的解密数据路径来增加在通用处理器中执行AES解密操作的速度。通过在逆SubBytes变换中组合乘法和逆运算来减少aes解密路径的关键路径延迟。通过将反混合列变换的适当常数合并到映射函数中来提供aes解密数据路径中关键路径延迟的进一步减小。

58. 发明授权

US08301680B2 Apparatus and method to compute reciprocal approximations 失效
标题翻译：用于计算相互近似的装置和方法
公开(公告)号：US08301680B2
公开(公告)日：2012-10-30
申请号：US11963833
申请日：2007-12-23
申请人： Vinodh Gopal , Gilbert M. Wolrich , Wajdi K. Feghali
发明人： Vinodh Gopal , Gilbert M. Wolrich , Wajdi K. Feghali
IPC分类号： G06F7/38 , G06F7/52
CPC分类号： G06F7/4873
摘要： A method and apparatus for reducing memory required to store reciprocal approximations as specified in Institute of Electrical and Electronic Engineers (IEEE) standards such as IEEE 754 is presented. Monotonic properties of the reciprocal function are used to bound groups of values. Efficient bit-vectors are used to represent information in groups resulting in a very compact table representation about four times smaller than storing all of the reciprocal approximations in a table.
摘要翻译：提出了一种用于减少存储相对近似值所需的存储器的方法和装置，如IEEE电气和电子工程师协会（IEEE）标准如IEEE 754所规定。互逆函数的单调属性用于约束值组。有效的比特向量用于表示组中的信息，导致非常紧凑的表格表示比存储表中的所有倒数近似的四倍小。

59. 发明授权

US08229109B2 Modular reduction using folding 有权
标题翻译：使用折叠模块化减少
公开(公告)号：US08229109B2
公开(公告)日：2012-07-24
申请号：US11476432
申请日：2006-06-27
申请人： William C. Hasenplaugh , Gunnar Gaubatz , Vinodh Gopal
发明人： William C. Hasenplaugh , Gunnar Gaubatz , Vinodh Gopal
IPC分类号： G06F7/72
CPC分类号： G06F7/72
摘要： Techniques are described to determine N mod M, where N is a number having a width of n-bits, and M is a number having a width of m-bits. The techniques, generally, involve determining N′=Nrt2f mod M+NL and, subsequently, determining N′ mod M.
摘要翻译：描述技术来确定N mod M，其中N是具有n位宽度的数，M是具有m位宽度的数。这些技术通常涉及确定N'= Nrt2f mod M + NL，并且随后确定N'mod M.

60. 发明授权

US08005210B2 Modulus scaling for elliptic-curve cryptography 有权
标题翻译：椭圆曲线加密的模量缩放
公开(公告)号：US08005210B2
公开(公告)日：2011-08-23
申请号：US11772165
申请日：2007-06-30
申请人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali
发明人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali
IPC分类号： H04K1/00 , H04L9/00 , H04L9/28 , G06F7/72
CPC分类号： G06F7/72 , G06F5/01 , G06F7/723 , G06F7/725 , H04L9/3066
摘要： Modulus scaling applied a reduction techniques decreases time to perform modular arithmetic operations by avoiding shifting and multiplication operations. Modulus scaling may be applied to both integer and binary fields and the scaling multiplier factor is chosen based on a selected reduction technique for the modular arithmetic operation.
摘要翻译：使用缩减技术的模量缩放通过避免移位和乘法运算来减少执行模数运算的时间。可以将模量缩放应用于整数和二进制字段，并且基于用于模数运算的选定的缩减技术来选择缩放倍数因子。

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