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1. 发明申请

US20180181394A1 PROCESSOR INSTRUCTIONS FOR DETERMINING TWO MINIMUM AND TWO MAXIMUM VALUES 审中-公开
公开(公告)号：US20180181394A1
公开(公告)日：2018-06-28
申请号：US15387823
申请日：2016-12-22
申请人： Vinodh Gopal , James D. Guilford
发明人： Vinodh Gopal , James D. Guilford
IPC分类号： G06F9/30 , G06F15/80
CPC分类号： G06F9/30021 , G06F9/3001 , G06F9/30109 , G06F9/30112 , G06F15/8007
摘要： Processor instructions for determining two minimum and two maximum values and associated apparatus and methods. The instructions include various 2MIN instructions for determining the two smallest values among three or four input values and 2MAX instructions for determining the two largest values among three or four input values. The 2MIN instructions employ two operands, with the first operand in some of the variations storing concatenated min1 and min2 values in a first register and a scr2 comparison value or two src2 concatenated src2 values in a second register. Comparators are used to implement hardware logic for determining whether the scr2 value(s) is/are less than each of min1 and min2. Based on the hardware logic, the smallest two values among min1, min2, and src2 (or both src2 values) are stored as concatenated values in the first register. The 2MAX instructions are implemented in a similar manner, except the comparisons are whether the scr2 value(s) is/are greater than each of max1 and max2 values. 128-bit 2MIN and 2MAX SIMD instructions are also provided for processing two 64-bit data-paths in parallel.

2. 发明授权

US09990201B2 Multiplication instruction for which execution completes without writing a carry flag 有权
公开(公告)号：US09990201B2
公开(公告)日：2018-06-05
申请号：US12645383
申请日：2009-12-22
申请人： Vinodh Gopal , James D. Guilford , Wajdi K. Feghali , Erdine Ozturk , Gilbert M. Wolrich , Martin G. Dixon , Mark C. Davis , Sean P. Mirkes , Alexandre Farcy , Bret L. Toll , Maxim Loktyukhin
发明人： Vinodh Gopal , James D. Guilford , Wajdi K. Feghali , Erdine Ozturk , Gilbert M. Wolrich , Martin G. Dixon , Mark C. Davis , Sean P. Mirkes , Alexandre Farcy , Bret L. Toll , Maxim Loktyukhin
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44 , G06F9/30
CPC分类号： G06F9/30094 , G06F9/30014
摘要： A method in one aspect may include receiving a multiply instruction. The multiply instruction may indicate a first source operand and a second source operand. A product of the first and second source operands may be stored in one or more destination operands indicated by the multiply instruction. Execution of the multiply instruction may complete without writing a carry flag. Other methods are also disclosed, as are apparatus, systems, and instructions on machine-readable medium.

3. 发明申请

US20170177404A1 HARDWARE ACCELERATORS AND METHODS FOR STATEFUL COMPRESSION AND DECOMPRESSION OPERATIONS 审中-公开
公开(公告)号：US20170177404A1
公开(公告)日：2017-06-22
申请号：US14975847
申请日：2015-12-20
申请人： Tracy G. Drysdale , James D. Guilford , Vinodh Gopal , Gilbert M. Wolrich , James T. Kukunas
发明人： Tracy G. Drysdale , James D. Guilford , Vinodh Gopal , Gilbert M. Wolrich , James T. Kukunas
IPC分类号： G06F9/46 , G06F9/50
CPC分类号： G06F9/466 , G06F9/5061 , G06F9/544 , G06F9/546 , G06F2209/509
摘要： Methods and apparatuses relating to stateful compression and decompression operations are described. In one embodiment, hardware processor includes a core to execute a thread and offload at least one of a compression and decompression thread, and a hardware compression and decompression accelerator to execute the at least one of the compression and decompression thread to consume input and generate output data, wherein the hardware compression and decompression accelerator is coupled to a plurality of input buffers to store the input data, a plurality of output buffers to store the output data, an input buffer descriptor array with an entry for each respective input buffer, an input buffer response descriptor array with a corresponding response entry for each respective input buffer, an output buffer descriptor array with an entry for each respective output buffer, and an output buffer response descriptor array with a corresponding response entry for each respective output buffer.

4. 发明申请

US20160085555A1 TECHNOLOGIES FOR EFFICIENT LZ77-BASED DATA DECOMPRESSION 有权
标题翻译：高效的基于LZ77的数据分解技术
公开(公告)号：US20160085555A1
公开(公告)日：2016-03-24
申请号：US14494766
申请日：2014-09-24
申请人： Vinodh Gopal , Sean M. Gulley , James D. Guilford
发明人： Vinodh Gopal , Sean M. Gulley , James D. Guilford
IPC分类号： G06F9/38 , G06F12/02 , G06F12/08 , H03M7/30
CPC分类号： H03M7/3086 , G06F3/0604 , G06F3/064 , G06F3/065 , G06F3/0673 , G06F9/3818 , G06F9/3863 , G06F12/023 , G06F12/0875 , G06F2212/1044 , G06F2212/452 , H03M7/3091 , H03M7/6005 , H03M7/6017
摘要： Technologies for data decompression include a computing device that reads a symbol tag byte from an input stream. The computing device determines whether the symbol can be decoded using a fast-path routine, and if not, executes a slow-path routine to decompress the symbol. The slow-path routine may include data-dependent branch instructions that may be unpredictable using branch prediction hardware. For the fast-path routine, the computing device determines a next symbol increment value, a literal increment value, a data length, and an offset based on the tag byte, without executing an unpredictable branch instruction. The computing device sets a source pointer to either literal data or reference data as a function of the tag byte, without executing an unpredictable branch instruction. The computing device may set the source pointer using a conditional move instruction. The computing device copies the data and processes remaining symbols. Other embodiments are described and claimed.
摘要翻译：用于数据解压缩的技术包括从输入流读取符号标记字节的计算设备。计算设备确定是否可以使用快速路径例程来解码符号，如果不是，则执行慢路径例程来解压缩符号。慢路径例程可以包括使用分支预测硬件可能不可预测的依赖于数据的分支指令。对于快速路径例程，计算设备基于标签字节确定下一个符号递增值，文字增量值，数据长度和偏移量，而不执行不可预测的分支指令。计算设备将源指针设置为文字数据或引用数据作为标记字节的函数，而不执行不可预测的分支指令。计算设备可以使用条件移动指令来设置源指针。计算设备复制数据并处理剩余符号。描述和要求保护其他实施例。

5. 发明授权

US09270460B2 Instructions to perform JH cryptographic hashing in a 256 bit data path 有权
标题翻译：在256位数据路径中执行JH加密散列的指令
公开(公告)号：US09270460B2
公开(公告)日：2016-02-23
申请号：US13995457
申请日：2011-12-22
申请人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal , James D. Guilford , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
发明人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal , James D. Guilford , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
IPC分类号： G06F21/00 , H04L9/14 , H04L9/32 , G06F9/30 , G06F9/38 , G06F21/60
CPC分类号： H04L9/14 , G06F9/30007 , G06F9/30032 , G06F9/30036 , G06F9/3893 , G06F21/602 , H04L9/3239
摘要： A method is described. The method includes executing one or more JH_SBOX_L instructions to perform S-Box mappings and a linear (L) transformation on a JH state and executing one or more JH_P instructions to perform a permutation function on the JH state once the S-Box mappings and the L transformation have been performed.
摘要翻译：描述了一种方法。该方法包括执行一个或多个JH_SBOX_L指令以在JH状态上执行S-Box映射和线性（L）变换，并且一旦S-Box映射和 L变换。

6. 发明授权

US09235414B2 SIMD integer multiply-accumulate instruction for multi-precision arithmetic 有权
标题翻译：用于多精度算术的SIMD整数乘法累加指令
公开(公告)号：US09235414B2
公开(公告)日：2016-01-12
申请号：US13992728
申请日：2011-12-19
申请人： Vinodh Gopal , Gilbert M. Wolrich , Erdinc Ozturk , James D. Guilford , Kirk S. Yap , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
发明人： Vinodh Gopal , Gilbert M. Wolrich , Erdinc Ozturk , James D. Guilford , Kirk S. Yap , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
IPC分类号： G06F7/52 , G06F9/30 , G06F9/38
CPC分类号： G06F9/3001 , G06F9/30036 , G06F9/30101 , G06F9/3893
摘要： A multiply-and-accumulate (MAC) instruction allows efficient execution of unsigned integer multiplications. The MAC instruction indicates a first vector register as a first operand, a second vector register as a second operand, and a third vector register as a destination. The first vector register stores a first factor, and the second vector register stores a partial sum. The MAC instruction is executed to multiply the first factor with an implicit second factor to generate a product, and to add the partial sum to the product to generate a result. The first factor, the implicit second factor and the partial sum have a same data width and the product has twice the data width. The most significant half of the result is stored in the third vector register, and the least significant half of the result is stored in the second vector register.
摘要翻译：乘法和累加（MAC）指令允许有效执行无符号整数乘法。 MAC指令表示作为第一操作数的第一向量寄存器，作为第二操作数的第二向量寄存器和作为目的地的第三向量寄存器。第一向量寄存器存储第一因子，第二向量寄存器存储部分和。执行MAC指令以将第一因子与隐含的第二因子相乘以生成乘积，并将部分和添加到乘积以生成结果。第一个因素，隐含的第二个因子和部分和具有相同的数据宽度，产品的数据宽度是两倍。结果的最大一半存储在第三向量寄存器中，结果的最低有效半存储在第二向量寄存器中。

7. 发明授权

US08929539B2 Instructions to perform Groestl hashing 有权
标题翻译：执行Groestl散列的说明
公开(公告)号：US08929539B2
公开(公告)日：2015-01-06
申请号：US13992461
申请日：2011-12-22
申请人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal , James D. Guilford , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
发明人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal , James D. Guilford , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
IPC分类号： H04K1/00 , H04L9/28 , G06F13/14 , G06F9/30 , H04L9/06
CPC分类号： H04L9/28 , G06F9/30018 , G06F9/30036 , G06F9/30109 , G06F13/14 , H04L9/0631 , H04L9/0643
摘要： A method is described. The method includes executing an instruction to perform one or more Galois Field (GF) multiply by 2 operations on a state matrix and executing an instruction to combine results of the one or more GF multiply by 2 operations with exclusive or (XOR) functions to generate a result matrix.
摘要翻译：描述了一种方法。该方法包括执行在状态矩阵上乘以2次操作的一个或多个伽罗瓦域（GF）的指令，并且执行将所述一个或多个GF乘以2个运算的结果与异或（XOR）函数相结合的指令，以产生一个结果矩阵。

8. 发明申请

US20140019764A1 METHOD FOR SIGNING AND VERIFYING DATA USING MULTIPLE HASH ALGORITHMS AND DIGESTS IN PKCS 有权
标题翻译：使用PKCS中的多个哈希算法和数据签名和验证数据的方法
公开(公告)号：US20140019764A1
公开(公告)日：2014-01-16
申请号：US13712401
申请日：2012-12-12
申请人： VINODH GOPAL , SEAN M. GULLEY , JAMES D. GUILFORD , WAJDI K. FEGHALI
发明人： VINODH GOPAL , SEAN M. GULLEY , JAMES D. GUILFORD , WAJDI K. FEGHALI
IPC分类号： H04L9/32
CPC分类号： H04L9/3247
摘要： Methods, systems, and apparatuses are disclosed for signing and verifying data using multiple hash algorithms and digests in PKCS including, for example, retrieving, at the originating computing device, a message for signing at the originating computing device to yield a signature for the message; identifying multiple hashing algorithms to be supported by the signature; for each of the multiple hashing algorithms identified to be supported by the signature, hashing the message to yield multiple hashes of the message corresponding to the multiple hashing algorithms identified; constructing a single digest having therein each of the multiple hashes of the messages corresponding to the multiple hashing algorithms identified and further specifying the multiple hashing algorithms to be supported by the signature; applying a signing algorithm to the single digest using a private key of the originating computing device to yield the signature for the message; and distributing the message and the signature to receiving computing devices. Other related embodiments are disclosed.
摘要翻译：公开了用于使用PKCS中的多个散列算法和摘要来签名和验证数据的方法，系统和装置，包括例如在起始计算设备处检索用于在始发计算设备处签名的消息以产生该消息的签名 ; 识别签名支持的多个散列算法; 对于被标识为被签名支持的多个散列算法中的每一个，散列消息以产生与识别的多个散列算法相对应的消息的多个哈希; 构建其中具有与识别的多个散列算法相对应的消息的多个散列中的每一个的单个摘要，并进一步指定要由签名支持的多个散列算法; 使用始发计算设备的私钥将签名算法应用于单个摘要以产生该消息的签名; 并将消息和签名分发给接收计算设备。公开了其他相关实施例。

9. 发明申请

US20140016773A1 INSTRUCTIONS PROCESSORS, METHODS, AND SYSTEMS TO PROCESS BLAKE SECURE HASHING ALGORITHM 有权
标题翻译：指令处理程序，方法和系统处理BLAKE安全冲洗算法
公开(公告)号：US20140016773A1
公开(公告)日：2014-01-16
申请号：US13976741
申请日：2011-12-22
申请人： Gilbert M. Wolrich , Kirk S. Yap , James D. Guilford , Vinodh Gopal , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
发明人： Gilbert M. Wolrich , Kirk S. Yap , James D. Guilford , Vinodh Gopal , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
IPC分类号： H04L9/28
CPC分类号： H04L9/28 , G06F9/30007 , G06F9/30036 , G06F21/72 , H04L9/0643 , H04L2209/122
摘要： A method of an aspect includes receiving an instruction indicating a first source having at least one set of four state matrix data elements, which represent a complete set of four inputs to a G function of a cryptographic hashing algorithm. The algorithm uses a sixteen data element state matrix, and alternates between updating data elements in columns and diagonals. The instruction also indicates a second source having data elements that represent message and constant data. In response to the instruction, a result is stored in a destination indicated by the instruction. The result includes updated state matrix data elements including at least one set of four updated state matrix data elements. Each of the four updated state matrix data elements represents a corresponding one of the four state matrix data elements of the first source, which has been updated by the G function.
摘要翻译：一种方面的方法包括：接收指示具有至少一组四个状态矩阵数据元素的第一源的指令，其表示对密码散列算法的G函数的四个输入的完整集合。该算法使用十六个数据元素状态矩阵，并在列和对角线之间更新数据元素。该指令还指示具有表示消息和常数数据的数据元素的第二源。响应该指令，结果存储在指令指示的目的地中。结果包括更新的状态矩阵数据元素，包括至少一组四个更新的状态矩阵数据元素。四个更新的状态矩阵数据元素中的每一个表示已由G功能更新的第一源的四个状态矩阵数据元素中的相应一个。

10. 发明申请

US20130283064A1 METHOD AND APPARATUS TO PROCESS SHA-1 SECURE HASHING ALGORITHM 有权
标题翻译：用于处理SHA-1安全冲洗算法的方法和装置
公开(公告)号：US20130283064A1
公开(公告)日：2013-10-24
申请号：US13976293
申请日：2011-12-22
申请人： Kirk S. Yap , Gilbert M. Wolrich , James D. Guilford , Vinodh Gopal , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
发明人： Kirk S. Yap , Gilbert M. Wolrich , James D. Guilford , Vinodh Gopal , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
IPC分类号： G06F21/60
CPC分类号： G06F21/602 , G06F9/30007 , H04L9/0643 , H04L9/3239 , H04L2209/122
摘要： A processor includes an instruction decoder to receive a first instruction to process a SHA-1 hash algorithm, the first instruction having a first operand to store a SHA-1 state, a second operand to store a plurality of messages, and a third operand to specify a hash function, and an execution unit coupled to the instruction decoder to perform a plurality of rounds of the SHA-1 hash algorithm on the SHA-1 state specified in the first operand and the plurality of messages specified in the second operand, using the hash function specified in the third operand.
摘要翻译：处理器包括指令解码器，用于接收处理SHA-1散列算法的第一指令，所述第一指令具有用于存储SHA-1状态的第一操作数，存储多个消息的第二操作数和第三操作数，指定散列函数，以及执行单元，其耦合到指令解码器，以在第一操作数中指定的SHA-1状态和第二操作数中指定的多个消息中执行多轮SHA-1散列算法，使用第三个操作数中指定的散列函数。

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