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1. 发明申请

US20100161536A1 PATTERN MATCHING 有权
标题翻译：图案匹配
公开(公告)号：US20100161536A1
公开(公告)日：2010-06-24
申请号：US12340360
申请日：2008-12-19
申请人： Christopher F. Clark , Vinodh Gopal , Gilbert M. Wolrich
发明人： Christopher F. Clark , Vinodh Gopal , Gilbert M. Wolrich
IPC分类号： G06N5/02
CPC分类号： H04L63/1416 , G06F21/552
摘要： A method and apparatus to perform pattern matching is provided. The apparatus includes a first storage to store data representing a first set of pattern components, and a second storage to store data representing a second set of pattern components each corresponding to one or more components of the first set of pattern components. A first pattern matcher is configured to detect in an input stream a first component of one or more patterns and to generate a signal indicative of the detection of the first component. A second pattern matcher is configured to receive the signal from the first pattern matcher and to detect if a second component of the one or more patterns of the set of patterns immediately follows the first component in the input stream.
摘要翻译：提供了执行模式匹配的方法和装置。该装置包括第一存储器，用于存储表示第一组模式组件的数据，以及第二存储器，用于存储表示第二组模式组件的数据，每个模式组件对应于第一组模式组件的一个或多个组件。第一模式匹配器被配置为在输入流中检测一个或多个模式的第一分量，并且生成指示第一分量的检测的信号。第二模式匹配器被配置为从第一模式匹配器接收信号并且检测该模式集合中的一个或多个模式的第二分量是否紧跟在输入流中的第一分量之后。

2. 发明申请

US20120150887A1 PATTERN MATCHING 审中-公开
标题翻译：图案匹配
公开(公告)号：US20120150887A1
公开(公告)日：2012-06-14
申请号：US12963438
申请日：2010-12-08
申请人： Christopher F. Clark , Vinodh Gopal , Gilbert M. Wolrich
发明人： Christopher F. Clark , Vinodh Gopal , Gilbert M. Wolrich
IPC分类号： G06F17/30
CPC分类号： G06F16/90344
摘要： An embodiment may include circuitry to determine, at least in part, whether one or more reference patterns are present in a data stream in a packet flow. The circuitry may include first pattern matching circuitry communicatively coupled to second pattern matching circuitry. The first pattern matching circuitry may determine, based at least in part upon one or more deterministic pattern matching operations, whether at least one portion of the one or more reference patterns is present in the stream. If the first pattern matching circuitry determines that the at least one portion of the one or more reference patterns is present in the stream, the second pattern matching circuitry may determine, based at least in part upon one or more pattern matching threads, whether at least one other portion of the one or more reference patterns is present in the stream. Many modifications are possible without departing from this embodiment.
摘要翻译：一个实施例可以包括至少部分地确定分组流中的数据流中是否存在一个或多个参考模式的电路。电路可以包括通信地耦合到第二模式匹配电路的第一模式匹配电路。第一模式匹配电路可以至少部分地基于一个或多个确定性模式匹配操作来确定流中是否存在一个或多个参考模式的至少一部分。如果第一模式匹配电路确定一个或多个参考模式的至少一部分存在于流中，则第二模式匹配电路可以至少部分地基于一个或多个模式匹配线程来确定是否至少一个或多个参考图案的另一部分存在于流中。在不脱离本实施例的情况下，可以进行许多修改。

3. 发明授权

US08484147B2 Pattern matching 有权
标题翻译：模式匹配
公开(公告)号：US08484147B2
公开(公告)日：2013-07-09
申请号：US12340360
申请日：2008-12-19
申请人： Christopher F. Clark , Vinodh Gopal , Gilbert M. Wolrich
发明人： Christopher F. Clark , Vinodh Gopal , Gilbert M. Wolrich
IPC分类号： G06F17/00 , G06N5/02
CPC分类号： H04L63/1416 , G06F21/552
摘要： A method and apparatus to perform pattern matching is provided. The apparatus includes a first storage to store data representing a first set of pattern components, and a second storage to store data representing a second set of pattern components each corresponding to one or more components of the first set of pattern components. A first pattern matcher is configured to detect in an input stream a first component of one or more patterns and to generate a signal indicative of the detection of the first component. A second pattern matcher is configured to receive the signal from the first pattern matcher and to detect if a second component of the one or more patterns of the set of patterns immediately follows the first component in the input stream.
摘要翻译：提供了执行模式匹配的方法和装置。该装置包括第一存储器，用于存储表示第一组模式组件的数据，以及第二存储器，用于存储表示第二组模式组件的数据，每个模式组件对应于第一组模式组件的一个或多个组件。第一模式匹配器被配置为在输入流中检测一个或多个模式的第一分量，并且生成指示第一分量的检测的信号。第二模式匹配器被配置为从第一模式匹配器接收信号并且检测该模式集合中的一个或多个模式的第二分量是否紧跟在输入流中的第一分量之后。

4. 发明授权

US09270698B2 Filter for network intrusion and virus detection 有权
标题翻译：过滤网络入侵和病毒检测
公开(公告)号：US09270698B2
公开(公告)日：2016-02-23
申请号：US12346734
申请日：2008-12-30
申请人： Vinodh Gopal , Christopher F. Clark , Gilbert M. Wolrich , Wajdi K. Feghali
发明人： Vinodh Gopal , Christopher F. Clark , Gilbert M. Wolrich , Wajdi K. Feghali
IPC分类号： G06F11/00 , H04L29/06 , G06F7/02 , G06F21/56
CPC分类号： H04L63/145 , G06F7/02 , G06F17/30949 , G06F17/30985 , G06F21/567 , G06F2207/025 , H04L63/0245 , H04L63/1416
摘要： Methods and apparatus to perform string matching for network packet inspection are disclosed. In some embodiments there is a set of string matching slice circuits, each slice circuit of the set being configured to perform string matching steps in parallel with other slice circuits. Each slice circuit may include an input window storing some number of bytes of data from an input data steam. The input window of data may be padded if necessary, and then multiplied by a polynomial modulo an irreducible Galois-field polynomial to generate a hash index. A storage location of a memory corresponding to the hash index may be accessed to generate a slice-hit signal of a set of H slice-hit signals. The slice-hit signal may be provided to an AND-OR logic array where the set of H slice-hit signals is logically combined into a match result.
摘要翻译：公开了对网络包检测进行字符串匹配的方法和装置。在一些实施例中，存在一组字符串匹配限幅电路，该组的每个片电路被配置为与其他片电路并行地执行字符串匹配步骤。每个切片电路可以包括从输入数据蒸汽存储一些数量的数据字节的输入窗口。如果需要，可以填充数据的输入窗口，然后乘以多项式模数不可约伽罗瓦域多项式以生成散列索引。可以访问与散列索引相对应的存储器的存储位置，以产生一组H个切片命中信号的切片命中信号。切片命中信号可以被提供给AND逻辑阵列，其中H组切片命中信号的组合被逻辑地组合成匹配结果。

5. 发明授权

US08325069B2 System, method, and apparatus for a scalable processor architecture for a variety of string processing applications 有权
标题翻译：用于各种字符串处理应用的可扩展处理器架构的系统，方法和装置
公开(公告)号：US08325069B2
公开(公告)日：2012-12-04
申请号：US12645392
申请日：2009-12-22
申请人： Vinodh Gopal , Gilbert M. Wolrich , Christopher F. Clark , Wadji K. Feghali
发明人： Vinodh Gopal , Gilbert M. Wolrich , Christopher F. Clark , Wadji K. Feghali
IPC分类号： H03M7/34 , H03M7/38
CPC分类号： H03M7/40 , H03M7/3084 , H03M13/09
摘要： Systems, methods, and apparatus for a scalable processor architecture for variety of string processing application are described. In one such apparatus, n input first in, first out (FIFO) buffer stores an input stream. A plurality of memory banks store data from the input stream. A re-configurable controller processes the input stream. And an output FIFO buffer stores the processed input stream.
摘要翻译：描述了用于各种字符串处理应用的可扩展处理器架构的系统，方法和装置。在一个这样的装置中，n输入先进先出（FIFO）缓冲器存储输入流。多个存储器组从输入流存储数据。可重新配置的控制器处理输入流。并且输出FIFO缓冲器存储经处理的输入流。

6. 发明授权

US09632782B2 Method and apparatus to process SHA-2 secure hashing algorithm 有权
公开(公告)号：US09632782B2
公开(公告)日：2017-04-25
申请号：US13976274
申请日：2012-03-30
申请人： Kirk S. Yap , Gilbert M. Wolrich , James D. Guilford , Vinodh Gopal , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
发明人： Kirk S. Yap , Gilbert M. Wolrich , James D. Guilford , Vinodh Gopal , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
IPC分类号： G06F9/30 , G06F21/60 , H04L9/06 , H04L9/32
CPC分类号： G06F9/3016 , G06F9/30007 , G06F9/30036 , G06F9/30058 , G06F9/30098 , G06F9/30145 , G06F9/3802 , G06F9/384 , G06F12/0875 , G06F12/0897 , G06F12/1027 , G06F15/8007 , G06F21/602 , G06F2212/452 , G06F2212/68 , H04L9/0643 , H04L9/3239 , H04L2209/125
摘要： A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

7. 发明授权

US09292548B2 Digest generation 有权
标题翻译：消化一代
公开(公告)号：US09292548B2
公开(公告)日：2016-03-22
申请号：US13995236
申请日：2011-11-01
申请人： Vinodh Gopal , James D. Guilford , Schuyler Eldridge , Gilbert M. Wolrich , Erdinc Ozturk , Wajdi K. Feghali
发明人： Vinodh Gopal , James D. Guilford , Schuyler Eldridge , Gilbert M. Wolrich , Erdinc Ozturk , Wajdi K. Feghali
IPC分类号： G06F17/30
CPC分类号： G06F17/30303 , G06F17/30306 , G06F17/3033
摘要： In one embodiment, circuitry may generate digests to be combined to produce a hash value. The digests may include at least one digest and at least one other digest generated based at least in part upon at least one CRC value and at least one other CRC value. The circuitry may include cyclical redundancy check (CRC) generator circuitry to generate the at least one CRC value based at least in part upon at least one input string. The CRC generator circuitry also may generate the at least one other CRC value based least in part upon at least one other input string. The at least one other input string resulting at least in part from at least one pseudorandom operation involving, at least in part, the at least one input string. Many modifications, variations, and alternatives are possible without departing from this embodiment.
摘要翻译：在一个实施例中，电路可以生成待组合的摘要以产生散列值。摘要可以至少部分地基于至少一个CRC值和至少一个其它CRC值来生成至少一个摘要和至少一个其他摘要。电路可以包括循环冗余校验（CRC）发生器电路，以至少部分地基于至少一个输入串来生成至少一个CRC值。 CRC发生器电路还可以至少部分地基于至少一个其他输入串来生成至少一个其它CRC值。所述至少一个其他输入字符串至少部分地由至少一个涉及至少一个输入字符串的伪随机操作产生。在不脱离本实施例的情况下，可以进行许多修改，变型和替换。

8. 发明授权

US09092645B2 Efficient multiplication, exponentiation and modular reduction implementations 有权
标题翻译：有效的乘法，乘法和模块化削减实现
公开(公告)号：US09092645B2
公开(公告)日：2015-07-28
申请号：US13994782
申请日：2011-12-05
申请人： Erdinc Ozturk , Vinodh Gopal , Gilbert M. Wolrich , Wajdi K. Feghali , James D. Guilford , Deniz Karakoyunlu , Martin G. Dixon , Kahraman D. Akdemir
发明人： Erdinc Ozturk , Vinodh Gopal , Gilbert M. Wolrich , Wajdi K. Feghali , James D. Guilford , Deniz Karakoyunlu , Martin G. Dixon , Kahraman D. Akdemir
IPC分类号： H04L29/00 , G06F21/71 , H04L9/30
CPC分类号： G06F21/71 , G06F7/723 , H04L9/3006 , H04L2209/12
摘要： In one embodiment, the present disclosure provides a method that includes segmenting an n-bit exponent e into a first segment et and a number t of k-bit segments ei in response to a request to determine a modular exponentiation result R, wherein R is a modular exponentiation of a generator base g for the exponent e and a q-bit modulus m, wherein the generator base g equals two and k is based at least in part on a processor configured to determine the result R; iteratively determining a respective intermediate modular exponentiation result for each segment ei, wherein the determining comprises multiplication, exponentiation and a modular reduction of at least one of a multiplication result and an exponentiation result; and generating the modular exponentiation result R=ge mod m based on, at least in part, at least one respective intermediate modular exponentiation result.
摘要翻译：在一个实施例中，本公开提供了一种方法，其包括响应于确定模幂运算结果R的请求，将n位指数e分割成第一段et和数目t的k比特段ei，其中R是指数e的发生器基数g和q位模数m的模幂运算，其中发生器基g等于2，并且k至少部分地基于被配置为确定结果R的处理器; 迭代地确定每个段ei的相应的中间模幂运算结果，其中所述确定包括相乘结果和求幂结果中的至少一个的乘法，乘法和模块化减少; 并且至少部分地基于至少一个相应的中间模幂运算结果来产生模幂运算结果R = ge mod m。

9. 发明申请

US20150082047A1 EFFICIENT MULTIPLICATION, EXPONENTIATION AND MODULAR REDUCTION IMPLEMENTATIONS 有权
标题翻译：有效的实施，授权和模块化的减少实施
公开(公告)号：US20150082047A1
公开(公告)日：2015-03-19
申请号：US13994782
申请日：2011-12-05
申请人： Vinodh Gopal , Gilbert M. Wolrich , Wajdi K. Feghali , James D. Guilford , Deniz Karakoyunlu , Martin G. Dixon , Kahraman D. Akdemir
发明人： Erdinc Ozturk , Vinodh Gopal , Gilbert M. Wolrich , Wajdi K. Feghali , James D. Guilford , Deniz Karakoyunlu , Martin G. Dixon , Kahraman D. Akdemir
IPC分类号： G06F21/71 , H04L9/30
CPC分类号： G06F21/71 , G06F7/723 , H04L9/3006 , H04L2209/12
摘要： In one embodiment, the present disclosure provides a method that includes segmenting an n-bit exponent e into a first segment et and a number t of k-bit segments ei in response to a request to determine a modular exponentiation result R, wherein R is a modular exponentiation of a generator base g for the exponent e and a q-bit modulus m, wherein the generator base g equals two and k is based at least in part on a processor configured to determine the result R; iteratively determining a respective intermediate modular exponentiation result for each segment ei, wherein the determining comprises multiplication, exponentiation and a modular reduction of at least one of a multiplication result and an exponentiation result; and generating the modular exponentiation result R=ge mod m based on, at least in part, at least one respective intermediate modular exponentiation result.
摘要翻译：在一个实施例中，本公开提供了一种方法，其包括响应于确定模幂运算结果R的请求，将n位指数e分割成第一段et和数目t的k比特段ei，其中R是指数e的发生器基数g和q位模数m的模幂运算，其中发生器基g等于2，并且k至少部分地基于被配置为确定结果R的处理器; 迭代地确定每个段ei的相应的中间模幂运算结果，其中所述确定包括相乘结果和求幂结果中的至少一个的乘法，乘法和模块化减少; 并且至少部分地基于至少一个相应的中间模幂运算结果来产生模幂运算结果R = ge mod m。

10. 发明授权

US08953785B2 Instruction set for SKEIN256 SHA3 algorithm on a 128-bit processor 有权
标题翻译： 128位处理器上的SKEIN256 SHA3算法指令集
公开(公告)号：US08953785B2
公开(公告)日：2015-02-10
申请号：US13631143
申请日：2012-09-28
申请人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal
发明人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal
IPC分类号： H04L9/28
CPC分类号： H04L9/0643 , G06F9/30007 , G06F9/30032 , G06F9/30036
摘要： According to one embodiment, a processor includes an instruction decoder to receive a first instruction to perform first SKEIN256 MIX-PERMUTE operations, the first instruction having a first operand associated with a first storage location to store a plurality of odd words, a second operand associated with a second storage location to store a plurality of even words, and a third operand. The processor further includes a first execution unit coupled to the instruction decoder, in response to the first instruction, to perform multiple rounds of the first SKEIN256 MIX-PERMUTE operations based on the odd words and even words using a first rotate value obtained from a third storage location indicated by the third operand, and to store new odd words in the first storage location indicated by the first operand.
摘要翻译：根据一个实施例，处理器包括指令解码器，用于接收执行第一SKEIN256 MIX-PERMUTE操作的第一指令，所述第一指令具有与第一存储位置相关联的第一操作数，以存储多个奇数字，第二操作数相关联具有存储多个偶数字的第二存储位置和第三操作数。处理器还包括响应于第一指令而耦合到指令解码器的第一执行单元，使用从第三指令获得的第一旋转值，基于奇数字和偶数字进行第一SKEIN256 MIX-PERMUTE操作的多轮由第三操作数指示的存储位置，并将新的奇数字存储在由第一操作数指示的第一存储位置中。

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