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51. 发明申请

US20110303915A1 Compressively Stressed FET Device Structures 有权
标题翻译：压缩式FET器件结构
公开(公告)号：US20110303915A1
公开(公告)日：2011-12-15
申请号：US12813311
申请日：2010-06-10
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L21/823431 , H01L21/823412 , H01L21/823807 , H01L21/823821 , H01L29/66795 , H01L29/7843 , H01L29/7846 , H01L29/785
摘要： Methods for fabricating FET device structures are disclosed. The methods include receiving a fin of a Si based material, and converting a region of the fin into an oxide element. The oxide element exerts pressure onto the fin where a Fin-FET device is fabricated. The exerted pressure induces compressive stress in the device channel of the Fin-FET device. The methods also include receiving a rectangular member of a Si based material and converting a region of the member into an oxide element. The methods further include patterning the member that N fins are formed in parallel, while being abutted by the oxide element, which exerts pressure onto the N fins. Fin-FET devices are fabricated in the compressed fins, which results in compressively stressed device channels. FET devices structures are also disclosed. An FET devices structure has a Fin-FET device with a fin of a Si based material. An oxide element is abutting the fin and exerts pressure onto the fin. The Fin-FET device channel is compressively stressed due to the pressure on the fin. A further FET device structure has Fin-FET devices in a row each having fins. An oxide element extending perpendicularly to the row of fins is abutting the fins and exerts pressure onto the fins. Device channels of the Fin-FET devices are compressively stressed due to the pressure on the fins.
摘要翻译：公开了用于制造FET器件结构的方法。所述方法包括接收Si基材料的翅片，以及将鳍片的区域转换为氧化物元件。氧化物元件在制造Fin-FET器件的鳍片上施加压力。施加的压力在Fin-FET器件的器件沟道中引起压应力。所述方法还包括接收Si基材料的矩形构件并将所述构件的区域转换为氧化物元件。所述方法进一步包括在与N个翅片施加压力的同时被N型翅片平行地形成的构件图案化。 Fin-FET器件制造在压缩鳍片中，这导致压缩应力器件通道。还公开了FET器件结构。 FET器件结构具有具有Si基材料的翅片的Fin-FET器件。氧化物元件邻接翅片并对翅片施加压力。 Fin-FET器件通道由于鳍上的压力而受到压缩应力。另外的FET器件结构具有各自具有鳍片的Fin-FET器件。垂直于翅片排延伸的氧化物元件邻接散热片并对翅片施加压力。 Fin-FET器件的器件通道由于鳍片上的压力而受到压缩应力。

52. 发明授权

US09461169B2 Device and method for fabricating thin semiconductor channel and buried strain memorization layer 有权
标题翻译：用于制造薄半导体沟道和埋层应变记忆层的器件和方法
公开(公告)号：US09461169B2
公开(公告)日：2016-10-04
申请号：US12789792
申请日：2010-05-28
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L21/00 , H01L21/84 , H01L29/78 , H01L21/02 , H01L21/265
CPC分类号： H01L29/7847 , H01L21/02532 , H01L21/02664 , H01L21/26506 , H01L29/7841 , H01L29/785
摘要： A device and method for inducing stress in a semiconductor layer includes providing a substrate having a dielectric layer formed between a first semiconductor layer and a second semiconductor layer and processing the second semiconductor layer to form an amorphized material. A stress layer is deposited on the first semiconductor layer. The wafer is annealed to memorize stress in the second semiconductor layer by recrystallizing the amorphized material.
摘要翻译：用于在半导体层中诱发应力的装置和方法包括提供具有形成在第一半导体层和第二半导体层之间的介电层的衬底，并且处理第二半导体层以形成非晶化材料。应力层沉积在第一半导体层上。将晶片退火以通过使非晶化材料重结晶来在第二半导体层中记忆应力。

53. 发明授权

US08900936B2 FinFET device having reduce capacitance, access resistance, and contact resistance 有权
标题翻译： FinFET器件具有降低电容，访问电阻和接触电阻
公开(公告)号：US08900936B2
公开(公告)日：2014-12-02
申请号：US13017966
申请日：2011-01-31
申请人： Pranita Kulkarni , Ali Khakifirooz , Kangguo Cheng , Bruce B. Doris , Ghavam Shahidi , Hemanth Jagannathan
发明人： Pranita Kulkarni , Ali Khakifirooz , Kangguo Cheng , Bruce B. Doris , Ghavam Shahidi , Hemanth Jagannathan
IPC分类号： H01L29/772 , H01L21/336 , H01L29/66 , H01L29/417 , H01L29/78
CPC分类号： H01L29/66803 , H01L29/41791 , H01L29/785
摘要： A fin field-effect transistor (finFET) device having reduced capacitance, access resistance, and contact resistance is formed. A buried oxide, a fin, a gate, and first spacers are provided. The fin is doped to form extension junctions extending under the gate. Second spacers are formed on top of the extension junctions. Each second spacer is adjacent to one of the first spacers to either side of the gate. The extension junctions and the buried oxide not protected by the gate, the first spacers, and the second spacers are etched back to create voids. The voids are filled with a semiconductor material such that a top surface of the semiconductor material extending below top surfaces of the extension junctions, to form recessed source-drain regions. A silicide layer is formed on the recessed source-drain regions, the extension junctions, and the gate not protected by the first spacers and the second spacers.
摘要翻译：形成具有减小的电容，存取电阻和接触电阻的鳍状场效应晶体管（finFET）器件。提供掩埋氧化物，鳍状物，栅极和第一间隔物。该鳍被掺杂以形成在栅极下方延伸的延伸结。第二间隔件形成在延伸接头的顶部。每个第二间隔件邻近门的任一侧的第一间隔件之一。延伸结和未被栅极保护的埋入氧化物，第一间隔物和第二间隔物被回蚀刻以产生空隙。空隙填充有半导体材料，使得半导体材料的顶表面延伸到延伸接头的顶表面之下，以形成凹陷的源极 - 漏极区域。在凹陷的源极 - 漏极区域，延伸结点和不被第一间隔物和第二间隔物保护的栅极上形成硅化物层。

54. 发明授权

US08673738B2 Shallow trench isolation structures 有权
标题翻译：浅沟隔离结构
公开(公告)号：US08673738B2
公开(公告)日：2014-03-18
申请号：US13531780
申请日：2012-06-25
申请人： Bruce B. Doris , Kangguo Cheng , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni , Arvind Kumar , Shom Ponoth
发明人： Bruce B. Doris , Kangguo Cheng , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni , Arvind Kumar , Shom Ponoth
IPC分类号： H01L21/76
CPC分类号： H01L29/0649 , H01L21/76224 , H01L21/76283
摘要： Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.
摘要翻译：提供了与UTBB（超薄体和掩埋氧化物）半导体衬底一起使用的浅沟槽隔离结构，其防止发生缺陷机制，例如在浅沟槽的侧壁上的硅层的暴露部分之间形成电短路 UTBB衬底，在浅沟槽的沟槽填充材料随后被蚀刻掉并凹入UTBB衬底的上表面的情况下。

55. 发明授权

US08617956B2 Method and structure for forming high-K/metal gate extremely thin semiconductor on insulator device 有权
公开(公告)号：US08617956B2
公开(公告)日：2013-12-31
申请号：US12859414
申请日：2010-08-19
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L29/78 , H01L21/36
CPC分类号： H01L29/0847 , H01L21/28114 , H01L29/165 , H01L29/42376 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/66628 , H01L29/78 , H01L29/7848
摘要： A semiconductor device is provided that includes a gate structure present on a substrate. The gate structure includes a gate conductor with an undercut region in sidewalls of a first portion of the gate conductor, wherein a second portion of the gate conductor is present over the first portion of the gate conductor and includes a protruding portion over the undercut region. A spacer is adjacent to sidewalls of the gate structure, wherein the spacer includes an extending portion filling the undercut region. A raised source region and a raised drain region is present adjacent to the spacers. The raised source region and the raised drain region are separated from the gate conductor by the extending portion of the spacers.

56. 发明申请

US20130313643A1 Structure and Method to Modulate Threshold Voltage For High-K Metal Gate Field Effect Transistors (FETs) 有权
标题翻译：用于调制高K金属栅场效应晶体管（FET）的阈值电压的结构和方法
公开(公告)号：US20130313643A1
公开(公告)日：2013-11-28
申请号：US13478154
申请日：2012-05-23
申请人： Bruce B. Doris , Kangguo Cheng , Steven J. Holmes , Ali Khakifirooz , Pranita Kulkarni , Shom Ponoth , Raghavasimhan Sreenivasan , Stefan Schmitz
发明人： Bruce B. Doris , Kangguo Cheng , Steven J. Holmes , Ali Khakifirooz , Pranita Kulkarni , Shom Ponoth , Raghavasimhan Sreenivasan , Stefan Schmitz
IPC分类号： H01L27/12 , H01L27/092 , H01L21/8238
CPC分类号： H01L21/823835 , H01L21/823842
摘要： A method for forming an electrical device that includes forming a high-k gate dielectric layer over a semiconductor substrate that is patterned to separate a first portion of the high-k gate dielectric layer that is present on a first conductivity device region from a second portion of the high-k gate dielectric layer that is present on a second conductivity device region. A connecting gate conductor is formed on the first portion and the second portion of the high-k gate dielectric layer. The connecting gate conductor extends from the first conductivity device region over the isolation region to the second conductivity device region. One of the first conductivity device region and the second conductivity device region may then be exposed to an oxygen containing atmosphere. Exposure with the oxygen containing atmosphere modifies a threshold voltage of the semiconductor device that is exposed.
摘要翻译：一种用于形成电气装置的方法，包括在半导体衬底上形成高k栅介质层，该半导体衬底被图案化以将存在于第一导电器件区域上的高k栅介质层的第一部分与第二部分分离存在于第二导电装置区域上的高k栅介质层。连接栅极导体形成在高k栅介质层的第一部分和第二部分上。连接栅极导体从隔离区域上的第一导电器件区域延伸到第二导电器件区域。然后可以将第一导电器件区域和第二导电器件区域中的一个暴露于含氧气氛中。用含氧气氛曝光改变暴露的半导体器件的阈值电压。

57. 发明授权

US08552487B2 SOI trench DRAM structure with backside strap 有权
标题翻译：具有背面带的SOI沟槽DRAM结构
公开(公告)号：US08552487B2
公开(公告)日：2013-10-08
申请号：US13568601
申请日：2012-08-07
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L27/108
CPC分类号： H01L27/1203 , H01L27/10829 , H01L27/10867
摘要： A semiconductor structure includes a SOI substrate having a top silicon layer overlying an insulation layer, which overlies a bottom silicon layer; a capacitor disposed at least partially in the insulation layer; a device disposed at least partially on the top silicon layer, which device is coupled to a doped portion of the top silicon layer; a backside strap of first epitaxially-deposited material, at least a first portion of the backside strap underlying the doped portion, the backside strap being coupled to the doped portion of the top silicon layer at a first end of the backside strap and to the capacitor at a second end of the backside strap; and second epitaxially-deposited material that at least partially overlies the doped portion of the top silicon layer, the second epitaxially-deposited material further at least partially overlying the first portion.
摘要翻译：半导体结构包括：SOI衬底，其具有覆盖在底部硅层上的绝缘层的顶部硅层; 至少部分地设置在绝缘层中的电容器; 至少部分地设置在顶部硅层上的器件，该器件耦合到顶部硅层的掺杂部分; 第一外延沉积材料的背面带，位于掺杂部分下面的背侧带的至少第一部分，背面带在背面带的第一端处耦合到顶部硅层的掺杂部分，并且连接到电容器在背面带的第二端; 以及第二外延沉积材料，其至少部分地覆盖在顶部硅层的掺杂部分上，第二外延沉积材料进一步至少部分地覆盖在第一部分上。

58. 发明申请

US20130249002A1 Structure and method to improve etsoi mosfets with back gate 有权
标题翻译：用后门改善等离子体的结构和方法
公开(公告)号：US20130249002A1
公开(公告)日：2013-09-26
申请号：US13424447
申请日：2012-03-20
申请人： Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni
发明人： Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0653 , H01L21/76224 , H01L21/84 , H01L29/66545
摘要： A structure and method to improve ETSOI MOSFET devices. A wafer is provided including regions with at least a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer. The regions are separated by a STI which extends at least partially into the second semiconductor layer and is partially filled with a dielectric. A gate structure is formed over the first semiconductor layer and during the wet cleans involved, the STI divot erodes until it is at a level below the oxide layer. Another dielectric layer is deposited over the device and a hole is etched to reach source and drain regions. The hole is not fully landed, extending at least partially into the STI, and an insulating material is deposited in said hole.
摘要翻译：改进ETSOI MOSFET器件的结构和方法。提供晶片，其包括具有覆盖在第二半导体层上的氧化物层的至少第一半导体层的区域。这些区域由至少部分地延伸到第二半导体层中并且部分地填充有电介质的STI分开。栅极结构形成在第一半导体层之上，并且在涉及的湿清洗期间，STI纹理腐蚀直到其处于低于氧化物层的水平。在器件上沉积另一个介电层，并蚀刻一个孔以到达源极和漏极区。孔不完全落地，至少部分地延伸到STI中，并且绝缘材料沉积在所述孔中。

59. 发明授权

US08486776B2 Strained devices, methods of manufacture and design structures 有权
标题翻译：应变装置，制造方法和设计结构
公开(公告)号：US08486776B2
公开(公告)日：2013-07-16
申请号：US12886881
申请日：2010-09-21
申请人： Stephen W. Bedell , Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Katherine L. Saenger
发明人： Stephen W. Bedell , Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Katherine L. Saenger
IPC分类号： H01L21/00
CPC分类号： H01L21/84 , H01L21/823807
摘要： Strained Si and strained SiGe on insulator devices, methods of manufacture and design structures is provided. The method includes growing an SiGe layer on a silicon on insulator wafer. The method further includes patterning the SiGe layer into PFET and NFET regions such that a strain in the SiGe layer in the PFET and NFET regions is relaxed. The method further includes amorphizing by ion implantation at least a portion of an Si layer directly underneath the SiGe layer. The method further includes performing a thermal anneal to recrystallize the Si layer such that a lattice constant is matched to that of the relaxed SiGe, thereby creating a tensile strain on the NFET region. The method further includes removing the SiGe layer from the NFET region. The method further includes performing a Ge process to convert the Si layer in the PFET region into compressively strained SiGe.
摘要翻译：应变Si和应变SiGe绝缘体器件，制造方法和设计结构。该方法包括在绝缘体上硅晶片上生长SiGe层。该方法还包括将SiGe层图案化成PFET和NFET区域，使得PFET和NFET区域中的SiGe层中的应变被放宽。该方法还包括通过离子注入直接在SiGe层下面的Si层的至少一部分而非晶化。该方法还包括进行热退火以使Si层重结晶，使得晶格常数与弛豫SiGe的晶格常数相匹配，从而在NFET区域上产生拉伸应变。该方法还包括从NFET区域去除SiGe层。该方法还包括执行Ge工艺以将PFET区域中的Si层转换为压缩应变的SiGe。

60. 发明授权

US08450807B2 MOSFETs with reduced contact resistance 有权
标题翻译：具有降低的接触电阻的MOSFET
公开(公告)号：US08450807B2
公开(公告)日：2013-05-28
申请号：US12719934
申请日：2010-03-09
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L21/70
CPC分类号： H01L29/66477 , H01L21/28518 , H01L23/485 , H01L29/0847 , H01L29/165 , H01L29/41725 , H01L29/41766 , H01L29/41783 , H01L29/45 , H01L29/456 , H01L29/66628 , H01L29/66636 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for forming a field effect transistor with reduced contact resistance are provided. The reduced contact resistance is manifested by a reduced metal semiconductor alloy contact resistance and a reduced conductively filled via contact-to-metal semiconductor alloy contact resistance. The reduced contact resistance is achieved in this disclosure by texturing the surface of the transistor's source region and/or the transistor's drain region. Typically, both the source region and the drain region are textured in the present disclosure. The textured source region and/or the textured drain region have an increased area as compared to a conventional transistor that includes a flat source region and/or a flat drain region. A metal semiconductor alloy, e.g., a silicide, is formed on the textured surface of the source region and/or the textured surface of the drain region. A conductively filled via contact is formed atop the metal semiconductor alloy.
摘要翻译：提供了形成具有降低的接触电阻的场效应晶体管的方法和结构。降低的接触电阻由金属半导体合金接触电阻降低和导电填充通孔接触 - 金属半导体合金接触电阻表现出来。在本公开内容中通过纹理化晶体管的源极区域和/或晶体管的漏极区域的表面来实现降低的接触电阻。通常，在本公开内容中，源极区域和漏极区域都被纹理化。与包括平坦源极区域和/或平坦漏极区域的常规晶体管相比，纹理化源极区域和/或织构化漏极区域具有增加的面积。在源极区域的纹理表面和/或漏极区域的纹理化表面上形成金属半导体合金，例如硅化物。在金属半导体合金的顶部形成导电填充的通孔接触。

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