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51. 发明授权

US06346825B1 Block RAM with configurable data width and parity for use in a field programmable gate array 有权
标题翻译：块RAM具有可配置的数据宽度和奇偶校验，用于现场可编程门阵列
公开(公告)号：US06346825B1
公开(公告)日：2002-02-12
申请号：US09680205
申请日：2000-10-06
申请人： Raymond C. Pang , Steven P. Young , Trevor J. Bauer
发明人： Raymond C. Pang , Steven P. Young , Trevor J. Bauer
IPC分类号： H03K19177
CPC分类号： H03K19/1776
摘要： A dedicated block random access memory (RAM) is provided for a programmable logic device (PLD), such as a field programmable gate array (FPGA). The block RAM includes a memory cell array and control logic that is configurable to select one of a plurality of parity or non-parity modes for accessing the memory cell array. In one embodiment, the non-parity modes include a 1×16384 mode, a 2×8192 mode, and a 4×4096 mode, while the parity modes include a 9×2048 mode, a 18×1024 mode and an 36×512 mode. The control logic selects the parity/non-parity mode in response to configuration bits stored in corresponding configuration memory cells of the PLD. The configuration bits are programmed during configuration of the PLD. In one variation, the control logic selects the parity/non-parity mode in response to user signals. In a particular embodiment, the block RAM is a dual-port memory having a first port and a second port. In this embodiment, the first and second ports can be independently configured to have different (or the same) parity or non-parity modes.
摘要翻译：为诸如现场可编程门阵列（FPGA）的可编程逻辑器件（PLD）提供专用块随机存取存储器（RAM）。块RAM包括存储单元阵列和控制逻辑，可配置为选择用于访问存储单元阵列的多个奇偶校验或非奇偶校验模式之一。在一个实施例中，非奇偶校验模式包括1x16384模式，2x8192模式和4×4096模式，而奇偶校验模式包括9×2048模式，18×1024模式和36×512模式。响应于存储在PLD的相应配置存储器单元中的配置位，控制逻辑选择奇偶校验/非奇偶校验模式。在配置PLD期间对配置位进行编程。在一个变化中，控制逻辑响应于用户信号选择奇偶校验/非奇偶校验模式。在特定实施例中，块RAM是具有第一端口和第二端口的双端口存储器。在该实施例中，第一和第二端口可以被独立地配置为具有不同的（或相同的）奇偶校验或非奇偶校验模式。

52. 发明授权

US06288568B1 FPGA architecture with deep look-up table RAMs 有权
标题翻译：具有深度查找表RAM的FPGA架构
公开(公告)号：US06288568B1
公开(公告)日：2001-09-11
申请号：US09574115
申请日：2000-05-19
申请人： Trevor J. Bauer , Steven P. Young
发明人： Trevor J. Bauer , Steven P. Young
IPC分类号： H03K19177
CPC分类号： H03K19/1736 , G11C19/00 , H03K19/17736 , H03K19/1776
摘要： A configurable logic block (CLB) having a plurality of identical configurable logic element CLE) slices is provided. Each CLE slice includes a plurality of function generators (lookup tables) that can be configured to form a random access memory (RAM). The width and depth of the RAM are selectable by controlling the routing of signals within the CLE slices. A hierarchy of wide function multiplexers (F5, F6, and F7 multiplexers) are provided to selectively route read data values from the lookup tables. Another set of multiplexers is used to selectively route write data values to the lookup tables. These multiplexers can be configured to provide a single write data value to all of the lookup tables to form a deep RAM. Alternatively, these multiplexers can be configured to provide one write data value to half of the lookup tables, and another write data value to the other half of the lookup tables. This pattern repeats down to the level where these multiplexers can be configured to provide a different write data value to each of the lookup tables. A write control circuit is also provided in each CLE slice to provide write enable signals to the lookup tables in a manner consistent with the selected RAM size.
摘要翻译：提供具有多个相同的可配置逻辑元件CLE）片的可配置逻辑块（CLB）。每个CLE切片包括可被配置成形成随机存取存储器（RAM）的多个功能发生器（查找表）。通过控制CLE切片内信号的路由可以选择RAM的宽度和深度。提供了多功能多路复用器（F5，F6和F7多路复用器）的层次结构，用于选择性地从查找表路由读取数据值。另一组多路复用器用于选择性地将写入数据值路由到查找表。这些多路复用器可以被配置为向所有查找表提供单个写数据值以形成深RAM。或者，这些多路复用器可以被配置为向查找表的一半提供一个写入数据值，并将另一个写入数据值提供给查找表的另一半。该模式重复到这些复用器可被配置为向每个查找表提供不同的写入数据值的级别。在每个CLE片中还提供写入控制电路，以与所选择的RAM大小一致的方式向查找表提供写使能信号。

53. 发明授权

US06262597B1 FIFO in FPGA having logic elements that include cascadable shift registers 有权
标题翻译： FPGA中的FIFO具有包括可级联移位寄存器的逻辑元件
公开(公告)号：US06262597B1
公开(公告)日：2001-07-17
申请号：US09624515
申请日：2000-07-24
申请人： Trevor J. Bauer , Bruce A. Newgard , William E. Allaire , Steven P. Young
发明人： Trevor J. Bauer , Bruce A. Newgard , William E. Allaire , Steven P. Young
IPC分类号： H03K19177
CPC分类号： G11C19/00 , H03K19/1736 , H03K19/17728 , H03K19/17736 , H03K19/17768
摘要： A set of logic elements can be configured as a cascadable shift register. In one embodiment, a logic element for an FPGA can be configured as any one of a random access memory, a cascadable shift register and a lookup table. The data-in path to the shift register includes a cascade multiplexer for optionally forming large shift registers using multiple logic elements. Each logic element includes a plurality of memory cells which are interconnected such that the data output of each memory cell can serve as the input to the next memory cell, causing the logic element to function as a shift register. The cascade multiplexer allows the last bit of one logic element to be connected to the first bit of the next logic element, bypassing any decode logic of the lookup table. Variable tap shift registers of arbitrary length can be created by cascading lookup tables of plural logic elements in series. The lookup table decode logic plus additional multiplexers can be used to select any memory cell (not necessarily the last memory cell) of the shift register.
摘要翻译：一组逻辑元件可以配置为可级联移位寄存器。在一个实施例中，用于FPGA的逻辑元件可以被配置为随机存取存储器，级联移位寄存器和查找表中的任何一个。到移位寄存器的数据输入路径包括级联多路复用器，用于可选地使用多个逻辑元件形成大移位寄存器。每个逻辑元件包括互连的多个存储器单元，使得每个存储器单元的数据输出可以用作到下一个存储器单元的输入，使逻辑元件用作移位寄存器。级联多路复用器允许一个逻辑元件的最后一位连接到下一个逻辑元件的第一位，绕过查找表的任何解码逻辑。可以通过串联多个逻辑元件的查询表来创建任意长度的可变抽头移位寄存器。查找表解码逻辑加上附加多路复用器可用于选择移位寄存器的任何存储单元（不一定是最后一个存储单元）。

54. 发明授权

US06204690B1 FPGA architecture with offset interconnect lines 有权
标题翻译：具有偏移互连线路的FPGA架构
公开(公告)号：US06204690B1
公开(公告)日：2001-03-20
申请号：US09574741
申请日：2000-05-18
申请人： Steven P. Young , Kamal Chaudhary , Trevor J. Bauer
发明人： Steven P. Young , Kamal Chaudhary , Trevor J. Bauer
IPC分类号： H01L2500
CPC分类号： H03K19/1737 , H03K19/17704 , H03K19/17736 , H03K19/17796
摘要： The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. A combination of single-length lines connecting to adjacent tiles and intermediate-length lines connecting to tiles several tiles away creates an interconnect hierarchy which allows any logic block to be connected to any other logic block, yet also allows for fast paths to both adjacent tiles and tiles some distance away. Longer interconnect lines may be included as a third level of hierarchy to permit interconnection of widely separated tiles. In a preferred embodiment, from a given tile an intermediate-length line connects to the tile three tiles away, then continues and connects to the tile six tiles away. In this embodiment, the intermediate-length line does not connect to the intervening tiles one, two, four, and five tiles away.
摘要翻译：本发明提供了优选地包括在相同瓦片阵列中的FPGA互连结构。连接到相邻瓦片的单条线和连接到瓦片几个瓦片的中间线的组合创建互连层级，其允许任何逻辑块连接到任何其他逻辑块，但是也允许到相邻瓦片的快速路径和瓷砖有一段距离。可以将更长的互连线包括为第三层次以允许广泛分隔的瓷砖的互连。在优选实施例中，从给定的瓦片中，中间线连接到瓦片三瓦片之外，然后继续并连接到瓦片六瓦片。在该实施例中，中间长度线不连接到中间瓦片一个，两个，四个和五个瓦片。

55. 发明授权

US06204689B1 Input/output interconnect circuit for FPGAs 有权
标题翻译： FPGA的输入/输出互连电路
公开(公告)号：US06204689B1
公开(公告)日：2001-03-20
申请号：US09321513
申请日：1999-05-27
申请人： Andrew K. Percey , Trevor J. Bauer , Steven P. Young
发明人： Andrew K. Percey , Trevor J. Bauer , Steven P. Young
IPC分类号： H01L2500
CPC分类号： H03K19/1737 , H03K19/17704 , H03K19/17736 , H03K19/17796
摘要： An input/output interconnect (IOI) circuit is provided for coupling input/output (IO) blocks to an array of configurable logic tiles in a field programmable gate array (FPGA). Each of the tiles includes a configurable logic block and a programmable interconnect structure that includes a plurality of intermediate-length buses. The intermediate-length buses are staggered, such that only a subset of the intermediate-length buses routed by a logic block is connected to the logic block. The IOI circuit includes routing circuits at the perimeter of the array for terminating the intermediate-length buses. In one embodiment, the routing circuits connect various ends of unidirectional intermediate-length buses in a U-turn configuration, thereby making use of all of the intermediate-length buses, and maintaining a regular pattern of intermediate-length buses in the tiles. In another embodiment, various ends of bi-directional intermediate-length buses are terminated to long lines through programmable interconnection points (PIPs). In another embodiment, PIPs are provided to enable horizontal long lines to be connected to horizontal intermediate-length buses, which in turn, can be connected to vertical long lines, thereby providing a low-skew, high fanout routing network.
摘要翻译：提供输入/输出互连（IOI）电路用于将输入/输出（IO）块耦合到现场可编程门阵列（FPGA）中的可配置逻辑块阵列。每个瓦片包括可配置逻辑块和包括多个中长度总线的可编程互连结构。中间长度总线是交错的，使得只有由逻辑块路由的中间长度总线的子集连接到逻辑块。 IOI电路包括用于终止中长度总线的阵列周边的路由电路。在一个实施例中，路由电路将单向中长度总线的各端连接在U形结构中，从而利用所有的中长度总线，并在瓦片中保持中长度总线的规则图案。在另一个实施例中，双向中间长度总线的各个端点通过可编程互连点（PIP）终止于长行。在另一个实施例中，提供PIP以使得水平长线能够连接到水平中间长度总线，其又可以连接到垂直长线，从而提供低偏移，高扇出路由网络。

56. 发明授权

US06201410B1 Wide logic gate implemented in an FPGA configurable logic element 有权
标题翻译：宽逻辑门在FPGA可配置逻辑元件中实现
公开(公告)号：US06201410B1
公开(公告)日：2001-03-13
申请号：US09374470
申请日：1999-08-13
申请人： Bernard J. New , Steven P. Young , Shekhar Bapat , Kamal Chaudhary , Trevor J. Bauer , Roman Iwanczuk
发明人： Bernard J. New , Steven P. Young , Shekhar Bapat , Kamal Chaudhary , Trevor J. Bauer , Roman Iwanczuk
IPC分类号： H01L2500
CPC分类号： H03K19/17736 , H03K19/1737 , H03K19/17704 , H03K19/17728 , H03K19/1778
摘要： The invention allows the implementation of common wide logic functions using only two function generators of a field programmable gate array. One embodiment of the invention provides a structure for implementing a wide AND-gate in an FPGA configurable logic element (CLE) or portion thereof that includes no more than two function generators. First and second function generators are configured as AND-gates, the output signals (first and second AND signals) being combined in a 2-to-1 multiplexer controlled by the first AND signal, “0” selecting the first AND signal and “1” selecting the second AND signal. Therefore, a wide AND-gate is provided having a number of input signals equal to the total number of input signals for the two function generators. In another embodiment, a wide OR-gate is provided by configuring the function generators as OR-gates and controlling the multiplexer using the second OR signal.
摘要翻译：本发明允许仅使用现场可编程门阵列的两个函数发生器实现普通的宽逻辑功能。本发明的一个实施例提供了一种用于在FPGA可配置逻辑元件（CLE）或其部分中实现宽的与门的结构，其包括不超过两个功能发生器。第一和第二功能发生器被配置为与门，输出信号（第一和第二AND信号）被组合在由第一AND信号控制的2对1多路复用器中，选择第一AND信号为“0”和“1” “选择第二个AND信号。因此，提供了具有等于两个功能发生器的输入信号的总数的多个输入信号的宽AND门。在另一个实施例中，通过将功能发生器配置为OR门并使用第二OR信号来控制多路复用器来提供宽的或门。

57. 发明授权

US6051992A Configurable logic element with ability to evaluate five and six input functions 有权
标题翻译：可配置逻辑元件，具有评估五个和六个输入功能的能力
公开(公告)号：US6051992A
公开(公告)日：2000-04-18
申请号：US283472
申请日：1999-04-01
申请人： Steven P. Young , Shekhar Bapat , Kamal Chaudhary , Trevor J. Bauer , Roman Iwanczuk
发明人： Steven P. Young , Shekhar Bapat , Kamal Chaudhary , Trevor J. Bauer , Roman Iwanczuk
IPC分类号： H01L25/00 , H03K19/173 , H03K19/177
CPC分类号： H03K19/17728 , H03K19/1737 , H03K19/17704
摘要： The invention provides a Configurable Logic Element (CLE) preferably included in each of an array of identical tiles. A CLE according to the invention has four function generators. The outputs of two function generators are combined with a fifth independent input in a five-input-function multiplexer or function generator to produce an output that can be any function of five inputs, or some functions of up to nine inputs. The outputs of the other two function generators are similarly combined. The outputs of the two five-input-function multiplexers or function generators are then combined with a sixth independent input in a six-input-function multiplexer or function generator. The six-input-function multiplexer or function generator therefore produces an output that can be any function of up to six inputs. Some functions of up to nineteen inputs can also be generated in a single CLE.
摘要翻译：本发明提供了优选地包括在相同瓦片的阵列中的每一个中的可配置逻辑元件（CLE）。根据本发明的CLE具有四个功能发生器。两个功能发生器的输出与五输入功能多路复用器或函数发生器中的第五个独立输入组合，以产生可以是五个输入或多达九个输入的一些功能的输出。其他两个功能发生器的输出类似地组合。然后，两个五输入功能多路复用器或函数发生器的输出与六输入函数多路复用器或函数发生器中的第六个独立输入相组合。因此，六输入功能多路复用器或函数发生器产生的输出可以是多达六个输入的任何功能。也可以在单个CLE中生成多达十九个输入的某些功能。

58. 发明授权

US06232845B1 Circuit for measuring signal delays in synchronous memory elements 有权
标题翻译：用于测量同步存储器元件中的信号延迟的电路
公开(公告)号：US06232845B1
公开(公告)日：2001-05-15
申请号：US09360350
申请日：1999-07-22
申请人： Christopher H. Kingsley , Trevor J. Bauer , Robert W. Wells , Robert D. Patrie
发明人： Christopher H. Kingsley , Trevor J. Bauer , Robert W. Wells , Robert D. Patrie
IPC分类号： G11C2900
CPC分类号： G11C29/028 , G01R27/04 , G01R31/2853 , G01R31/2882 , G01R31/3016 , G01R31/31725 , G01R31/318516 , G01R31/31937 , G11C29/50012
摘要： A circuit measures a signal propagation delay through a series of memory elements. In one embodiment the memory elements are configured in series so that together they form a delay circuit. In another embodiment the memory elements are configured in a loop to form a ring oscillator. Each memory element propagates a signal to a subsequent memory element so that the time the signal takes to traverse all of the memory elements is proportional to the average delay induced by the individual elements. This proportionality provides an effective means for measuring the delays of those components. Various embodiments of the invention measure the speeds at which memory elements can be preset, cleared, written to, read from, or clock enabled.
摘要翻译：电路通过一系列存储器元件测量信号传播延迟。在一个实施例中，存储器元件被串联构造，使得它们一起形成延迟电路。在另一个实施例中，存储器元件被配置成环路以形成环形振荡器。每个存储器元件将信号传播到后续存储器元件，使得信号经过所有存储器元件的时间与由各个元件引起的平均延迟成比例。这种相称性为测量这些部件的延迟提供了有效手段。本发明的各种实施例测量存储器元件可被预置，清除，写入，读取或启用时钟的速度。

59. 发明授权

US06956399B1 High-speed lookup table circuits and methods for programmable logic devices 有权
标题翻译：用于可编程逻辑器件的高速查找表电路和方法
公开(公告)号：US06956399B1
公开(公告)日：2005-10-18
申请号：US10772859
申请日：2004-02-05
申请人： Trevor J. Bauer
发明人： Trevor J. Bauer
IPC分类号： H03K19/177
CPC分类号： H03K19/17748 , H03K19/17728 , H03K19/1776
摘要： A lookup table (LUT) circuit comprises a multiplexer circuit having two modes. In a first mode, the multiplexer circuit functions as a standard multiplexer. In a second mode, the multiplexer circuit selects two or more stored values, where the two or more stored values have the same logical value. Thus, in the second mode the delay through the multiplexer circuit is reduced. In a PLD embodiment, two select terminals of the multiplexer are coupled to two different signal lines. When both signal lines are used, the multiplexer circuit is placed into the first mode. When only one of the signal lines is used, the multiplexer circuit is placed into the second mode, a value on the unused signal line is ignored, and two stored values are provided to the output terminal. Thus, the multiplexer circuit has a reduced path delay when one of the two signal lines is unused.
摘要翻译：查找表（LUT）电路包括具有两种模式的多路复用器电路。在第一模式中，多路复用器电路用作标准多路复用器。在第二模式中，多路复用器电路选择两个或多个存储的值，其中两个或多个存储的值具有相同的逻辑值。因此，在第二模式中，减少了通过多路复用器电路的延迟。在PLD实施例中，多路复用器的两个选择端耦合到两个不同的信号线。当使用两条信号线时，多路复用器电路被置于第一模式。当仅使用一条信号线时，将多路复用器电路置于第二模式，忽略未使用信号线上的值，并将两个存储值提供给输出端。因此，当两个信号线中的一个未使用时，多路复用器电路具有减小的路径延迟。

60. 发明授权

US06907595B2 Partial reconfiguration of a programmable logic device using an on-chip processor 有权
标题翻译：使用片上处理器对可编程逻辑器件进行部分重新配置
公开(公告)号：US06907595B2
公开(公告)日：2005-06-14
申请号：US10319051
申请日：2002-12-13
申请人： Derek R. Curd , Punit S. Kalra , Richard J. LeBlanc , Vincent P. Eck , Stephen W. Trynosky , Jeffrey V. Lindholm , Trevor J. Bauer
发明人： Derek R. Curd , Punit S. Kalra , Richard J. LeBlanc , Vincent P. Eck , Stephen W. Trynosky , Jeffrey V. Lindholm , Trevor J. Bauer
IPC分类号： G06F15/78 , G06F17/50
CPC分类号： G06F15/7867
摘要： A programmable logic device, such as a field programmable gate array, is partially reconfigured using a read-modify-write scheme that is controlled by a processor. The partial reconfiguration includes (1) loading a base set of configuration data values into a configuration memory array of the programmable logic device, thereby configuring the programmable logic device; (2) reading a first frame of configuration data values from the configuration memory array; (3) modifying a subset of the configuration data values in the first frame of configuration data values, thereby creating a first modified frame of configuration data values; and (4) overwriting the first frame of configuration data values in the configuration memory array with the first modified frame of configuration data values, thereby partially reconfiguring the programmable logic device. The steps of reading, modifying and overwriting are performed under the control of a processor.
摘要翻译：使用由处理器控制的读 - 修改 - 写入方案来部分地重新配置可编程逻辑器件，例如现场可编程门阵列。部分重新配置包括（1）将一组配置数据值加载到可编程逻辑器件的配置存储器阵列中，从而配置可编程逻辑器件; （2）从配置存储器阵列读取配置数据值的第一帧; （3）修改配置数据值的第一帧中的配置数据值的子集，由此创建配置数据值的第一修改帧; 和（4）用配置数据值的第一修改帧重写配置存储器阵列中的配置数据值的第一帧，从而部分地重新配置可编程逻辑器件。读取，修改和重写的步骤在处理器的控制下执行。

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