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51. 发明授权

US5452436A System for connecting plurality of electronic units to data and clock buses wherein transmitting and receiving data in synchronization with transmitting and receiving clock signals 失效
标题翻译：用于将多个电子单元连接到与发送和接收时钟信号同步地发送和接收数据的数据和时钟总线的系统
公开(公告)号：US5452436A
公开(公告)日：1995-09-19
申请号：US367927
申请日：1995-01-03
申请人： Kiyokazu Arai , Akira Yamagiwa , Toshihiro Okabe
发明人： Kiyokazu Arai , Akira Yamagiwa , Toshihiro Okabe
IPC分类号： G06F13/42 , G06F1/10 , G06F13/00 , H04L7/00 , H04L12/40 , G06F1/04
CPC分类号： G06F1/10 , H04L7/0008
摘要： A data processing apparatus, including a number of electronic circuit units, in which high-speed data can be transmitted among the electronic circuit units. When data is transmitted from one electronic circuit unit to another electronic circuit unit, a clock signal to fetch the data in the sink side electronic circuit unit is transmitted from the source side electronic circuit unit via a clock signal line having the same signal propagation delay characteristics as those of the data signal line.
摘要翻译：一种数据处理装置，包括多个电子电路单元，其中可以在电子电路单元之间传输高速数据。当从一个电子电路单元发送数据到另一个电子电路单元时，通过具有相同信号传播延迟特性的时钟信号线从源极侧电子单元发送用于取出接收侧电子电路单元中的数据的时钟信号作为数据信号线的那些。

52. 发明授权

US5365402A Cooling apparatus of electronic device 失效
标题翻译：电子设备冷却装置
公开(公告)号：US5365402A
公开(公告)日：1994-11-15
申请号：US800268
申请日：1991-11-29
申请人： Toshio Hatada , Shigeo Ohashi , Tadakatsu Nakajima , Heikichi Kuwahara , Hitoshi Matsushima , Motohiro Sato , Hiroshi Inouye , Takao Ohba , Akira Yamagiwa , Kanji Otsuka , Yuuji Shirai
发明人： Toshio Hatada , Shigeo Ohashi , Tadakatsu Nakajima , Heikichi Kuwahara , Hitoshi Matsushima , Motohiro Sato , Hiroshi Inouye , Takao Ohba , Akira Yamagiwa , Kanji Otsuka , Yuuji Shirai
IPC分类号： H01L23/36 , H01L23/367 , H01L23/40 , H01L23/433 , H05K7/20
CPC分类号： H01L23/433 , H01L23/3677 , H01L23/4006 , H01L2023/405 , H01L2224/32188 , H01L2224/451 , H01L2224/48091 , H01L2224/48227 , H01L2224/49109 , H01L2224/73265 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2924/00014 , H01L2924/15312 , H01L2924/1532 , H01L2924/16195
摘要： A cooling apparatus for an electronic device of high calorific density including an elastomer interposed between a semiconductor chip and a heat sink so as to connect them thermally. The elastomer may also be in close contact with a large number of semiconductor chips having various configurations which are mounted on a board, so that the elastomer is thermally connected with them, whereby the elastomer absorbs thermal deformations.
摘要翻译：一种用于高热密度的电子装置的冷却装置，包括插入在半导体芯片和散热片之间的弹性体，以便将它们热连接。弹性体还可以与安装在板上的具有各种构造的大量半导体芯片紧密接触，使得弹性体与它们热连接，由此弹性体吸收热变形。

53. 发明授权

US5361188A Cooling apparatus of electronic equipment 失效
标题翻译：电子设备冷却装置
公开(公告)号：US5361188A
公开(公告)日：1994-11-01
申请号：US115669
申请日：1993-09-02
申请人： Yoshihiro Kondou , Hitoshi Matsushima , Toshio Hatada , Hiroshi Inouye , Toshihiro Komatsu , Takao Ohba , Akira Yamagiwa
发明人： Yoshihiro Kondou , Hitoshi Matsushima , Toshio Hatada , Hiroshi Inouye , Toshihiro Komatsu , Takao Ohba , Akira Yamagiwa
IPC分类号： H05K7/20 , H01L23/467
CPC分类号： H01L23/467 , H05K7/20563 , H01L2224/32 , H01L2224/73253 , Y10S165/908
摘要： In a cooling apparatus of an electronic equipment, a plurality each of integrated circuit devices and large-scale integrated circuit devices are mounted onto a plurality of substrates, respectively, and a cooling fan supplies cooling air from outside to each of these integrated circuit devices. A duct having a comb-tooth shape suitable for encompassing each substrate and defining flow paths along the substrates introduces the cooling air supplied by the cooling fan to each of the integrated circuit devices. The duct includes a plurality of small holes disposed at positions corresponding to the positions of the integrated circuit devices on the substrates and having open areas corresponding to the heating values of the integrated circuit devices. The small holes flow the cooling air supplied by the cooling fan as jet streams to the integrated circuit devices. This jet stream cooling improves cooling performance and can make uniform the temperature distribution of the integrated circuit devices.
摘要翻译：在电子设备的冷却装置中，分别将多个集成电路装置和大型集成电路装置安装在多个基板上，并且冷却风扇从外部向这些集成电路装置中的每一个提供冷却空气。具有适于包围每个基板并且沿着基板限定流动路径的梳齿形状的管道将由冷却风扇供应的冷却空气引入到每个集成电路装置。导管包括多个小孔，其设置在与基板上的集成电路器件的位置对应的位置处，并且具有与集成电路器件的发热值对应的开放区域。这些小孔将作为喷射流的冷却风扇供给的冷却空气流向集成电路装置。这种喷射流冷却改善了冷却性能，并且可以使集成电路器件的温度分布均匀。

54. 发明授权

US5315482A Semiconductor apparatus of module installing type 失效
标题翻译：模块安装型半导体装置
公开(公告)号：US5315482A
公开(公告)日：1994-05-24
申请号：US961394
申请日：1992-10-15
申请人： Akira Tanaka , Hiroichi Shinohara , Kazuji Yamada , Takao Ohba , Akira Yamagiwa , Hitoshi Yoshidome , Yuji Shirai , Toshio Hatada , Munehisa Kishimoto , Michiharu Honda
发明人： Akira Tanaka , Hiroichi Shinohara , Kazuji Yamada , Takao Ohba , Akira Yamagiwa , Hitoshi Yoshidome , Yuji Shirai , Toshio Hatada , Munehisa Kishimoto , Michiharu Honda
IPC分类号： H01L23/36 , H01L23/367 , H01L25/10 , H05K1/02 , H05K1/14 , H05K1/18 , H05K3/00 , H05K3/36 , H05K7/20
CPC分类号： H05K1/021 , H01L23/367 , H01L25/105 , H01L2225/107 , H01L2225/1094 , H01L2924/0002 , H05K1/141 , H05K1/182 , H05K2203/049 , H05K3/0061 , H05K3/366
摘要： A semiconductor apparatus comprises a heat diffusing plate and a surface installing printed board. A semiconductor device of a high heat generation is installed on the heat diffusing plate. A surface installing package and chip parts are installed on both surfaces of the printed board. A through hole is formed at the center of the printed board so that the semiconductor device is located at the center. The heat diffusing plate on which the semiconductor device has been installed and the surface installing printed board are connected and integrated.
摘要翻译：半导体装置包括热扩散板和表面安装印刷板。在散热板上安装有高发热的半导体装置。表面安装封装和芯片部件安装在印刷电路板的两个表面上。在印刷电路板的中心形成通孔，使得半导体器件位于中心。已经安装了半导体器件的散热板和表面安装印刷板连接并整合。

55. 发明授权

US5145800A Method of wiring for power supply to large-scale integrated circuit 失效
标题翻译：大规模集成电路供电方式
公开(公告)号：US5145800A
公开(公告)日：1992-09-08
申请号：US731616
申请日：1991-07-17
申请人： Kiyokazu Arai , Masatoshi Kawashima , Akira Yamagiwa , Toshihiro Okabe
发明人： Kiyokazu Arai , Masatoshi Kawashima , Akira Yamagiwa , Toshihiro Okabe
IPC分类号： H01L21/822 , H01L21/82 , H01L23/528 , H01L27/04 , H01L27/118
CPC分类号： H01L23/5286 , H01L2924/0002
摘要： A method for wiring a power supply for a large-scale integrated circuit. The power supply wires define a power supply grid surrounding lattice openings with fixed longitudinal and transverse lattice dimensions. The wire width is determined based on the integrated circuit chip size, the number of function circuits to be on the integrated circuit, the electrical power requirements of the function circuits, and the fixed longitudinal and transverse lattice dimensions. Longitudinal and transverse locations of the power supply wires chips are determined based on the determined wire width and the fixed longitudinal and transverse dimensions of the lattice openings. Alternatively, the wire width may be fixed and the dimensions of the lattice openings determined based on the integrated circuit chip size, the number of function circuits, the electrical power requirements of the function circuits and that wire width. When the electrical power requirement of a function circuit is significantly larger than that of another function circuit, the wire width may be increased in the vicinity of the one function circuit. When the function circuits include a large-scale function block, a wire width around a region of the integrated circuit chip in which the large-scale block is to be disposed may be selected which results in a wire area equal to the wire area of the power supply wire that would occupy the particular region for usual function circuits.
摘要翻译：一种用于大规模集成电路的电源接线的方法。电源线定义了围绕具有固定的纵向和横向晶格尺寸的格栅开口的电源网格。线宽是基于集成电路芯片尺寸，集成电路上的功能电路的数量，功能电路的电功率要求以及固定的纵向和横向晶格尺寸来确定的。电源线芯片的纵向和横向位置基于确定的线宽度和格子孔的固定纵向和横向尺寸来确定。或者，线宽可以是固定的，并且基于集成电路芯片尺寸，功能电路的数量，功能电路的电功率要求和线宽度确定的格子孔的尺寸。当功能电路的电力需求明显大于另一个功能电路的电力需求时，可以在一个功能电路附近增加导线宽度。当功能电路包括大规模功能块时，可以选择其中要布置大规模块的集成电路芯片的区域周围的导线宽度，这导致导线面积等于将占用特定区域用于通常功能电路的电源线。

56. 发明授权

US5087829A High speed clock distribution system 失效
标题翻译：高速时钟分配系统
公开(公告)号：US5087829A
公开(公告)日：1992-02-11
申请号：US443503
申请日：1989-12-01
申请人： Kenichi Ishibashi , Takehisa Hayashi , Toshio Doi , Mitsuo Asai , Noboru Masuda , Akira Yamagiwa , Toshihiro Okabe
发明人： Kenichi Ishibashi , Takehisa Hayashi , Toshio Doi , Mitsuo Asai , Noboru Masuda , Akira Yamagiwa , Toshihiro Okabe
IPC分类号： H03K5/15
CPC分类号： H03K5/15
摘要： This invention discloses a clock distribution system which distributes a first clock signal as a reference clock as the reference for the phase and frequency to each processing unit (e.g. LSI) and generates a multi-phase second clock signal to be used in each processing unit by a delay circuit group whose delay time is adjusted. The clock distribution system comprises a clock generation block for generating a one-phase reference clock; a first control loop for comparing the phase of the reference clock with the phase of a feedback signal and adjusting the phase of the reference clock so that their phases are in agreement; and a second control loop including a delay circuit group consisting of a plurality of variable delay circuits to which the reference clock phase-adjusted by the first control loop is inputted and which are connected in series, and means for generating a multi-phase clock signal by use of the output signal of each of the plurality of variable delay circuits and the phase-adjusted referencde clock, controlling the delay time of the plurality of variable delay circuits so as to accomplish a predetermined relation with the period of the phase-adjusted reference clock and applying one of the multi-phase clock signals as the feedback signal described above to the first control loop.
摘要翻译：本发明公开了一种时钟分配系统，其将作为基准时钟的第一时钟信号作为相位和频率的参考分配给每个处理单元（例如，LSI），并且通过以下方式生成要在每个处理单元中使用的多相第二时钟信号：延迟时间被调整的延迟电路组。时钟分配系统包括用于产生单相参考时钟的时钟产生模块; 第一控制环路，用于将参考时钟的相位与反馈信号的相位进行比较，并且调整参考时钟的相位，使得它们的相位一致; 以及包括由多个可变延迟电路组成的延迟电路组的第二控制回路，所述多个可变延迟电路输入由第一控制回路相位调整的参考时钟并串联连接的参考时钟，以及用于产生多相时钟信号的装置通过使用多个可变延迟电路中的每一个的输出信号和相位调整参考时钟，控制多个可变延迟电路的延迟时间，以便与相位调整参考的周期完成预定的关系时钟，并将多相时钟信号中的一个作为上述反馈信号施加到第一控制回路。

57. 发明授权

US06737741B2 Process for mounting electronic device and semiconductor device 失效
标题翻译：电子器件和半导体器件的安装工艺
公开(公告)号：US06737741B2
公开(公告)日：2004-05-18
申请号：US10224504
申请日：2002-08-21
申请人： Satoshi Imasu , Ikuo Yoshida , Tetsuya Hayashida , Akira Yamagiwa , Shinobu Takeura
发明人： Satoshi Imasu , Ikuo Yoshida , Tetsuya Hayashida , Akira Yamagiwa , Shinobu Takeura
IPC分类号： H01L2314
CPC分类号： H01L23/13 , H01L21/563 , H01L23/24 , H01L23/49811 , H01L23/5383 , H01L24/29 , H01L24/32 , H01L25/105 , H01L2224/0401 , H01L2224/05567 , H01L2224/05571 , H01L2224/05572 , H01L2224/1134 , H01L2224/13144 , H01L2224/16225 , H01L2224/16237 , H01L2224/29111 , H01L2224/2919 , H01L2224/32225 , H01L2224/45 , H01L2224/45144 , H01L2224/48 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48599 , H01L2224/49 , H01L2224/49109 , H01L2224/73103 , H01L2224/73203 , H01L2224/73204 , H01L2224/73265 , H01L2224/81191 , H01L2224/83101 , H01L2224/83191 , H01L2224/83192 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/15153 , H01L2924/1517 , H01L2924/15174 , H01L2924/15311 , H01L2924/1579 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/351 , H05K1/0271 , H05K1/111 , H05K1/112 , H05K3/4602 , H05K2201/0133 , H05K2201/091 , H05K2201/09472 , H05K2201/0949 , H05K2201/09536 , H05K2201/0959 , H05K2201/10674 , H05K2203/1581 , Y02P70/611 , H01L2924/00014 , H01L2924/00012 , H01L2924/00 , H01L2224/13111 , H01L2224/05552
摘要： An electronic device comprising a semiconductor chip which is fixed to the mounting face of a wiring board through an adhesive and in which external terminals are electrically connected with electrode pads of the wiring board through bump electrodes. Recesses are formed in the electrode pads, and in the recesses the electrode pads and the bump electrodes are connected. The electrode pads are formed over the surface of a soft layer, and the recesses are formed by elastic deformation of the electrode pads and the soft layer.
摘要翻译：一种电子设备，包括通过粘合剂固定到布线板的安装面的半导体芯片，其中外部端子通过凸块电极与布线板的电极焊盘电连接。在电极焊盘上形成凹部，在凹部中连接有电极焊盘和凸块电极。电极焊盘形成在软层的表面上，并且通过电极焊盘和软层的弹性变形形成凹部。

58. 发明授权

US06335867B1 Apparatus for interconnecting logic boards 失效
标题翻译：用于互连逻辑板的装置
公开(公告)号：US06335867B1
公开(公告)日：2002-01-01
申请号：US09708594
申请日：2000-11-09
申请人： Kenichi Ishibashi , Takehisa Hayashi , Tsutomu Goto , Akira Yamagiwa , Tsuyoshi Watanabe
发明人： Kenichi Ishibashi , Takehisa Hayashi , Tsutomu Goto , Akira Yamagiwa , Tsuyoshi Watanabe
IPC分类号： H05K0114
CPC分类号： G06F1/185 , G06F1/184 , G06F1/186 , H05K1/14 , H05K7/1445
摘要： Apparatus for interconnecting logic boards is provided with a backplane, a plurality of logic boards connected to the backplane, and a plurality of interconnecting boards, connected to the backplane, for interconnecting the plurality of logic boards. In the apparatus, the plurality of logic boards are connected to the backplane with the logic boards in vertical position at right angles with the interconnecting boards and a specified distance away from the interconnecting boards.
摘要翻译：用于互连逻辑板的装置设置有背板，连接到背板的多个逻辑板，以及连接到背板的多个互连板，用于互连多个逻辑板。在该装置中，多个逻辑板连接到背板，逻辑板与互连板成垂直的垂直位置，并且距离互连板一定距离。

59. 发明授权

US6163464A Apparatus for interconnecting logic boards 失效
公开(公告)号：US6163464A
公开(公告)日：2000-12-19
申请号：US128779
申请日：1998-08-04
申请人： Kenichi Ishibashi , Takehisa Hayashi , Tsutomu Goto , Akira Yamagiwa , Tsuyoshi Watanabe
发明人： Kenichi Ishibashi , Takehisa Hayashi , Tsutomu Goto , Akira Yamagiwa , Tsuyoshi Watanabe
IPC分类号： G06F3/00 , G06F1/18 , H05K1/14 , H05K7/14
CPC分类号： G06F1/185 , G06F1/184 , G06F1/186 , H05K1/14 , H05K7/1445
摘要： Apparatus for interconnecting logic boards is provided with a backplane, a plurality of logic boards connected to the backplane, and a plurality of interconnecting boards, connected to the backplane, for interconnecting the plurality of logic boards. In the apparatus, the plurality of logic boards are connected to the backplane with the logic boards in vertical position at right angles with the interconnecting boards and a specified distance away from the interconnecting boards.

60. 发明授权

US5852728A Uninterruptible clock supply apparatus for fault tolerant computer system 失效
标题翻译：用于容错计算机系统的不间断时钟提供装置
公开(公告)号：US5852728A
公开(公告)日：1998-12-22
申请号：US585344
申请日：1996-01-11
申请人： Koji Matsuda , Soichi Takaya , Yoshihiro Miyazaki , Kenichi Kurosawa , Shinichiro Yamaguchi , Sako Ishikawa , Akira Yamagiwa , Masao Inoue , Kenji Kashiwagi
发明人： Koji Matsuda , Soichi Takaya , Yoshihiro Miyazaki , Kenichi Kurosawa , Shinichiro Yamaguchi , Sako Ishikawa , Akira Yamagiwa , Masao Inoue , Kenji Kashiwagi
IPC分类号： G06F1/04 , G06F11/16 , G06F11/18 , G06F11/20 , G06F1/06
CPC分类号： G06F11/1604 , G06F1/04 , G06F11/1679 , G06F11/20
摘要： The present invention concerns clock source switchover between dual clock sources in the event of failure of any of them without affecting the clock output in the dual system, thereby preventing malfunctioning of processors therein. In the fault tolerant computer system of the invention, each of the plural processing units comprises a clock source, a clock selector, a clock stop detection unit, a clock phase adjusting unit, and a phase coincidence detection/operation suppression/resetting unit, whereby when switching over from a faulty clock source to a normal clock source in the event of clock failure, the clock phase adjusting unit ensures continuity in the output clock signals. The clock phase adjusting unit provided in the subsequent stage of the clock selector inserts the PLL circuit having an overdamping response characteristic obtained by lowering the gain of its loop filter.
摘要翻译：本发明涉及双时钟源中的任何一个时钟源的时钟源切换，而不会影响双系统中的时钟输出，从而防止其中的处理器的故障。在本发明的容错计算机系统中，多个处理单元中的每一个包括时钟源，时钟选择器，时钟停止检测单元，时钟相位调整单元和相位一致检测/操作抑制/复位单元，由此在时钟故障的情况下，当从故障时钟源切换到正常时钟源时，时钟相位调整单元确保输出时钟信号的连续性。设置在时钟选择器的后续级中的时钟相位调整单元插入具有通过降低其环路滤波器的增益而获得的过阻抗响应特性的PLL电路。

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