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    • 5. 发明授权
    • Signal transmitting device suited to fast signal transmission
    • 信号传输设备适合快速信号传输
    • US07911224B2
    • 2011-03-22
    • US12116541
    • 2008-05-07
    • Toshitsugu TakekumaRyoichi KuriharaAkira Yamagiwa
    • Toshitsugu TakekumaRyoichi KuriharaAkira Yamagiwa
    • H03K19/003
    • H04L25/0298G06F13/4072G06F13/4086H04B3/02H04L25/0278H04L25/028H04L25/0292H05K1/0216H05K1/0237H05K1/14
    • A signal transmitting circuit includes a circuit block having a driving circuit and an intra-block transmission line for transmitting a signal from the driving circuit, a circuit block having a receiving circuit and an intra-block transmission line for transmitting the signal to said receiving circuit, and a main interblock transmission line for propagating a signal between the driving and receiving circuit blocks. The inter-block transmission line is terminated by a resistor having substantially the same impedance as the interblock transmission line. The intra-block transmission lines are provided with a resistance element having a resistance substantially equal to a value derived by subtracting half of an impedance of the inter-block transmission line from an impedance of the intra-block transmission line, to lower signal amplitude and suppress reflections of a signal at branch points along the main interblock transmission line, thereby enabling a high-speed signal transfer.
    • 信号发送电路包括具有用于发送来自驱动电路的信号的驱动电路和块内传输线路的电路块,具有接收电路的电路块和用于将信号发送到所述接收电路的块内传输线路 以及用于在驱动和接收电路块之间传播信号的主块间传输线。 块间​​传输线由具有与块间传输线基本上相同阻抗的电阻端接。 块内传输线路设置有电阻元件,其电阻基本上等于通过将块间传输线路的阻抗的一半从块内传输线路的阻抗减去一半到更低的信号幅度, 抑制沿着主块间传输线的分支点处的信号的反射,从而实现高速信号传送。
    • 8. 发明授权
    • Branch bus system for inter-LSI data transmission
    • 分支总线系统,用于LSI间数据传输
    • US06766404B1
    • 2004-07-20
    • US09568055
    • 2000-05-10
    • Hideki OsakaAkira YamagiwaKenichi Ishibashi
    • Hideki OsakaAkira YamagiwaKenichi Ishibashi
    • G06F100
    • H04L25/0278G06F13/4077
    • A fast transfer bus system capable of fast data transfer with no reflection at branch points. Four LSIs having constant-impedance interfaces are connected via two variable resistors each having three signal terminals. A variable impedance LSI is connected between these variable resistors. When the LSIs connected to the variable resistor do not work as a bus driver, three variable resistance elements in each variable resistor are set to have a value of ⅓ of the characteristic impedance Zo of connection lines, and are connected in a Y-letter shape. When one of LSIs connected to the variable resistor works as a bus driver, the values of the variable resistance elements are set to low impedance or Zo.
    • 快速传输总线系统,能够快速传输数据,在分支点无反射。 具有恒定阻抗接口的四个LSI通过两个可变电阻器连接,每个可变电阻器具有三个信号端子。 可变阻抗LSI连接在这些可变电阻之间。 当连接到可变电阻器的LSI不能用作总线驱动器时,每个可变电阻器中的三个可变电阻元件被设置为连接线的特性阻抗Zo的1/3,并且以Y- 字母形状。 当连接到可变电阻器的LSI中的一个作为总线驱动器工作时,可变电阻元件的值被设置为低阻抗或Zo。