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51. 发明授权

US07564735B2 Memory device, and method for operating a memory device 有权
标题翻译：存储器件和操作存储器件的方法
公开(公告)号：US07564735B2
公开(公告)日：2009-07-21
申请号：US11481157
申请日：2006-07-05
申请人： Martin Brox , Thomas Hein
发明人： Martin Brox , Thomas Hein
IPC分类号： G11C7/00
CPC分类号： G11C29/26 , G11C11/4087 , G11C29/1201 , G11C29/46
摘要： A memory device, in particular to a DRAM, and a system comprising a memory device is disclosed. Further, the invention relates to a method for operating a memory device. According to an embodiment of the invention, a memory device is provided, including: a first chip select pin, and a second chip select pin. Further, a method for operating a memory device is provided, the memory device including a first chip select pin, and a second chip select pin, the method including: applying a chip select signal to the first or the second chip select pin.
摘要翻译：公开了一种存储器件，特别是DRAM，以及包括存储器件的系统。此外，本发明涉及一种用于操作存储器件的方法。根据本发明的一个实施例，提供了一种存储器件，包括：第一芯片选择引脚和第二芯片选择引脚。此外，提供了一种用于操作存储器件的方法，所述存储器件包括第一芯片选择引脚和第二芯片选择引脚，所述方法包括：将片选信号施加到第一芯片选择引脚或第二芯片选择引脚。

52. 发明授权

US07515456B2 Memory circuit, a dynamic random access memory, a system comprising a memory and a floating point unit and a method for storing digital data 失效
标题翻译：存储器电路，动态随机存取存储器，包括存储器和浮点单元的系统以及用于存储数字数据的方法
公开(公告)号：US07515456B2
公开(公告)日：2009-04-07
申请号：US11530858
申请日：2006-09-11
申请人： Peter Mayer , Wolfgang Spirkl , Markus Balb , Christoph Bilger , Martin Brox , Thomas Hein , Michael Richter
发明人： Peter Mayer , Wolfgang Spirkl , Markus Balb , Christoph Bilger , Martin Brox , Thomas Hein , Michael Richter
IPC分类号： G11C11/00
CPC分类号： G11C7/16 , G11C7/1006 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C11/4085 , G11C11/4096
摘要： A memory circuit comprises a D/A converter connected with an input/output circuit and with a writing circuit, wherein the D/A converter converts a digital data with at least two digital bits received from the input/output circuit to one analog value and forwards the analog value to the writing circuit, wherein the digital data is at least a part of a floating point number, wherein the writing circuit writes the analog value in at least one selected memory cell, and an A/D converter connected with a reading circuit and with the input/output circuit, wherein the reading circuit reads an analog value from a selected memory cell and forwards the analog value to the A/D converter, wherein the A/D converter converts the analog value to digital data, and wherein the A/D converter forwards the digital data to the input/output circuit. Furthermore, a method is provided for reading data from at least one memory cell of a memory, wherein an analog value is read from the memory cell and the analog value is corrected according to a correction factor representing a storage time the analog value was stored and wherein the corrected analog value is converted to digital data.
摘要翻译：存储电路包括与输入/输出电路和写入电路连接的D / A转换器，其中D / A转换器将具有从输入/输出电路接收的至少两个数字位的数字数据转换成一个模拟值，将模拟值转发到写入电路，其中数字数据是浮点数的至少一部分，其中写入电路将模拟值写入至少一个选择的存储单元，以及与读取器连接的A / D转换器电路和输入/输出电路，其中读取电路从所选择的存储器单元读取模拟值并将模拟值转发到A / D转换器，其中A / D转换器将模拟值转换为数字数据，其中 A / D转换器将数字数据转发到输入/输出电路。此外，提供一种用于从存储器的至少一个存储单元读取数据的方法，其中从存储器单元读取模拟值，并且根据表示存储模拟值的存储时间的校正因子来校正模拟值，以及其中所述经修正的模拟值被转换为数字数据。

53. 发明申请

US20080225603A1 Circuit 有权
标题翻译：电路
公开(公告)号：US20080225603A1
公开(公告)日：2008-09-18
申请号：US11726401
申请日：2007-03-21
申请人： Thomas Hein
发明人： Thomas Hein
IPC分类号： G11C7/10 , G11C8/18
CPC分类号： G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/1093
摘要： An embodiment of a circuit includes an output buffer, a data interface which is at least in a position to transmit data, the data interface being coupled to an output of the output buffer, a command/address interface coupled to an input of the output buffer, a memory core coupled to the input of the output buffer, and a controller circuit configured to cause data stored within the output buffer to be output to the data interface, further configured to cause data stored within the memory core to be output to the input of the output buffer, so that the data is stored within the output buffer, and further configured to cause provision of data received at the command/address interface to the input of the output buffer, so that the data is stored within the output buffer.
摘要翻译：电路的一个实施例包括一个输出缓冲器，至少在一个位置上传输数据的数据接口，该数据接口耦合到该输出缓冲器的一个输出端;一个命令/地址接口，耦合到输出缓冲器的输入端耦合到所述输出缓冲器的输入的存储器核心;以及控制器电路，被配置为将存储在所述输出缓冲器内的数据输出到所述数据接口，还被配置为使存储在所述存储器核心内的数据输出到所述输入，使得数据存储在输出缓冲器内，并进一步被配置为使得在命令/地址接口处接收到的数据提供给输出缓冲器的输入，使得数据被存储在输出缓冲器内。

54. 发明申请

US20080117223A1 Display with memory for storing picture data 审中-公开
标题翻译：显示用于存储图像数据的存储器
公开(公告)号：US20080117223A1
公开(公告)日：2008-05-22
申请号：US11602716
申请日：2006-11-21
申请人： Peter Mayer , Wolfgang Spirkl , Markus Balb , Christoph Bilger , Martin Brox , Thomas Hein , Michael Richter
发明人： Peter Mayer , Wolfgang Spirkl , Markus Balb , Christoph Bilger , Martin Brox , Thomas Hein , Michael Richter
IPC分类号： G06T1/60
CPC分类号： G06F3/14 , G09G5/363 , G09G2320/103 , G09G2330/021 , G09G2360/06 , G09G2360/18
摘要： A display having a screen, and memory for storing picture data is disclosed. In one embodiment, the screen includes a plurality of pixels, the pixels in a first mode of the display being controlled by the picture data stored in the memory, and in a second mode of the display being controlled by picture data received from an external processing unit.
摘要翻译：公开了一种具有屏幕的显示器和用于存储图像数据的存储器。在一个实施例中，屏幕包括多个像素，显示器的第一模式中的像素由存储在存储器中的图像数据控制，并且显示器的第二模式由从外部处理接收的图像数据控制单元。

55. 发明申请

US20050270852A1 Read latency control circuit 有权
标题翻译：读延迟控制电路
公开(公告)号：US20050270852A1
公开(公告)日：2005-12-08
申请号：US11136712
申请日：2005-05-25
申请人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Peter Schroegmeier
发明人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Peter Schroegmeier
IPC分类号： G06F3/06 , G11C7/22 , G11C11/4076
CPC分类号： G11C11/4076 , G11C7/1066 , G11C7/20 , G11C7/22 , G11C7/222 , G11C11/4072 , G11C2207/2272
摘要： The invention provides a method for setting and controlling a read latency (L) by means of a FIFO-based read latency control circuit for a read access to a semiconductor memory, having the method steps of providing a common internal clock signal; generating an internal first clock signal and an internal second clock signal, which is different from the first clock signal, from the common clock signal; generating an output pointer for reading out the read data from the first clock signal; generating an input pointer for reading in the read data from the second clock signal; initializing the input and output pointers by allocating a defined, fixedly predetermined time offset between output pointer and input pointer. The invention furthermore provides a corresponding circuit arrangement for carrying out the method.
摘要翻译：本发明提供了一种用于通过用于对半导体存储器的读取访问的基于FIFO的读延迟控制电路来设置和控制读延迟（L）的方法，具有提供公共内部时钟信号的方法步骤; 从公共时钟信号产生与第一时钟信号不同的内部第一时钟信号和内部第二时钟信号; 产生用于从所述第一时钟信号读出读取数据的输出指针; 生成用于从所述第二时钟信号读取所述读取数据的输入指针; 通过在输出指针和输入指针之间分配定义的，固定地预定的时间偏移来初始化输入和输出指针。本发明还提供了一种用于执行该方法的相应电路装置。

56. 发明申请

US20050253638A1 Method and circuit arrangement for resetting an integrated circuit 有权
标题翻译：用于复位集成电路的方法和电路装置
公开(公告)号：US20050253638A1
公开(公告)日：2005-11-17
申请号：US11117736
申请日：2005-04-29
申请人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Peter Schrogmeier
发明人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Peter Schrogmeier
IPC分类号： G06F1/24 , G11C5/14 , G11C11/4072 , H01L21/82 , H03K5/1534 , H03L7/00
CPC分类号： G06F1/24 , H03K5/1534
摘要： The invention relates to a method for resetting at least one circuit part of an integrated circuit, in particular a synchronous semiconductor memory, in which a clock signal and a clock signal that is inverted with respect to the latter are provided in order to clock the integrated circuit, and in which, when a reset condition is present, an item of reset information is coded onto the clock signal or onto the inverted clock signal. The invention also relates to a circuit arrangement for carrying out the method according to the invention, having a clock suppression device and a decoder circuit, which is intended to extract the reset information from the clock signal or from the inverted clock signal.
摘要翻译：本发明涉及一种用于复位集成电路，特别是同步半导体存储器的至少一个电路部分的方法，其中提供时钟信号和相对于后者反相的时钟信号，以便对集成电路电路，并且当存在复位条件时，将复位信息的项目编码到时钟信号或反相时钟信号上。本发明还涉及用于执行根据本发明的方法的电路装置，其具有时钟抑制装置和解码器电路，其用于从时钟信号或反相时钟信号中提取复位信息。

57. 发明授权

US06946848B2 Calibration configuration 失效
标题翻译：校准配置
公开(公告)号：US06946848B2
公开(公告)日：2005-09-20
申请号：US10673965
申请日：2003-09-29
申请人： Andreas Täuber , Thomas Hein , Aaron Nygren
发明人： Andreas Täuber , Thomas Hein , Aaron Nygren
IPC分类号： G01R35/00 , G01R31/00 , G01R27/08 , G01R21/36
CPC分类号： G01R35/007
摘要： A calibration configuration for setting an adjustable impedance has a voltage divider with a variable resistor and a resistor connected in series, which circuit is supplied with potentials of a supply voltage and has, between the resistors, a partial voltage tap off terminal. A circuit has a further resistor, whose value is in a fixed relationship with a resistance of the first voltage divider resistor, and generates a voltage dependent upon a value derived from the further resistor. The voltage and the partial voltage are fed to a comparator for outputting a comparison result to a downstream control logic unit, which logic unit is coupled to the resistor of the first voltage divider and generates a control signal dependent upon the comparator output signal. The control logic unit control signal is used to set the variable resistor until the voltages fed to the comparator correspond to one another.
摘要翻译：用于设置可调阻抗的校准配置具有分压器，其具有可变电阻器和串联连接的电阻器，该电路被供给电源电压，并且在电阻器之间具有部分电压抽头端子。电路具有另一个电阻，其值与第一分压电阻器的电阻成固定关系，并且产生取决于从另一电阻器导出的值的电压。电压和部分电压被馈送到比较器，用于将比较结果输出到下游控制逻辑单元，该逻辑单元耦合到第一分压器的电阻器，并根据比较器输出信号产生控制信号。控制逻辑单元控制信号用于设置可变电阻，直到馈送到比较器的电压彼此相对应。

58. 发明授权

US06480024B2 Circuit configuration for programming a delay in a signal path 有权
公开(公告)号：US06480024B2
公开(公告)日：2002-11-12
申请号：US10046395
申请日：2001-10-19
申请人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Michael Markert , Thilo Marx , Torsten Partsch , Sabine Schöniger Kieser , Peter Schrögmeier , Michael Sommer , Christian Weis
发明人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Michael Markert , Thilo Marx , Torsten Partsch , Sabine Schöniger Kieser , Peter Schrögmeier , Michael Sommer , Christian Weis
IPC分类号： H03K190173
CPC分类号： H03K5/133 , H03K2005/00065 , H03K2005/00071 , H03K2005/00091
摘要： A circuit configuration includes two signal path sections that are used to program the delay of a signal path, in particular in DRAMs. The two signal path sections have different delays and can be driven in parallel at the input end. The two signal path sections can be connected to an output terminal via a multiplexer. A selection circuit includes two signal path sections which are connected between supply voltage potentials. The selection circuit has two complimentary transistors which are connected in series and has source-end programmable elements. These transistors can be driven by complimentary control signals. This permits the delay to be programmed flexibly with little expenditure on circuitry.

59. 发明授权

US06188642B1 Integrated memory having column decoder for addressing corresponding bit line 失效
标题翻译：具有用于寻址相应位线的列解码器的集成存储器
公开(公告)号：US06188642B1
公开(公告)日：2001-02-13
申请号：US09348736
申请日：1999-07-06
申请人： Sabine Schöniger , Peter Schrögmeier , Thomas Hein , Stefan Dietrich , Thilo Marx
发明人： Sabine Schöniger , Peter Schrögmeier , Thomas Hein , Stefan Dietrich , Thilo Marx
IPC分类号： G11C800
CPC分类号： G11C8/00
摘要： The integrated memory has a column decoder for decoding column addresses and for addressing corresponding bit lines. The memory also has a first column address bus, which is used to transfer first column addresses to the column decoder, and a second column address bus, which is used to transfer second column addresses to the column decoder. The column decoder in each case addresses bit lines which correspond to the first and second column addresses supplied to it.
摘要翻译：集成存储器具有用于解码列地址并用于寻址对应位线的列解码器。存储器还具有第一列地址总线，其用于将第一列地址传送到列解码器，以及第二列地址总线，其用于将第二列地址传送到列解码器。列解码器在每种情况下都对应于提供给它的第一列地址和第二列地址的位线。

60. 发明授权

US6028815A Integrated memory 有权
标题翻译：集成内存
公开(公告)号：US6028815A
公开(公告)日：2000-02-22
申请号：US258940
申请日：1999-03-01
申请人： Sabine Schoniger , Peter Schrogmeier , Thomas Hein , Stefan Dietrich
发明人： Sabine Schoniger , Peter Schrogmeier , Thomas Hein , Stefan Dietrich
IPC分类号： G11C7/10 , G11C8/00 , G11C8/14
CPC分类号： G11C7/1006 , G11C8/00 , G11C8/14
摘要： The integrated memory has byte selection lines for selecting all the bit lines of a respective byte, as well as masking signals that are allocated to the respective byte of at least one word. In addition, the memory has a column decoder with outputs which are connected to the word selection lines, each of which, when addressed, causes all the byte selection lines for one of the words to be simultaneously selected if none of the masking signals are active. The masking signals, when activated, prevent the addressed word selection line from selecting the byte selection lines, allocated to a corresponding byte, for a corresponding word.
摘要翻译：集成存储器具有用于选择相应字节的所有位线的字节选择线以及分配给至少一个字的相应字节的屏蔽信号。此外，存储器具有列解码器，其具有连接到字选择线的输出，每个字选择线在寻址时都使得如果没有一个屏蔽信号有效则同时选择一个字的所有字节选择线。屏蔽信号被激活时，防止寻址字选择线选择分配给相应字节的字节选择线作为相应字。

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