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51. 发明申请

US20060140026A1 Method and apparatus for improving yield in semiconductor devices by guaranteeing health of redundancy information 失效
公开(公告)号：US20060140026A1
公开(公告)日：2006-06-29
申请号：US11024516
申请日：2004-12-28
申请人： Alper Ilkbahar , Derek Bosch
发明人： Alper Ilkbahar , Derek Bosch
IPC分类号： G11C29/00
CPC分类号： G11C29/76
摘要： A method is provided comprising reading a set of memory cells indicating whether stored redundancy information is reliable and, if the set of memory cells indicates that the stored redundancy information is reliable, determining whether to read primary memory or redundant memory based on the stored redundancy information. Another method is provided comprising reading a set of memory cells associated with a group of memory cells in a primary memory, the set of memory cells indicating whether data can be reliably stored in the group of memory cells; if the set of memory cells indicates that data can be reliably stored in the group of memory cells, storing data in the group of memory cells; and if the set of memory cells does not indicate that data can be reliably stored in the group of memory cells, storing data in a group of memory cells in a redundant memory. In another preferred embodiment, a method for providing memory redundancy is provided.

52. 发明授权

US07005350B2 Method for fabricating programmable memory array structures incorporating series-connected transistor strings 有权
标题翻译：用于制造并入串联晶体管串的可编程存储器阵列结构的方法
公开(公告)号：US07005350B2
公开(公告)日：2006-02-28
申请号：US10335089
申请日：2002-12-31
申请人： Andrew J. Walker , En-Hsing Chen , Sucheta Nallamothu , Roy E. Scheuerlein , Alper Ilkbahar , Luca Fasoli , Igor Koutnetsov , Christopher Petti
发明人： Andrew J. Walker , En-Hsing Chen , Sucheta Nallamothu , Roy E. Scheuerlein , Alper Ilkbahar , Luca Fasoli , Igor Koutnetsov , Christopher Petti
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , G11C16/0483 , H01L27/115 , H01L27/11502
摘要： A three-dimensional flash memory array incorporates thin film transistors having a charge storage dielectric arranged in series-connected NAND strings to achieve a 4F2 memory cell layout. The memory array may be programmed and erased using only tunneling currents, and no leakage paths are formed through non-selected memory cells. Each NAND string includes two block select devices for respectively coupling one end of the NAND string to a global bit line, and the other end to a shared bias node. Pairs of NAND strings within a block share the same global bit line. The memory cells are preferably depletion mode SONOS devices, as are the block select devices. The memory cells may be programmed to a near depletion threshold voltage, and the block select devices are maintained in a programmed state having a near depletion mode threshold voltage. NAND strings on more than one layer may be connected to global bit lines on a single layer. By interleaving the NAND strings on each memory level and using two shared bias nodes per block, very little additional overhead is required for the switch devices at each end of the NAND strings. The NAND strings on different memory levels are preferably connected together by way of vertical stacked vias, each preferably connecting to more than one memory level. Each memory level may be produced with less than three masks per level.
摘要翻译：三维闪存阵列包括具有布置在串联连接的NAND串中的电荷存储电介质的薄膜晶体管，以实现4F 2存储单元布局。可以仅使用隧穿电流对存储器阵列进行编程和擦除，并且不通过未选择的存储器单元形成泄漏路径。每个NAND串包括用于分别将NAND串的一端耦合到全局位线的两个块选择器件，另一端连接到共享偏置节点。块内的一对NAND串共享相同的全局位线。存储器单元优选地是耗尽型SONOS器件，块选择器件也是如此。存储器单元可以被编程为接近耗尽阈值电压，并且块选择器件保持在具有接近耗尽模式阈值电压的编程状态。多个层上的NAND串可以连接到单个层上的全局位线。通过在每个存储器级别交错NAND串并且每个块使用两个共享偏置节点，对于NAND串的每一端的开关器件需要非常少的附加开销。不同存储器级别的NAND串优选通过垂直堆叠的通孔连接在一起，每个优选地连接到多于一个的存储器级。每个存储器级别可以以每级别少于三个掩码来生成。

53. 发明授权

US06928590B2 Memory device and method for storing bits in non-adjacent storage locations in a memory array 有权
标题翻译：用于存储存储器阵列中非相邻存储位置中的位的存储器件和方法
公开(公告)号：US06928590B2
公开(公告)日：2005-08-09
申请号：US10024647
申请日：2001-12-14
申请人： Alper Ilkbahar , Roy E. Scheuerlein , Derek J. Bosch
发明人： Alper Ilkbahar , Roy E. Scheuerlein , Derek J. Bosch
IPC分类号： G06F11/00 , G06F11/10 , H04B1/74
CPC分类号： G06F11/1028
摘要： The preferred embodiments described herein provide a memory device and method for storing bits in non-adjacent storage locations in a memory array. In one preferred embodiment, a memory device is provided comprising a register and a memory array. A plurality of bits provided to the memory device are stored in the register in a first direction, read from the register in a second direction, and then stored in the memory array. Bits that are adjacent to one another when provided to the memory device are stored in non-adjacent storage locations in the memory array. When the plurality of bits takes the form of an ECC word, the storage of bits in non-adjacent storage locations in the memory array reduces the likelihood of an uncorrectable multi-bit error. In another preferred embodiment, a memory device is provided comprising a memory array and a register comprising a first set of wordlines and bitlines and a second set of wordlines and bitlines arranged orthogonal to the first set. In yet another preferred embodiment, memory decoders or a host device is used to store bits in non-adjacent storage locations in a memory array of a memory device. Other preferred embodiments are provided, and each of the preferred embodiments described herein can be used alone or in combination with one another.
摘要翻译：本文描述的优选实施例提供了一种用于存储位于存储器阵列中的非相邻存储位置中的位的存储器件和方法。在一个优选实施例中，提供了包括寄存器和存储器阵列的存储器件。提供给存储器件的多个位以第一方向存储在寄存器中，从第二方向从寄存器读取，然后存储在存储器阵列中。当提供给存储器件时彼此相邻的位被存储在存储器阵列中的非相邻存储位置中。当多个位采用ECC字的形式时，存储器阵列中非相邻存储位置中的位的存储减少了不可校正的多位错误的可能性。在另一个优选实施例中，提供了存储器件，其包括存储器阵列和包括第一组字线和位线的寄存器以及与第一组正交布置的第二组字线和位线。在另一优选实施例中，存储器解码器或主机设备用于存储存储器件的存储器阵列中的非相邻存储位置中的位。提供了其它优选实施方案，并且本文所述的各优选实施方案可以单独使用或彼此组合使用。

54. 发明申请

US20050128807A1 Nand memory array incorporating multiple series selection devices and method for operation of same 审中-公开
标题翻译：包含多个系列选择装置的Nand存储器阵列及其操作方法
公开(公告)号：US20050128807A1
公开(公告)日：2005-06-16
申请号：US10729865
申请日：2003-12-05
申请人： En-Hsing Chen , Andrew Walker , Roy Scheuerlein , Sucheta Nallamothu , Alper Ilkbahar , Luca Fasoli , James Cleeves
发明人： En-Hsing Chen , Andrew Walker , Roy Scheuerlein , Sucheta Nallamothu , Alper Ilkbahar , Luca Fasoli , James Cleeves
IPC分类号： G11C8/08 , G11C16/04 , G11C16/08 , G11C16/34
CPC分类号： G11C16/0483 , G11C8/08 , G11C16/08 , G11C16/3418 , G11C16/3427
摘要： An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.
摘要翻译：示例性的NAND串存储器阵列提供半选择的存储器单元通道的电容性升压以减少半选择单元的程序干扰效应。为了减小升压电平的漏电流劣化的影响，采用较短持续时间的多个编程脉冲来限制这种漏电流可能降低未选择的NAND串中的电压的时间周期。此外，在每个NAND串的一端或两端的多个串联选择装置进一步确保了对于未选择的和选择的NAND串的这种选择装置的减少的泄漏。在某些示例性实施例中，存储器阵列包括具有电荷存储电介质的存储单元晶体管的串联连接的NAND串，并且包括形成在衬底上方的多于一个的存储单元平面。

55. 发明申请

US20050122780A1 NAND memory array incorporating multiple write pulse programming of individual memory cells and method for operation of same 有权
标题翻译： NAND存储器阵列结合了各个存储单元的多个写脉冲编程及其操作方法
公开(公告)号：US20050122780A1
公开(公告)日：2005-06-09
申请号：US10729844
申请日：2003-12-05
申请人： En-Hsing Chen , Andrew Walker , Roy Scheuerlein , Sucheta Nallamothu , Alper Ilkbahar , Luca Fasoli
发明人： En-Hsing Chen , Andrew Walker , Roy Scheuerlein , Sucheta Nallamothu , Alper Ilkbahar , Luca Fasoli
IPC分类号： G11C5/02 , G11C11/56 , G11C16/04 , G11C16/10
CPC分类号： G11C16/10 , G11C11/5671 , G11C16/0466 , G11C16/0483
摘要： An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.
摘要翻译：示例性的NAND串存储器阵列提供半选择的存储器单元通道的电容性升压以减少半选择单元的程序干扰效应。为了减小升压电平的漏电流劣化的影响，采用较短持续时间的多个编程脉冲来限制这种漏电流可能降低未选择的NAND串中的电压的时间周期。此外，在每个NAND串的一端或两端的多个串联选择装置进一步确保了对于未选择的和选择的NAND串的这种选择装置的减少的泄漏。在某些示例性实施例中，存储器阵列包括具有电荷存储电介质的存储单元晶体管的串联连接的NAND串，并且包括形成在衬底上方的多于一个的存储单元平面。

56. 发明申请

US20050079675A1 Semiconductor device with localized charge storage dielectric and method of making same 有权
公开(公告)号：US20050079675A1
公开(公告)日：2005-04-14
申请号：US10965763
申请日：2004-10-18
申请人： Alper Ilkbahar , Roy Scheuerlein , Andrew Walker , Luca Fasoli
发明人： Alper Ilkbahar , Roy Scheuerlein , Andrew Walker , Luca Fasoli
IPC分类号： G11C16/04 , H01L21/28 , H01L21/336 , H01L29/792 , H01L21/00 , H01L21/31 , H01L21/469 , H01L21/84
CPC分类号： H01L29/66833 , G11C16/0466 , G11C16/0491 , H01L21/28282 , H01L29/792
摘要： An array of transistors includes a plurality of transistors, a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction. Each transistor includes a source, a drain, a channel and a localized charge storage dielectric. A first transistor of the plurality of transistors and a second transistor of the plurality of transistors share a common source/drain. A first localized charge storage dielectric of the first transistor does not overlap the common source/drain and a second localized charge storage dielectric of the second transistor overlaps the common source/drain.

57. 发明授权

US06868022B2 Redundant memory structure using bad bit pointers 有权
标题翻译：冗余内存结构使用坏位指针
公开(公告)号：US06868022B2
公开(公告)日：2005-03-15
申请号：US10402385
申请日：2003-03-28
申请人： Roy E. Scheuerlein , Mark G. Johnson , Derek J. Bosch , Alper Ilkbahar , J. James Tringali
发明人： Roy E. Scheuerlein , Mark G. Johnson , Derek J. Bosch , Alper Ilkbahar , J. James Tringali
IPC分类号： G11C7/10 , G11C7/24 , G11C29/00 , G11C29/44 , G11C7/00
CPC分类号： G11C29/76 , G11C7/1006 , G11C7/24 , G11C29/44 , G11C29/4401 , G11C29/78
摘要： The preferred embodiments described herein relate to a redundant memory structure using bad bit pointers. In one preferred embodiment, data is written in a first plurality of memory cells, and an error is detected in writing data in one of the memory cells. In response to the detected error, a pointer is written in a second plurality of memory cells, the pointer identifying which memory cell in the first plurality of memory cells contains the error. During a read operation, the data is read from the first plurality of memory cells, and the pointer is read from the second plurality of memory cells. From the pointer, the memory cell containing the error is identified, and the error is corrected. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.
摘要翻译：这里描述的优选实施例涉及使用坏位指针的冗余存储器结构。在一个优选实施例中，将数据写入第一多个存储单元，并且在存储单元之一中写入数据时检测到错误。响应于检测到的错误，指针被写入第二多个存储单元中，该指针标识第一多个存储单元中的哪个存储单元包含该错误。在读操作期间，从第一多个存储单元读取数据，并从第二多个存储单元读取指针。从指针中，识别包含错误的存储单元，并纠正错误。提供了其它优选实施方案，并且每个优选实施方案可以单独使用或彼此组合使用。

58. 发明申请

US20050044459A1 Redundant memory structure using bad bit pointers 有权
公开(公告)号：US20050044459A1
公开(公告)日：2005-02-24
申请号：US10961501
申请日：2004-10-08
申请人： Roy Scheuerlein , Mark Johnson , Derek Bosch , Alper Ilkbahar , J. Tringali
发明人： Roy Scheuerlein , Mark Johnson , Derek Bosch , Alper Ilkbahar , J. Tringali
IPC分类号： G11C7/10 , G11C7/24 , G11C29/00 , G11C29/44
CPC分类号： G11C29/76 , G11C7/1006 , G11C7/24 , G11C29/44 , G11C29/4401 , G11C29/78
摘要： The preferred embodiments described herein relate to a redundant memory structure using bad bit pointers. In one preferred embodiment, data is written in a first plurality of memory cells, and an error is detected in writing data in one of the memory cells. In response to the detected error, a pointer is written in a second plurality of memory cells, the pointer identifying which memory cell in the first plurality of memory cells contains the error. During a read operation, the data is read from the first plurality of memory cells, and the pointer is read from the second plurality of memory cells. From the pointer, the memory cell containing the error is identified, and the error is corrected. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.

59. 发明授权

US06629274B1 Method and apparatus to structurally detect random defects that impact AC I/O timings in an input/output buffer 失效
标题翻译：结构上检测影响输入/输出缓冲器中的AC I / O时序的随机缺陷的方法和装置
公开(公告)号：US06629274B1
公开(公告)日：2003-09-30
申请号：US09470091
申请日：1999-12-21
申请人： Mike Tripp , Tak M. Mak , Alper Ilkbahar , R. Tim Frodsham
发明人： Mike Tripp , Tak M. Mak , Alper Ilkbahar , R. Tim Frodsham
IPC分类号： G11C2900
CPC分类号： G11C29/50012 , G01R31/31716 , G01R31/3185 , G11C29/02
摘要： According to one embodiment, a method of conducting a switching state (AC) loop back test at a buffer circuit comprises varying the relationship between the generation of strobe signals at a strobe input/output (I/O) circuit of a first group of I/O circuits and the reception of data at the first group of I/O circuits receiving the strobe signals fails, and comparing the time at which the first I/O circuit fails with a predetermined timing performance for the first group of I/O circuits. Subsequently, it is determined whether the first group of I/O circuits satisfies the predetermined timing performance.
摘要翻译：根据一个实施例，在缓冲电路处进行开关状态（AC）环回测试的方法包括改变第一组I的选通输入/输出（I / O）电路之间的选通信号的产生之间的关系 / O电路和接收到选通信号的第一组I / O电路的数据接收失败，并且将第一I / O电路故障的时间与第一组I / O电路的预定定时性能进行比较。随后，确定第一组I / O电路是否满足预定的定时性能。

60. 发明授权

US06545520B2 Method and apparatus for electro-static discharge protection 有权
标题翻译：静电放电保护方法及装置
公开(公告)号：US06545520B2
公开(公告)日：2003-04-08
申请号：US09820111
申请日：2001-03-28
申请人： Timothy J. Maloney , Alper Ilkbahar
发明人： Timothy J. Maloney , Alper Ilkbahar
IPC分类号： H02H904
CPC分类号： H01L27/0285 , Y10S977/70 , Y10S977/94
摘要： A circuit includes an output driver, where the output driver includes a pull-up device and a pull-down device. The pull-up device has a first control terminal that is responsive to an RC-timer so as to bias the pull-up device on in response to an electrostatic discharge (ESD) event that activates a device coupled to an output of the RC-timer. The pull-down device has a second control terminal that, for one aspect, is in a substantially indeterminate state (i.e. the second control terminal may be a “1”, “0” or some other voltage, which may or may not be within the voltage range between “1” and “0”) during the ESD event.
摘要翻译：电路包括输出驱动器，其中输出驱动器包括上拉装置和下拉装置。上拉装置具有响应于RC定时器的第一控制端子，以便响应于激活耦合到RC-输出端的输出的装置的静电放电（ESD）事件而使上拉装置偏置，定时器下拉装置具有第二控制端子，一方面，该控制端子处于基本上不确定的状态（即，第二控制端子可以是“1”，“0”或一些其它可能在或不在其内的电压在ESD事件期间的“1”和“0”之间的电压范围。

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