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    • 51. 发明授权
    • Semiconductor pressure sensor and manufacturing method therefof
    • 半导体压力传感器及其制造方法
    • US06218717B1
    • 2001-04-17
    • US09231799
    • 1999-01-15
    • Inao ToyodaHiroaki TanakaNoboru Endo
    • Inao ToyodaHiroaki TanakaNoboru Endo
    • H01L2982
    • G01L9/0054G01L9/0042
    • A semiconductor pressure sensor includes a semiconductor substrate having a diaphragm portion. A diaphragm formation region including the diaphragm portion is electrically insulated from a peripheral region therearound. Voltage is applied to the diaphragm formation region via a pad and a wire both formed on a surface of the semiconductor substrate, for fixing a potential of the diaphragm formation region when the sensor is put in an operating state. The fixed potential is set to be equal to or higher than a maximum potential of a gauge diffusion resistive layer formed in the diaphragm formation region. As a result, even when the maximum potential of the gauge diffusion resistive layer is a power supply voltage, it can be prevented that current leaks from the gauge diffusion resistive layer.
    • 半导体压力传感器包括具有隔膜部分的半导体基板。 包括隔膜部分的隔膜形成区域与其周边区域电绝缘。 电压通过在半导体基板的表面上形成的焊盘和导线施加到隔膜形成区域,用于在传感器处于工作状态时固定隔膜形成区域的电位。 固定电位被设定为等于或高于形成在隔膜形成区域中的量规扩散电阻层的最大电位。 结果,即使当量规扩散电阻层的最大电位是电源电压时,也可以防止电流从量规扩散电阻层泄漏。
    • 53. 发明授权
    • Curable liquid resin composition
    • 可固化液体树脂组合物
    • US6048953A
    • 2000-04-11
    • US000474
    • 1998-02-03
    • Miki KawashimaKunio HoriuchiHiroaki Tanaka
    • Miki KawashimaKunio HoriuchiHiroaki Tanaka
    • C08F265/06C08L55/00C09D4/02C09D4/06C09D11/10C09D155/00C08F220/10C08F220/18
    • C09D155/005C08F265/06C08L55/005C09D11/101C09D4/06
    • A curable liquid resin composition containing 100 parts by weight of the following (meth)acrylic liquid resin (A) and 1 to 1,000 parts by weight of a (meth)acrylic monomer (B) having an unsaturated double bond in its molecule and having a number average molecular weight of 1,000 or less, the (meth)acrylic liquid resin (A) being a liquid resin which is obtained by polymerizing monomers containing an alkyl (meth)acrylate monomer (a-1-1) of the formula (1),CH.sub.2 C(R.sup.1)COO--R.sup.2 (1)wherein R.sup.1 is a hydrogen atom or CH.sub.3 and R.sup.2 is an alkyl group,and/or an alkylene glycol (meth)acrylate monomer (a-1-2) of the formula (2),CH.sub.2 .dbd.C(R.sup.1)COO(C.sub.n H.sub.2n O).sub.m R.sup.3(2)wherein R.sup.1 is a hydrogen atom or CH.sub.3, R.sup.3 is an alkyl group or a phenyl group, n is an integer of 1 to 3, and m is an integer of 3 to 25, and other polymerizable vinyl monomer (a-2), an average of molecular weights of all the monomers being 100 to 1,500, the liquid resin having a number average molecular weight of 10,000 to 200,000 and a viscosity of 1 to 10,000 poise (measured at 50.degree. C.), or a modified product of the above liquid resin, the curable liquid resin composition can form a film as a film-forming material or as a resin for an adhesive without using a solvent and give a cured film.
    • PCT No.PCT / JP97 / 01871 Sec。 371日期1998年2月3日 102(e)1998年2月3日PCT 1997年6月2日PCT公布。 出版物WO97 / 46601 日期1997年12月11日含有100重量份以下(甲基)丙烯酸系液态树脂(A)和1〜1000重量份具有不饱和双键的(甲基)丙烯酸系单体(B)的固化性液态树脂组合物 其分子的数均分子量为1000以下,作为液状树脂的(甲基)丙烯酸系液态树脂(A)是将含有(甲基)丙烯酸烷基酯单体(a-1-1)的单体 式(1),其中R1是氢原子或CH3,R2是烷基的CH2(R)COO-R2(1),和/或亚烷基二醇(甲基)丙烯酸酯单体(a-1-2) 式(2)中,CH 2 = C(R 1)COO(C n H 2n O)m R 3(2)其中R 1为氢原子或CH 3,R 3为烷基或苯基,n为1〜3的整数, m为3〜25的整数,其它的聚合性乙烯基单体(a-2),所有单体的分子量平均为100〜1500,数均分子量为10,000〜200,000的液态树脂和vi 1〜10,000泊(50℃测定)的光泽度或上述液态树脂的改性物,可固化型液态树脂组合物可以形成作为成膜材料的膜或粘合剂用树脂,而不使用 溶剂,得到固化膜。
    • 57. 发明授权
    • Method and apparatus for performing exception processing routine in
pipeline processing
    • 在流水线处理中执行异常处理程序的方法和装置
    • US5938762A
    • 1999-08-17
    • US726753
    • 1996-10-07
    • Hiroshi HayakawaHarutsugu FukumotoHiroaki Tanaka
    • Hiroshi HayakawaHarutsugu FukumotoHiroaki Tanaka
    • G06F9/32G06F9/38G06F9/46
    • G06F9/322G06F9/3861
    • An information processing apparatus and method, such that when an interruption occurs in a microprocessor, an exception processing sequence control is started, a program condition of an interrupted program and an address of the interrupted program are saved in a RAM, a program address of a jump instruction is read out from an exception processing generating source and is set in a program counter, and the exception processing sequence control is stopped. Thereafter, a normal processing sequence control is started, the jump instruction is read out from a ROM, an address of an exception processing vector is calculated according to the jump instruction, the exception processing vector is read out from the ROM, a branch address of an exception processing routine indicated by the exception processing vector is set in the program counter, and an operation state of the microprocessor is branched to the exception processing routine. Thereafter, the normal processing sequence control is stopped, and the exception processing routine is performed in the exception processing sequence control.
    • 一种信息处理装置和方法,当在微处理器中发生中断时,开始异常处理顺序控制,中断程序的程序条件和中断程序的地址被保存在RAM中,程序地址 从异常处理生成源读出跳转指令,并将其设置在程序计数器中,并停止异常处理顺序控制。 此后,开始通常的处理顺序控制,从ROM读出跳转指令,根据跳转指令计算出异常处理向量的地址,从ROM中读出异常处理向量,分支地址 在程序计数器中设置由异常处理向量指示的异常处理程序,并且将微处理器的操作状态分支到异常处理程序。 此后,停止正常处理顺序控制,并且在异常处理顺序控制中执行异常处理程序。
    • 60. 发明授权
    • Logic operation circuit and carry look ahead adder
    • 逻辑运算电路并携带前瞻加法器
    • US5877973A
    • 1999-03-02
    • US806213
    • 1997-02-26
    • Koji KatoHarutsugu FukumotoHiroaki Tanaka
    • Koji KatoHarutsugu FukumotoHiroaki Tanaka
    • G06F7/50G06F7/506G06F7/508
    • G06F7/506G06F7/508
    • An 8-bit CLA adder is constructed for inputting 4 lower bits a3:0,b3:0 and 4 upper bits a7:4,b7:4 of two input signals to the two 4-bit full adders 2,12 and a carry c-1 to the lowest bit the full adder of the first-stage 2 to generate carries c3,c7 correspondint to the third and seventh bit of the input signals from a carry generation signal g7:0 and a carry propagation signal p7:0 generated by the both adders 2,12 and the carry c-1. The full adder of the second-stage 12 is constructed to add the 4 upper bits a7:4,b7:4 with setting a carry-in as 0 so as to generate a temporary summing signal sz7:4. A logical circuit 14 generates a true sum of 4 upper bits from a carry c3 to the third bit to the forth bit, a temporary sum sz7:4 and a carry propagation signal p7:4 generated by the full adder of the second-stage 12.
    • 一个8位CLA加法器被构造用于将两个输入信号的4个低位位a3:0,b3:0和4个高位位a7:4,b7:4输入到两个4位全加器2,12和一个进位c -1到第一级2的全加器的最低位,以产生载波c3,c7,对应于来自进位产生信号g7:0的输入信号的第三和第七位以及由...生成的进位传播信号p7:0 两个加法器2,12和进位c-1。 第二级12的全加器被构造为通过将进位设置为0来添加4个高位位a7:4,b7:4,以产生临时求和信号sz7:4。 逻辑电路14产生从进位c3到第三位到第四位的4个高位的真和,由第二级12的全加器产生的临时和sz7:4和进位传播信号p7:4 。