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    • 51. 发明申请
    • METHODS OF FABRICATING A SEMICONDUCTOR SUBSTRATE FOR REDUCING WAFER WARPAGE
    • 制造半导体基板以减少波纹的方法
    • US20070004211A1
    • 2007-01-04
    • US11530218
    • 2006-09-08
    • Won KimYoung-Wook ParkJeong-Do Ryu
    • Won KimYoung-Wook ParkJeong-Do Ryu
    • H01L21/461H01L21/302
    • H01L21/0209H01L21/302H01L21/6708H01L21/76895H01L27/10844H01L27/10882H01L29/7842
    • Methods of fabricating a semiconductor device can include forming at least one layer on a first and a second side of a semiconductor substrate. Portions of the at least one layer may be removed on the first side of the semiconductor substrate to form a pattern of the at least one layer on the first side of the substrate while the at least one layer is maintained on the second side of the substrate. A capping layer can be formed on the pattern of the at least one layer on the first side of the substrate and on the at least one layer on the second side of the semiconductor substrate. The capping layer can be removed on the second side of the semiconductor substrate, thereby exposing the at least one layer on the second side of the substrate while maintaining the capping layer on the first side of the substrate. The at least one layer can be removed on the second side of the semiconductor substrate, while the capping layer and the pattern of the at least one layer is maintained on the first side of the semiconductor substrate. A portion of the capping layer can be removed on the first side of the semiconductor substrate.
    • 制造半导体器件的方法可以包括在半导体衬底的第一和第二侧上形成至少一个层。 可以在半导体衬底的第一侧上去除至少一个层的部分,以在衬底的第一侧上形成至少一层的图案,同时将至少一层保持在衬底的第二面上 。 可以在衬底的第一侧上的至少一层的图案和半导体衬底的第二侧上的至少一个层上形成覆盖层。 可以在半导体衬底的第二侧上去除覆盖层,从而在衬底的第二侧上保持覆盖层的同时暴露衬底的第二面上的至少一个层。 可以在半导体衬底的第二侧上移除至少一个层,同时覆盖层和至少一层的图案保持在半导体衬底的第一侧上。 可以在半导体衬底的第一侧上去除覆盖层的一部分。
    • 52. 发明申请
    • Plasma display and driving method thereof
    • 等离子体显示及其驱动方法
    • US20060164358A1
    • 2006-07-27
    • US11319731
    • 2005-12-29
    • Won YoonYang LeeWon KimJang Cho
    • Won YoonYang LeeWon KimJang Cho
    • G09G3/36
    • G09G3/2965G09G3/2942G09G2310/066G09G2360/16
    • A plasma display panel for adaptively reducing load effect and improving luminescence efficiency and discharge efficiency, and a driving method thereof. A plasma display panel includes a capacitive load; a source capacitor; a sustain voltage source to generate a sustain voltage; a first inductor formed on a first current path where a current flows from the capacitive load to the source capacitor; a second inductor formed on a second current path where a current flows from the source capacitor to the capacitive load; a switch configuration and switch control circuit that controls the switching operations of the switch configuration such that at least two discharges may occur during one sustain pulse cycle.
    • 一种用于自适应地降低负载效应并提高发光效率和放电效率的等离子体显示面板及其驱动方法。 等离子体显示面板包括容性负载; 源电容器; 维持电压源,产生维持电压; 形成在电流从电容性负载流向源电容器的第一电流路径上的第一电感器; 形成在第二电流路径上的第二电感器,其中电流从源电容器流向电容性负载; 开关配置和开关控制电路,其控制开关配置的开关操作,使得在一个维持脉冲周期期间可能发生至少两次放电。
    • 53. 发明申请
    • Fully packed capillary electrophoretic separation microchips with self-assembled silica colloidal particles in microchannels and their preparation methods
    • 在微通道中具有自组装二氧化硅胶体颗粒的完全填充的毛细管电泳分离微芯片及其制备方法
    • US20060147344A1
    • 2006-07-06
    • US11241364
    • 2005-09-30
    • Chong AhnSeHwan LeeJongman ParkShigeyoshi HoriikeWon Kim
    • Chong AhnSeHwan LeeJongman ParkShigeyoshi HoriikeWon Kim
    • G01N30/02
    • G01N30/02G01N27/44717G01N30/6095
    • A novel CEC column preparation method for various forms of CEC separation using selectively or fully packed microchannels with self-assembled silica colloidal particles is disclosed. The method relies on the three dimensional uniform silica colloidal packing through selective regions or whole channels resulting in uniform EOF and reproducibility. The fully packed capillary electrophoretic separation microchip is inherently suited for a handheld system since it exploits uniquely fully packed separation channels to achieve better separation efficiency and stability. The fully packed capillary electrophoretic separation microchip can be easily fabricated using low-cost, rapid manufacturing techniques, and can provide high performance for CEC separation with various chromatographic stationary support packing, functionalized surface of packed beads. The fully packed microchannels with self-assembled silica colloidal particles can be applied for preparation of a built-in submicron filter. Embodiments of the present invention address a significant challenge in the development of disposable CEC microchips, specifically, providing a reliable solution for preparation of the CEC separation column in a device that may be immediately applied for a variety of CEC applications.
    • 公开了一种用于使用具有自组装二氧化硅胶体颗粒的选择性或完全包装的微通道的各种形式的CEC分离的新型CEC柱制备方法。 该方法依赖于通过选择性区域或全部通道的三维均匀二氧化硅胶体填充,导致均匀的EOF和再现性。 完全包装的毛细管电泳分离微芯片本质上适用于手持系统,因为它利用独特的完全包装的分离通道以实现更好的分离效率和稳定性。 完全包装的毛细管电泳分离微芯片可以使用低成本,快速的制造技术容易地制造,并且可以为各种色谱固定支持填料,填充珠的功能化表面的CEC分离提供高性能。 具有自组装二氧化硅胶体颗粒的完全包装的微通道可用于制备内置亚微米过滤器。 本发明的实施例解决了一次性CEC微芯片开发中的重大挑战,具体地说,提供了可以立即应用于各种CEC应用的装置中CEC分离柱的制备的可靠解决方案。
    • 58. 发明申请
    • Domestic appliance having stackable structure
    • 家用电器具有堆叠结构
    • US20060010934A1
    • 2006-01-19
    • US11155517
    • 2005-06-20
    • Won Kim
    • Won Kim
    • B08B3/12D06F29/00
    • D06F39/12
    • A domestic appliance having a stackable structure for stably vertically stacking with other domestic appliances. The domestic appliances include a first domestic appliance and a second domestic appliance placed on the first domestic appliance. A first connecting member is installed on an outer surface of the first domestic appliance, for connecting the first domestic appliance to the second domestic appliance. A second connecting member sets a position of the first and second domestic appliances relative to each other when the first connecting member is connected to the second domestic appliance.
    • 一种具有可堆叠结构的家用电器,用于与其他家用电器稳定地垂直堆叠。 家用电器包括家用电器第一台和第一台家用电器。 第一连接构件安装在第一家用电器的外表面上,用于将第一家用电器连接到第二家用电器。 当第一连接构件连接到第二家用电器时,第二连接构件设定第一和第二家用电器相对于彼此的位置。
    • 60. 发明授权
    • Galois field multiplier array for use within a finite field arithmetic unit
    • 用于有限域运算单元内的伽罗瓦域乘法器阵列
    • US07403964B2
    • 2008-07-22
    • US10459988
    • 2003-06-12
    • Joshua PortenWon KimScott D. JohnsonJohn R. Nickolls
    • Joshua PortenWon KimScott D. JohnsonJohn R. Nickolls
    • G06F15/00H03M13/00
    • G06F7/724
    • A Galois field multiplier array includes a 1st register, a 2nd register, a 3rd register, and a plurality of multiplier cells. The 1st register stores bits of a 1st operand. The 2nd register stores bits of a 2nd operand. The 3rd register stores bits of a generating polynomial that corresponds to one of a plurality of applications (e.g., FEC, CRC, Reed Solomon, et cetera). The plurality of multiplier cells is arranged in rows and columns. Each of the multiplier cells outputs a sum and a product and each cell includes five inputs. The 1st input receives a preceding cell's multiply output, the 2nd input receives at least one bit of the 2nd operand, the 3rd input receives a preceding cell's sum output, a 4th input receives at least one bit of the generating polynomial, and the 5th input receives a feedback term from a preceding cell in a preceding row. The multiplier cells in the 1st row have the 1st input, 3rd input, and 5th input set to corresponding initialization values in accordance with the 2nd operand.
    • 伽罗瓦域倍增器阵列包括1 寄存器,第二寄存器,第三寄存器和多个乘法器单元。 1&lt; ST&gt;寄存器存储1&lt; ST&gt;操作数的位。 2 寄存器存储第2个操作数的位。 3 寄存器存储对应于多个应用中的一个应用(例如,FEC,CRC,Reed Solomon等)的生成多项式的比特。 多个乘法器单元被排列成行和列。 每个乘法器单元输出和和乘积,并且每个单元包括五个输入。 1 输入接收前一个单元的乘法输出,第二个输入端接收第二个操作数的至少一位,3个< SUP> rd 输入接收前一个单元的和输出,第4个输入接收生成多项式的至少一个位,并且第5个输入接收一个 来自前一行中的前一个单元格的反馈项。 1 行中的乘法器单元具有1 输入,3 输入和5 输入 根据第2操作数设置为相应的初始化值。