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1. 发明授权

US07403964B2 Galois field multiplier array for use within a finite field arithmetic unit 有权
标题翻译：用于有限域运算单元内的伽罗瓦域乘法器阵列
公开(公告)号：US07403964B2
公开(公告)日：2008-07-22
申请号：US10459988
申请日：2003-06-12
申请人： Joshua Porten , Won Kim , Scott D. Johnson , John R. Nickolls
发明人： Joshua Porten , Won Kim , Scott D. Johnson , John R. Nickolls
IPC分类号： G06F15/00 , H03M13/00
CPC分类号： G06F7/724
摘要： A Galois field multiplier array includes a 1st register, a 2nd register, a 3rd register, and a plurality of multiplier cells. The 1st register stores bits of a 1st operand. The 2nd register stores bits of a 2nd operand. The 3rd register stores bits of a generating polynomial that corresponds to one of a plurality of applications (e.g., FEC, CRC, Reed Solomon, et cetera). The plurality of multiplier cells is arranged in rows and columns. Each of the multiplier cells outputs a sum and a product and each cell includes five inputs. The 1st input receives a preceding cell's multiply output, the 2nd input receives at least one bit of the 2nd operand, the 3rd input receives a preceding cell's sum output, a 4th input receives at least one bit of the generating polynomial, and the 5th input receives a feedback term from a preceding cell in a preceding row. The multiplier cells in the 1st row have the 1st input, 3rd input, and 5th input set to corresponding initialization values in accordance with the 2nd operand.
摘要翻译：伽罗瓦域倍增器阵列包括1 寄存器，第二寄存器，第三寄存器和多个乘法器单元。 1＆lt; ST＆gt;寄存器存储1＆lt; ST＆gt;操作数的位。 2 寄存器存储第2个操作数的位。 3 寄存器存储对应于多个应用中的一个应用（例如，FEC，CRC，Reed Solomon等）的生成多项式的比特。多个乘法器单元被排列成行和列。每个乘法器单元输出和和乘积，并且每个单元包括五个输入。 1 ^{输入接收前一个单元的乘法输出，第二个输入端接收第二个操作数的至少一位，3个< SUP> rd 输入接收前一个单元的和输出，第4个输入接收生成多项式的至少一个位，并且第5个输入接收一个来自前一行中的前一个单元格的反馈项。 1 ^{行中的乘法器单元具有1 ^{输入，3 输入和5 输入根据第2操作数设置为相应的初始化值。}}}

2. 发明授权

US07343472B2 Processor having a finite field arithmetic unit utilizing an array of multipliers and adders 有权
标题翻译：处理器具有利用乘法器和加法器阵列的有限域运算单元
公开(公告)号：US07343472B2
公开(公告)日：2008-03-11
申请号：US10459907
申请日：2003-06-11
申请人： Joshua Porten , Won Kim , Scott D. Johnson , John R. Nickolls
发明人： Joshua Porten , Won Kim , Scott D. Johnson , John R. Nickolls
IPC分类号： G06F15/76 , G06F9/30 , G06F9/40 , G06F7/00 , G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44 , H03M13/00
CPC分类号： G06F7/724 , G06F9/30018
摘要： A processor includes an instruction memory, arithmetic logic unit, finite field arithmetic unit, at least one digital storage device, and an instruction decoder. The instruction memory temporarily stores an instruction that includes at least one of: an operational code, destination information, and source information. The instruction decoder is operably coupled to interpret the instruction to identify the arithmetic logic unit and/or the finite field arithmetic unit to perform the operational code of the corresponding instruction. The instruction decoder then identifies at least one destination location within the digital storage device based on the destination information contained within the corresponding instruction. The instruction decoder then identifies at least one source location within the digital storage device based on the source information of the corresponding instruction. When the finite field arithmetic unit is to perform the operational code, it performs a finite field arithmetic function upon data stored in the at least one source location in accordance with the operational code and provides the resultant to the destination location.
摘要翻译：处理器包括指令存储器，算术逻辑单元，有限域算术单元，至少一个数字存储设备和指令解码器。指令存储器临时存储包括以下操作代码，目的地信息和源信息中的至少一个的指令。指令解码器可操作地耦合以解释用于识别算术逻辑单元和/或有限域运算单元的指令以执行相应指令的操作代码。然后，指令解码器基于包含在相应指令内的目的地信息来识别数字存储设备内的至少一个目的地位置。然后，指令解码器基于相应指令的源信息识别数字存储设备内的至少一个源位置。当有限域算术单元要执行操作代码时，它根据操作代码对存储在至少一个源位置的数据执行有限域算术功能，并将结果提供给目的地位置。

3. 发明授权

US06249881B1 Method for enabling and servicing critical interrupts while running an interrupt based debug monitor 失效
标题翻译：在运行基于中断的调试监视器时启用和维护关键中断的方法
公开(公告)号：US06249881B1
公开(公告)日：2001-06-19
申请号：US08884200
申请日：1997-07-01
申请人： Joshua Porten , Amir Bar-Niv
发明人： Joshua Porten , Amir Bar-Niv
IPC分类号： G06F1100
CPC分类号： G06F11/362
摘要： A method for debugging an application on an embedded processor using a debug monitor service routine (debug ISR) and allowing critical interrupts to be transparently serviced is provided. The method enters and runs a debug monitor service routine transparently such that the application program being debugged is unaware of the monitor. A debug interrupt is completely transparent to the application software that runs on the embedded processor and is therefore non-maskable. In addition, when entering the debug ISR, shadow registers and the global interrupt disable bit (if they exist) are not be altered, which preserves the monitor's transparency to the application. Once the debug monitor is entered, a context save may be performed if needed and the monitor may proceed to enable interrupts if necessary. Using a second global interrupt enable/disable mechanism, distinct from, and in series with, the normal global interrupt enable/disable mechanism, the debug ISR can decide to enable or disable global interrupts. If an interrupt does occur while the debug monitor is running and interrupts are still enabled, that interrupt is serviced transparently to the debug monitor. Once the debugger releases the monitor it may exit, in a single atomic operation which avoids confusing a regular return from interrupt with a debug return from interrupt. If the debug monitor does not need to do a context save upon entering the debug ISR, the processor may be set to operate in mode where interrupts are not disabled upon entry into the debug ISR. However, the monitor may always opt to disable interrupts once the debug ISR is running. Upon exiting the debug ISR, the second global interrupt enable/disable mechanism is set to enable interrupts, thereby preserving the status of the normal global interrupt enable/disable mechanism.
摘要翻译：提供了一种使用调试监视器服务程序（调试ISR）调试嵌入式处理器上的应用程序并允许关键中断被透明地服务的方法。该方法透明地输入和运行调试监视器服务程序，使得被调试的应用程序不知道监视器。调试中断对于在嵌入式处理器上运行的应用软件是完全透明的，因此是不可屏蔽的。此外，当进入调试ISR时，影子寄存器和全局中断禁用位（如果存在）不被更改，这保留了监视器对应用程序的透明度。一旦输入调试监视器，如果需要，可以执行上下文保存，如果需要，监视器可以继续执行中断。使用与正常全局中断使能/禁止机制不同的一个第二个全局中断使能/禁止机制，调试ISR可以决定启用或禁用全局中断。如果在调试监视器运行并且中断仍然使能的情况下发生中断，则该中断将对调试监视器透明地进行服务。一旦调试器释放监视器，它就可能退出一个单一的原子操作，避免了中断的定期返回与中断的调试返回。如果调试监视器在进入调试ISR时不需要执行上下文保存，则处理器可能被设置为在进入调试ISR时不中断中断的模式下工作。但是，一旦调试ISR运行，监视器可能总是选择禁用中断。退出调试ISR后，第二个全局中断使能/禁止机制被设置为允许中断，从而保持正常全局中断使能/禁止机制的状态。

4. 发明申请

US20170076081A1 METHOD AND APPARATUS FOR SECURING USER OPERATION OF AND ACCESS TO A COMPUTER SYSTEM 审中-公开
标题翻译：用于保护用户操作和访问计算机系统的方法和装置
公开(公告)号：US20170076081A1
公开(公告)日：2017-03-16
申请号：US14963183
申请日：2015-12-08
申请人： Sofin Raskin , Corie Duchateau , Joshua Porten , Matt Ouellette
发明人： Sofin Raskin , Corie Duchateau , Joshua Porten , Matt Ouellette
IPC分类号： G06F21/34 , H04L9/32 , H04L29/06 , G06F13/42 , G06F21/44 , G06F9/44
CPC分类号： G06F21/34 , G06F9/4401 , G06F13/4282 , G06F21/44 , G06F21/575 , H04L9/3234 , H04L9/3247 , H04L63/0442 , H04L63/0861 , H04L63/12
摘要： The present invention provides methods and apparatuses for computer system security. According to certain aspects, embodiments of the invention comprise a portable storage device that, when attached, “unlocks” a computer system, such as a desktop, laptop, tablet computer running a conventional operating system such as Windows, thereby creating added security. More particularly, embodiments of the invention use a standard USB memory stick as an “ignition key” to unlock and operate a PC, tablet or other computer system. The ignition key can be required to boot the computer, utilize peripheral devices, ports, network connections, a keyboard and/or a mouse of the computer system, and limit access to certain parts of computer. According to further aspects, in these and other embodiments, the invention is implemented using a modified BIOS that prevents a computer from fully booting into an operational state until verifying the presence of, and information stored on the “ignition key” connected to the computer.
摘要翻译：本发明提供了计算机系统安全性的方法和装置。根据某些方面，本发明的实施例包括便携式存储装置，当附接时，“解锁”计算机系统，例如运行诸如Windows的常规操作系统的台式机，笔记本电脑，平板电脑，从而创造额外的安全性。更具体地，本发明的实施例使用标准USB记忆棒作为“点火钥匙”来解锁和操作PC，平板电脑或其它计算机系统。可能需要点火钥匙来引导计算机，利用计算机系统的外围设备，端口，网络连接，键盘和/或鼠标，并限制对计算机某些部分的访问。根据其他方面，在这些和其他实施例中，本发明使用修改的BIOS来实现，该修改的BIOS防止计算机完全引导到操作状态，直到验证存储在连接到计算机的“点火钥匙”的存在和信息。

5. 发明授权

US5996059A System for monitoring an execution pipeline utilizing an address pipeline in parallel with the execution pipeline 失效
标题翻译：用于使用与执行流水线并行的地址管线监视执行管线的系统
公开(公告)号：US5996059A
公开(公告)日：1999-11-30
申请号：US886520
申请日：1997-07-01
申请人： Joshua Porten , Amir Bar-Niv
发明人： Joshua Porten , Amir Bar-Niv
IPC分类号： G06F9/38 , G06F11/00 , G06F11/34 , G06F9/30
CPC分类号： G06F9/3867 , G06F11/3466 , G06F11/006
摘要： An address pipeline includes a sequence of registers for storing the memory addresses of instructions currently being processed within the different stages of an execution pipeline. In parallel with the execution pipeline, the address pipeline advances the corresponding memory addresses as the instructions are advanced through the execution pipeline. Address pipelining allows the programmer of a pipelined processor to understand the otherwise hidden operation of a pipelined processor by giving the programmer means to track instructions through the pipeline. In addition, the address pipeline includes an instruction status register for indicating whether an instruction at any given stage of the pipeline has been executed and a program counter address breakpoint register for storing the address of the instruction that actually triggers a breakpoint.
摘要翻译：地址流水线包括用于存储在执行流水线的不同阶段当前正在处理的指令的存储器地址的寄存器序列。与执行流水线并行，当指令通过执行流水线进行时，地址管线将前进相应的存储器地址。地址流水线允许流水线处理器的编程器通过给编程器装置跟踪通过流水线的指令来理解流水线处理器的另外隐藏的操作。此外，地址管线包括指示状态寄存器，用于指示是否已经执行了流水线的任何给定阶段的指令，以及用于存储实际触发断点的指令的地址的程序计数器地址断点寄存器。

6. 发明授权

US07313583B2 Galois field arithmetic unit for use within a processor 有权
标题翻译：用于处理器内的伽罗瓦域算术单元
公开(公告)号：US07313583B2
公开(公告)日：2007-12-25
申请号：US10460599
申请日：2003-06-12
申请人： Joshua Porten , Won Kim , Scott D. Johnson , John R. Nickolls
发明人： Joshua Porten , Won Kim , Scott D. Johnson , John R. Nickolls
IPC分类号： G06F15/00 , H03M13/00
CPC分类号： G06F7/724
摘要： A Galois field arithmetic unit includes a Galois field multiplier section and a Galois field adder section. The Galois field multiplier section includes a plurality of Galois field multiplier arrays that perform a Galois field multiplication by multiplying, in accordance with a generating polynomial, a 1st operand and a 2nd operand. The bit size of the 1st and 2nd operands correspond to the bit size of a processor data path, where each of the Galois field multiplier arrays performs a portion of the Galois field multiplication by multiplying, in accordance with a corresponding portion of the generating polynomial, corresponding portions of the 1st and 2nd operands. The bit size of the corresponding portions of the 1st and 2nd operands corresponds to a symbol size of symbols of a coding scheme being implemented by the corresponding processor.
摘要翻译：伽罗瓦域算术单元包括伽罗瓦域乘法器部分和伽罗瓦域加法器部分。伽罗瓦域乘法器部分包括多个伽罗瓦域乘法器阵列，其通过根据生成多项式乘以第1和第2操作数和第2和/ >操作数。 1 ^{和 nd / / SUP>操作数的位大小对应于处理器数据路径的位大小，其中Galois域乘法器阵列中的每一个执行Galois的一部分根据生成多项式的对应部分乘以1＆lt; S＆gt;和2＆lt; nd＆gt;操作数的对应部分进行场乘法运算。第1和第2和第2操作数的对应部分的位大小对应于由对应的处理器实现的编码方案的符号的符号大小。}

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